JP2005309622A - Data storage device, data storage control device, data storage control method and data storage control program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To store all data in a memory consisting of a plurality of memory banks and read a plurality of intended data simultaneously without placing a burden on hardware. <P>SOLUTION: When all data are stored in a memory 10 consisting of a plurality of memory banks, a data storage processing part 20 makes an initial arrangement by storing data among access candidates in the same bank based on an access pattern showing a plurality of intended data to be read simultaneously. A data read and storage processing part 30 stores data of the pixels read from a bank address in a position of the write word line address and the write bit line address plus 1 of a bank address of the read bank address minus 1 for all data of the initial arrangement, and, while incrementing the word line address and the bit line address, reads data of the pixels on the word line address and the bit line address by the number of banks. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a data storage device, a data storage control device, a data storage control method, and a data storage control program that store all data in a memory composed of a plurality of memory banks and simultaneously read out a desired plurality of data.

  As shown in FIG. 23, the semiconductor memory has a structure in which the memory cell MC is accessed by designating the word line WL and the bit line BL, and is located at a position where the activated one word line and the bit line intersect. Data stored in the memory cell MC is read out.

  In a semiconductor memory having such a structure, data of a plurality of word lines share the same bit line. Therefore, when a plurality of word lines WL1 and WL2 are designated as shown in FIG. Since it is broken, data on different word lines cannot be accessed simultaneously.

  On the other hand, it is possible to simultaneously read data from independent memory banks. As shown in FIG. 25, the memory is divided into n memory banks BK0 to BKn-1, and different addresses are designated for the respective memory banks. Thus, data on a plurality of word lines can be accessed simultaneously, but data on different word lines in the memory bank cannot be accessed simultaneously. That is, data stored on the same word line from each memory bank can be read simultaneously, and data stored on different word lines in the same memory bank cannot be read simultaneously.

  Here, the memory bank refers to a memory unit having a single word address selected in a memory composed of a plurality of word lines and a plurality of bit lines.

  Conventionally, processing such as pattern recognition of image data has been performed by recognizing a specific data array included in input data.

  Conventionally, processing such as pattern recognition and motion detection of image data has been performed by recognizing a specific data array included in input data.

  For example, a buffer memory that can store several lines of image data and output in pixel units, a data processor that includes multiple processor elements that can process several bits of width data, and that can process data simultaneously in multiple processor elements, and matching A control information memory for storing reference data and control data, and each processor element of the data processor selects a group of image data in a matrix centered on a target pixel addressed to itself among the image data output from the buffer memory. Then, it is binarized using a threshold value, converted into target data divided into serial array bit widths that can be processed by the processor element, and it is determined whether it matches the reference data in the control information memory in the same format. (For example, refer to Patent Document 1).

  Also, in the field of moving image processing, motion, that is, the motion direction and size (or speed) of an object in a temporally different image is used. For example, a motion compensation frame in high-efficiency encoding of an image Motion is used for inter-coding, parameter control by motion in a television noise reduction device using an inter-frame time domain filter, and the like. A block matching method is known as a motion detection method for obtaining motion.

In the motion detection method for detecting motion in an image signal, the applicant of the present application generates (a) an integrated value table by a matching method for each relatively large block obtained by dividing an entire screen or a screen into a plurality of blocks. Using the integrated value table, extracting one or a plurality of candidate vectors for each relatively large block obtained by dividing the entire one screen or a plurality of one screen, and (b) matching only the candidate vectors. A two-step motion detection method has been proposed which includes a step of detecting a motion vector for each pixel or each relatively small block. In this two-step motion detection method, any two or more pixel data in an image are simultaneously read out in the two-step process of representative point matching and vector assignment in which image motion detection is performed by two-step representative point matching. There is a need (see, for example, Patent Document 2).
JP 2003-203236 A JP 2001-61152 A

By the way, for example, as shown in FIG. 26, when a pixel to be accessed simultaneously has a pattern of 4 pixels as shown in FIG. 26, the minimum necessary for storing a desired plurality of pixels in another bank as shown in FIG. The number of banks is 4. If there is a vertical (h pixel) × horizontal (w pixel) search area SR, and there are n candidates to be accessed, there are _{(h × w)} C _(n) types. Each of these is called an access pattern. As an access pattern, a combination of any number of access candidates in the search area is possible. In the example of FIG. 26, one of the _{16 × 8} C _four combinations is shown.

  However, in order to cope with the movement of the pattern to be accessed in the scan order, it is necessary to devise a storage method other than the access pixel in the initial arrangement.

  For example, as shown in FIG. 28, it is necessary to store pixels between access candidates in a separate bank for each pixel, or store pixels between access candidates in the same bank as shown in FIG.

  When the pixels between the access candidates are stored in the same bank, as shown in FIGS. 30A, 30B, and 30C, even if the pattern moves in the scan order, it is possible to simultaneously access a certain section. Become.

  However, as shown in FIG. 31, if the movement of the access pattern exceeds between access pixels, the pixels in the same bank are simultaneously accessed.

  Here, the numbers in FIG. 27 to FIG. 31 represent the bank address of the storage destination.

  In order to access this data simultaneously, it is stored either in another bank or on the same word line. Depending on the pattern, simultaneous access may be possible if the storage location is selected appropriately. However, in order to allow simultaneous access to any pattern, the bank is divided so finely that one bank is composed of only one word line. There is a need. However, the finer the number of banks, the larger the number of banks. As the number of banks increases, the following problems occur.

  In other words, since different addresses are assigned to each bank, the address bus becomes enormous.

  In addition, since the number of decoders and selectors required is the same as the number of banks, the chip area increases.

  In addition, power consumption increases because multiple banks operate simultaneously.

  Furthermore, if the number of data for one word line is increased, the word line becomes longer and it takes time to access the data for one word line.

  Thus, in a semiconductor memory, if only one word line is configured per bank, data can be read simultaneously. However, if the amount of data to be stored is enormous, the hardware is burdened, which is not realistic.

  Therefore, in the conventional technique, a buffer or cache for reading data and temporarily storing it is provided, and a plurality of desired data is divided into a plurality of times in time, temporarily stored in the buffer or cache, and read.

  However, when the number of desired plural data increases and the data input / output speeds up, the data read processing is delayed in time. In order to solve this problem, the number of buffers and caches to be temporarily stored has been increased. However, if the area becomes large, a burden is imposed on hardware.

  When pixels between access candidates are stored in the same bank, depending on the size of the image and the size of the search area, it may be necessary to prepare a very large bank as the final bank. This is due to the fact that the final candidate pixels and subsequent are stored in the same bank. An increase in the bank leads to an increase in the number of pixels on one word line, which causes a problem that it takes time to access each data.

  In view of the above-described conventional problems, an object of the present invention is to include a plurality of memory banks without depending on the size of an image and the size of a search area and without causing a burden on hardware. An object of the present invention is to provide a data storage device, a data storage control device, a data storage control method, and a data storage control program capable of storing all data in a memory and simultaneously reading desired plural data.

  Other objects of the present invention and specific advantages obtained by the present invention will become more apparent from the description of embodiments described below.

  When the data storage device according to the present invention distributes and stores all data in a plurality of memory banks constituting the memory, the data storage device is configured based on an access pattern indicating a plurality of desired data to be read simultaneously. The data storage processing unit that stores data between access candidates in the same bank until the final candidate, and stores the data by switching the bank at predetermined intervals after the final access pattern, and the plurality of memory banks A data read storage processing unit that reads out the data of the pixels on the word line address and the bit line address by the number of banks while incrementing the word line address and the bit line address for all the data initially arranged in the memory consisting of The data read / store processing unit includes an access pattern and the same word. It reads the data of one pixel of de line, +1 position to the last bit line address of the last word line address of the bank address of the bank address -1, and wherein storing the data of one pixel read above.

  Further, the present invention is a data storage control device for controlling writing / reading of data to / from a memory composed of a plurality of memory banks, and when all data is distributed and stored in a plurality of memory banks constituting the memory, Based on the access pattern indicating the desired multiple data to be read simultaneously, the data between the access candidates is stored in the same bank until the final access pattern candidate, and the bank is switched every predetermined cycle after the final access pattern The data storage processing unit that is initially arranged by storing data and the word line address and bit line address for all data initially arranged on the memory composed of the plurality of memory banks while incrementing the word line address Reads the pixel data on the address and bit line address by the number of banks. The data read storage processing unit reads an access pattern and data of one pixel on the same word line, and sets the final bit line address of the last word line address of the bank address of the bank address −1. The read one-pixel data is stored in a position incremented by one.

  Further, the present invention is a data storage control method for controlling writing / reading of data to / from a memory composed of a plurality of memory banks, and when all data is distributed and stored in a plurality of memory banks constituting the memory, Based on the access pattern indicating the desired multiple data to be read simultaneously, the data between the access candidates is stored in the same bank until the final access pattern candidate, and the bank is switched every predetermined cycle after the final access pattern The data is stored in an initial arrangement, and the access pattern and the data of one pixel on the same word line are read from all the data initially arranged on the memory composed of the plurality of memory banks, and the bank address-1 Position of bank address last word line address plus last bit line address Stores data of one pixel read out above, while incrementing the word line address and the bit line address, and wherein the reading the word line address, the data of the pixels on the bit line address by the number of banks.

  The present invention also provides a data storage control program for executing data storage control for storing all data in a memory composed of a plurality of memory banks and performing simultaneous reading of a desired plurality of data by a computer. Are stored in a plurality of memory banks constituting the memory, and based on the access pattern indicating the desired plurality of data to be read simultaneously, the data between the access candidates is the same until the final access pattern candidate The data is stored in the bank, and after the last access pattern, the data is stored by switching the bank every predetermined period, and the access pattern is applied to all the data initially arranged on the memory composed of the plurality of memory banks. 1 pixel data on the same word line is read out and the bank of the bank address-1 is read. The read one pixel data is stored at the position of the last word line address of the address plus 1 with respect to the last bit line address, and the word line address and bit line address are incremented while incrementing the word line address and bit line address. The pixel data is read by the number of banks.

  According to the present invention, it can be realized with the minimum necessary number of banks, and the address bus, selector, decoder, power consumption, etc. can be minimized, and desired data can be accessed simultaneously in all data.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Needless to say, the present invention is not limited to the following examples, and can be arbitrarily changed without departing from the gist of the present invention.

  The present invention is implemented by, for example, a data storage device 100 configured as shown in FIG.

  The data storage device 100 includes a plurality of banks of memory 10, a data storage control unit 20 that writes data to the memory 10, reads data from the memory 10, and controls rewrite of prime data. The data read / store control unit 30 supplies data to be stored to the memory 10 and the data storage control unit 20, and an access pattern indicating simultaneous reading of a plurality of data is supplied to the data storage control unit 20 to control operation control. Signals are supplied to the memory 10, the data storage control unit 20, and the data read / storage control unit 30.

  As shown in FIG. 2, the data storage control unit 20 includes a counter 21 for counting supplied data, a coincidence determination unit 22 for performing coincidence determination between the count output of the counter 21 and an access pattern, and the coincidence determination unit. A flag generation unit 23 that generates a flag in response to the determination output of 22, a bank address counter 24 that is incremented by the output of the counter 21, a bit line address counter 25 that is incremented by the output of the bank address counter 24, A word line address counter 26 that is incremented by the output of the bit line address counter 25 and an address generation unit 27 that generates a write address based on the outputs of the counters 24, 25, and 26. The output is the bank address counter 24 It is adapted to be applied to the fine bit line address counter 25.

  Further, as shown in FIG. 3, the data read / store control unit 30 receives a data read cycle counter 31, a bank address counter 32 incremented by the output of the cycle counter 31, and an output of the bank address counter 32. A bit line address counter 33 that is incremented, a word line address counter 34 that is incremented by the output of the bit line address counter 33, and an address generation unit that generates a write address based on the outputs of the counters 32, 33, and 34 The address is given to the bank address counter 32.

  An initial arrangement of image data in each bank in the data storage device 100 having such a configuration will be described.

As an example, as shown in FIG. 4, there is a pattern corresponding to a plurality of pixels to be accessed simultaneously for a single image, and raster scanning is performed from the upper left. Here, an example in which four pixels are simultaneously accessed using the memory 10 of four banks [bank addresses 0 to 3] will be described. An access pattern corresponding to a plurality of pixels to be accessed simultaneously is not limited to the example shown in FIG. That is, as described above, there is a vertical (h pixel) × horizontal (w pixel) search area SR, and when there are n candidates to be arbitrarily accessed, the type is _{(h × w)} C _{(n )} pieces there. Each of these is called an access pattern. As an access pattern, a combination of any number of access candidates in the search area is possible. In the example of FIG. 4, one example of _{16 × 8} C _four combinations is shown.

  Here, the number of pixels to be accessed simultaneously is referred to as the number of access candidates, and is equal to the number of candidates constituting the access pattern. In this example, since the access pattern is formed from four candidates, the number of access candidates is four.

  In the data storage device 100, when the image data is input, the data storage control unit 20 performs an initial arrangement process. If the data storage device 100 matches the access pattern, the value of the bit line address counter 25 at that time is set. When the value of the word line address counter 26 is stored as a write bit line address and a write word line address of the bank, the bank address counter 24 is incremented to store a pixel at the bank address, and when it does not match the access pattern The bit line address counter 25 is stored in the incremented bit address position in the current bank address, and when the bit line address is completed, the bit line address counter 25 is returned to 0 and the word line address counter 26 is incremented. For example, FIG. As shown, storing pixel between access candidates in the same bank. When storing one pixel at a time from the upper left of the image in the bank, the data storage control unit 20 increments the bank address every time it matches the access pattern. The banks between the access candidates are stored in the same bank. The numbers in FIG. 5 represent storage destination bank addresses.

  In other words, in the situation where the access pattern is set at the access start position, the image data matches or does not match the access pattern.

  In the data storage device 100, the data storage control unit 20 is constituted by, for example, a microprocessor, and according to a data storage control program stored in a program memory (not shown), as shown in the flowchart of FIG. The initial placement processing is performed by executing the storage processing before the pixel (initial placement processing A) and the storage processing after the last pixel of the access pattern (initial placement processing B).

  In the initial arrangement process A, according to the procedure shown in the flowchart of FIG. 7, based on an access pattern indicating a plurality of desired data to be read simultaneously, an image of pixels between access candidates for pixels before the last pixel of the access pattern Performs processing to store data in the same bank.

  That is, in the initial arrangement process A, first, the values of the bank address counter 24, the bit line address counter 25, and the word line address counter 26 are all initialized to “0” (step S1).

  Then, when image data for one pixel to be stored is input (step S2), the coincidence determination unit 22 determines whether or not it is an access location (step S3), and when the determination result is NO. Stores the image data of the pixel in the memory 10 at the write address indicated by the values of the current bank address counter 24, bit line address counter 25, and word line address counter 26 (step S6). It is determined whether data of all access pixels has been input (step S7).

  If the determination result in step S7 is NO, the bit line address counter 25 is incremented (step S8), and it is determined whether or not the value of the bit line address counter 25 has become larger than the bit line length (step). S9).

  If the determination result in step S9 is NO, the process returns to step S2 to perform storage processing for the next one pixel of image data. If the decision result in the step S9 is YES, the value of the bit line address counter 25 is reset to “0” and the word line address counter 26 is incremented (step S10), and then the step S2 Returning to step S2, the storage processing is performed for the image data for the next one pixel.

  When the determination result in step S3 is YES, that is, in the case of the access position, the values of the word line address counter 26 and the bit line address counter 25 are stored as the word line address and bit line address of the back address. From (Step S4), the bank address counter 24 is incremented, and the values of the word line address counter 26 and the bit line address counter 25 are reset to “0” (Step S5). The image data of the input pixel is stored in the memory 10 with the write address indicated by the value of “0” in the bank address counter 24, the word line address counter 25, and the bit line address counter 26.

  By repeating the processing from step S1 to step S10, data storage processing for all access pixels at the initial position is performed. When the determination result in step S7 is YES, the initial arrangement processing A is terminated.

  Then, in the next initial arrangement process B, according to the procedure shown in the flowchart of FIG. 8, for the pixels after the last pixel of the access pattern, a process of switching and storing the bank at every predetermined period, that is, every certain number of pixels is performed. Here, the predetermined cycle for switching the bank is equal to the bit line address (number of columns).

  That is, in the initial arrangement process B, first, the value of the word line address counter 26 is set to W, and the values of the counter 21, the bank address counter 24, and the bit line address counter 25 are all set to “0” (step S11). .

Here, W is a value determined by the size of the image, the size of the search area, and the number of columns.
W = number of pixels in the vertical direction of the search area × number of pixels in the horizontal direction of the image / number of columns.

  When image data for one pixel to be stored is input (step S12), it is determined whether or not the value of the counter 21 is larger than the number of pixels corresponding to a predetermined period (step S13). If the determination result is NO, the image data of the input pixel is stored in the memory 10 at the write address indicated by the values of the current bank address counter 24, bit line address counter 25, and word line address counter 26. (Step S18), it is determined whether or not all data has been input (Step S19).

  If the determination result in step S19 is NO, the bit line address counter 25 is incremented (step S20), and it is determined whether or not the value of the bit line address counter 25 has become larger than the bit line length (step). S21).

  If the determination result in step S21 is NO, the process returns to step S12 to perform storage processing for the next one pixel of image data. If the decision result in the step S21 is YES, the value of the bit line address counter 25 is reset to “0” and the word line address counter 26 is incremented (step S22). The storage process is performed for the next one pixel of image data.

  When the determination result in step S13 is YES, that is, when image data for the number of pixels corresponding to a predetermined cycle is stored in one bank, the bank address counter 24 is incremented (step S14), and the bank It is determined whether or not the value of the address counter 24 has become larger than the number of access candidates (step S15).

  If the determination result in step S15 is NO, the value of the bit line address counter 25 is reset to “0” and the value b of the word line address counter 26 is set to b−cycle / number of columns. In step S15, the process proceeds to step S18, and the image data of the input pixel is stored in the memory 10 at the write address indicated by the values of the bank address counter 24, the bit line address counter 25, and the word line address counter 26.

  If the determination result in step S15 is YES, the values of the bank address counter 24 and the bit line address counter 25 are reset to “0” and the word line address counter 26 is incremented (step S17). In step S18, the image data of the input pixel is stored in the memory 10 at the write address indicated by the values of the bank address counter 24, the bit line address counter 25, and the word line address counter 26.

  By repeating the processing from step S11 to step S22, all data storage processing is performed. When the determination result in step S19 is YES, the initial arrangement processing B is terminated.

  As described above, in the initial arrangement process B, the image data input for each pixel after the final pixel is stored while incrementing the bit line address of the final bank (the bit line address counter 25 is terminated). For example, the bit line address counter 25 is reset to 0 and the word line address counter 26 is incremented), and the bank address counter 24 and the bit line address counter 25 are reset to 0 every time a certain number of pixels are stored, that is, every predetermined period. The data is stored in the address of the word line in which the maximum pixel distance per bank that can be calculated from the image size and the search area can be stored.

  Here, in the case where the number of columns (upper limit of the bit line address) is 40 and the period is 80 pixels, an example of the initial arrangement of data is shown in FIG. The one-dimensional array state in 1 to 3 is shown in FIG. 9B, and FIG. 10 shows how data is stored in the bid line and the word line. Note that the numbers in FIG. 9A represent the bit line addresses of the storage destination banks.

  Next, how to access pixels having a desired pattern and data re-storage will be described.

  In this data storage device 100, the image data of each pixel initially arranged on the memory 10 as described above stores the pixels between access candidates in the same bank, so even if the access pattern moves in the scan order. A certain interval can be accessed at the same time, but if the movement of the access pattern exceeds the access pixels, the pixels in the same bank will be accessed at the same time. By devising it, it can cope with the movement of the access pattern.

  That is, as shown in FIGS. 11A and 11B, the access pattern and one pixel on the same word line are read out from the image data of each pixel initially arranged on the memory 10, and FIGS. As shown in (B), the data just read out is stored next to the last bit line of the last word line number of the bank address −1. That is, the first pixel of the bank next to the bank in which the access candidate last pixel exists is also read and stored next to the last bank, the write word line address, and the write word line address. Since these pixels are stored on the same word line, simultaneous access is possible.

  Here, in FIG. 11 and FIG. 12, (A) shows a two-dimensional arrangement state of data, and (B) shows a one-dimensional arrangement state in each of the memory banks 1-3. The numbers in FIGS. 11 and 12A represent the bit line addresses of the storage destination banks.

  As the search area moves, reading from each bank remains the same, but the next bank where the access candidate final pixel exists is replaced one after another, so that even if the pattern moves in the scan order, simultaneous access Can be realized.

  Here, FIGS. 13A and 13B and FIGS. 14A and 14B show how to access and how data is re-stored when the search area is moved +1 in the horizontal direction. FIGS. 15A and 15B and FIG. 16A and FIG. 16B show how to access and how data is re-stored when the search area is moved +1 in the vertical direction. FIGS. 17A and 17B and FIGS. 18A and 18B show how to access and how data is re-stored when moved +2 in the vertical direction.

  13 to 18, (A) shows a two-dimensional arrangement state of data, and (B) shows a one-dimensional arrangement state in each of the memory banks 1 to 3. The numbers in FIGS. 13 to 18A represent the bit line addresses of the storage destination banks.

  In the data storage device 100, the data read / store control unit 30 is constituted by, for example, a microprocessor, and performs access processing according to the procedure shown in the flowchart of FIG. 19 in accordance with a data storage control program stored in a program memory (not shown). .

  That is, when the data read / store control unit 30 starts the access process, first, the values of the period counter 31, the bank address counter 32a, the bank address counter 32b, the bit line address counter 33, and the word line address counter 34a are set to “0”. And the value of the word line address counter 34b is set to “W” (step S31).

  Then, the image data for one pixel is read from the bank of the bank address [a] of the memory 10 at the read address indicated by the values of the bank address counter 32a, the bit line address counter 33, and the word line address counter 34a (step S32). Further, the write word line address and write bit line address of the previous bank address [a-1] are read, and the image data for one pixel is re-stored at that position (step S33). Further, the write word line address and the write final bit line address are calculated and stored in the previous bank address [a-1] (step S34).

  Next, it is determined whether or not the bank address [a] given by the bank address counter 32a is larger than the number of access candidates (step S35).

  If the decision result in the step S35 is NO, the bank address counter 32a is incremented (step S36), and the process returns to the step S32 to perform an access process for the next bank.

  If the decision result in the step S35 is YES, the bank address [b] of the memory 10 is read by the read address indicated by the values of the bank address counter 32b, the bit line address counter 33 and the word line address counter 34b. Image data for one pixel is read out (step S37), the write word line address and write bit line address of the prepared final bank are read, and the image data for one pixel is stored again at that position (step S38). ). Further, the write word line address and the write final bit line address are calculated and stored in the final bank address (step S39).

  Next, it is determined whether or not one screen has been scanned (step S40).

  If the determination result in step S40 is NO, the value of the bank address counter 32a, that is, the bank address [a] is reset to “0” (step S41), the period counter 31 is incremented (step S42), It is determined whether or not the value of the cycle counter 31 has become larger than the number of pixels in a predetermined cycle (step S43).

  If the decision result in the step S43 is NO, the bit line address, the word line address [a] and the word line address [b] are calculated (step S49), and the process returns to the step S32 and the next bank Access processing for.

  If the determination result in step S43 is YES, the bank address counter 32b is incremented (step S44), and it is determined whether or not the bank address [b] is larger than the access candidate number (step S44). S45).

  If the decision result in the step S45 is NO, the value of the word line address counter 34b, that is, the word line address [b] is set to b−cycle / column number (step S46), and further, the bit line address, the word The line address [a] is calculated (step S47), and the process returns to step S32.

  Here, after reading r_last, it is desired to read b_first next. However, as shown in FIG. 20, after reading r_last, the read address is r_here because it is incremented in step S42. End up. Therefore, in order to set the read address to b_first, the word line address [b] is set to b−cycle / column number in step S46. In this example, since the period = 80 and the number of columns = 40, the period / number of columns is [2]. By subtracting two word line addresses [b] to b_first, b_first is read next to r_last. .

  If the decision result in the step S45 is YES, the value of the bank address counter 32b, that is, the bank address [b] is reset to “0” (step S48), the process proceeds to the step S49, and the bit line address Then, the word line address [a] and the word line address [b] are calculated, and the process returns to step S32.

  Then, the processing from step S32 to step S49 is repeated, and when the determination result in step S40 is YES, that is, when one screen is scanned, the access processing is terminated.

  Here, the calculation of the word line address and the bit line address in step S47 is performed according to the procedure shown in the flowchart of FIG.

  That is, the bit line address counter 33 is incremented (step S51), and it is determined whether or not the value of the bit line address counter 33a has become larger than the bit line length (step S52).

  If the decision result in the step S52 is YES, the value of the bit line address counter 33 is reset to “0” and the word line address counter 34b is incremented (step S53), and the word line address counter 34b It is determined whether or not the value is larger than a predetermined word line length W (step S54).

  Here, the word line length W is set so that the memory address is not insufficient in each memory bank regardless of any arbitrary point in the search area SR as an access candidate. belongs to.

  If the decision result in the step S54 is YES, the value of the word line address counter 34b is reset to “0” and the process is ended.

  Moreover, a process is complete | finished when the determination result in the said step S52, S54 is NO.

  Further, the calculation of the word line address and the bit line address in step S49 is performed according to the procedure shown in the flowchart of FIG.

  That is, the bit line address counter 33 is incremented (step S61), and it is determined whether or not the value of the bit line address counter 33b is larger than the bit line length (step S62).

  If the decision result in the step S62 is YES, the value of the bit line address counter 33 is reset to “0” and the word line address counter 34b is incremented (step S63), and the process is ended.

  Moreover, a process is complete | finished when the determination result in the said step S62 is NO.

  Thus, in this embodiment, the data in the memory banks BK1, BK2, and BK3 are read out through the memory bank BK3.

  In the above-described embodiment, when the area between the access pattern candidates is scanned in the raster direction, the data in the memory bank BK3 is written in the memory bank BK2, the data in the memory bank BK2 is written in the memory bank BK1, The data in the bank BK1 is written in the memory bank BK0. However, the memory bank address is not limited to this, the data in the memory bank BK3 is stored in the memory bank BK0, and the data in the memory bank BK0 is stored in the memory bank BK2. In addition, the data may be read / written in accordance with a certain pattern in which data in the memory bank BK2 is written in the memory bank BK1. Further, the scanning direction is not limited to the raster direction, and may be the reverse of the raster direction, the vertical direction, the diagonal direction, or the like.

  In the above-described embodiment, the data read storage processing unit reads the pixel data on the word line address and the bit line address by the number of banks while incrementing the word line address and the bit line address. The invention is not limited to this, and it is sufficient if reading is performed according to a certain pattern. Therefore, the word line address and the bit line address may be decremented, and the word line address and bit line address pixels may be read based on a predetermined pattern.

It is a block diagram which shows the structure of the data storage apparatus which implements this invention. It is a block diagram which shows the structure of the data storage control part of the said data storage apparatus. It is a block diagram which shows the structure of the data read-out storage control part of the said data storage apparatus. It is a figure which shows typically an example of the access pattern corresponding to the pixel which wants to access multiple images simultaneously with respect to a certain image. It is a figure which shows typically the state which stored the pixel between access candidates in the same bank in order to enable simultaneous reading of the image data of several pixels in the said data storage device. It is a flowchart which shows the procedure of the initial arrangement process performed by the said data storage control part. It is a flowchart which shows the procedure of the initial arrangement | positioning process A performed by the said data storage control part. It is a flowchart which shows the procedure of the initial arrangement | positioning process B performed by the said data storage control part. It is a figure which shows typically the initial stage arrangement | positioning state which stored the pixel between access candidates in the same bank in order to enable simultaneous reading of the image data of several pixels in the said data storage device. It is a figure which shows typically the method of the storing to the word line and bit line in the said data storage device. It is a figure which shows typically the method of the access in the said data storage device, and the mode of the re-storage of data. It is a figure which shows typically the method of the access in the said data storage device, and the mode of the re-storage of data. It is a figure which shows typically the method of the access when a search area is moved +1 to a horizontal direction, and the mode of the re-storing of data. It is a figure which shows typically the method of the access when a search area is moved +1 to a horizontal direction, and the mode of the re-storing of data. It is a figure which shows typically the method of access when the search area is moved +1 in the vertical direction and the state of data re-storage. It is a figure which shows typically the method of access when the search area is moved +1 in the vertical direction and the state of data re-storage. It is a figure which shows typically the method of the access when the search area is moved +2 to the vertical direction, and the mode of data re-storage. It is a figure which shows typically the method of the access when the search area is moved +2 to the vertical direction, and the mode of data re-storage. It is a flowchart which shows the procedure of the access process performed by the said data read / store control part. It is a figure where it uses for description of the setting of the word line address [b] in the said access process. It is a flowchart which shows the procedure of the calculation process of the word line address and bit line address to the last candidate of the access pattern in the said access process. It is a flowchart which shows the procedure of the calculation process of the word line address and bit line address after the last candidate of the access pattern in the said access process. It is a figure which shows typically the structure of a general semiconductor memory. It is a figure which shows typically the state which cannot access simultaneously in the said semiconductor memory. It is a figure which shows the memory structure of a several memory bank. It is a figure which shows typically the pattern of 4 pixels which wants to access simultaneously with respect to a certain image. It is a figure which shows typically the state which stored 4 pixels to access simultaneously in another bank. It is a figure which shows typically the state which stored the pixel between access candidates in another bank for every pixel. It is a figure which shows typically the state which stored the pixel between access candidates in the same bank. It is the figure which showed typically that a certain area can be accessed simultaneously by storing the pixel between access candidates in the same bank, even if a pattern moves in a scanning order. It is the figure which showed typically that a certain area can be accessed simultaneously by storing the pixel between access candidates in the same bank, even if a pattern moves in a scanning order. It is the figure which showed typically that a certain area can be accessed simultaneously by storing the pixel between access candidates in the same bank, even if a pattern moves in a scanning order. It is the figure which showed typically that if the movement of an access pattern exceeds between access pixels, it will access the pixel of the same bank simultaneously.

Explanation of symbols

  10 memory, 20 data storage control unit, 21, 31 counter, 22 match determination unit, 23 flag generation unit, 24, 32 bank address counter, 25, 33 bit line address counter, 26, 34 word line address counter, 27, 35 Address generation unit, 30 data read / storage control unit, 40 address generation unit, 100 data storage device

Claims (12)

When data is distributed and stored in a plurality of memory banks constituting the memory, data between access candidates is determined until the final access pattern candidate based on an access pattern indicating a plurality of desired data to be read simultaneously. A data storage processing unit that is stored in the same bank and initially arranged by storing the data by switching the bank every predetermined cycle after the final access pattern;
A data read storage processing unit for reading out pixel data from each bank for data initially arranged on a memory composed of a plurality of memory banks,
The data read / store processing unit reads data of one pixel on the access pattern and the same word line, and one of the ranges determined based on each position of the access pattern candidate is determined based on the moving direction of the access pattern. A data storage device, wherein the read out one pixel is stored in a bank in which data of pixels in an adjacent range is stored.   2. The data according to claim 1, wherein the data read / store processing unit reads the data of the pixels on the word line address and the bit line address by the number of banks according to a certain pattern of the word line address and the bit line address. Enclosure. 3. The data storage device according to claim 2, wherein the certain pattern is increment or decrement.   The range determined based on each position of the access pattern candidate is a range from one candidate to the next candidate in a direction in which the access pattern moves among candidates constituting the access pattern. The data storage device according to claim 1. 2. The data storage device according to claim 1, wherein the data of the pixels in the one adjacent range is data of pixels in a range adjacent in a direction opposite to the moving direction of the access pattern.   When the data storage processing unit distributes and stores all data in a plurality of memory banks constituting the memory, the data to be stored is based on an access pattern indicating a plurality of desired data to be read simultaneously. Is the data corresponding to the access pattern, and if it matches the access pattern until the final access pattern candidate, the current bit line address and word line address values are stored in the bank. As the write bit line address and write word line address, the bank address is incremented and the pixel data is stored in the bank address. If the access pattern does not match, the bit line address is stored in the current bank address. By storing in the incremented position Data storage apparatus according to claim 1, characterized in that initially arranged on a memory composed of all data from a plurality of memory banks. A data storage control device for controlling writing / reading of data to / from a memory composed of a plurality of memory banks,
When data is distributed and stored in a plurality of memory banks constituting the memory, data between access candidates is determined until the final access pattern candidate based on an access pattern indicating a plurality of desired data to be read simultaneously. A data storage processing unit that is stored in the same bank and initially arranged by storing the data by switching the bank every predetermined cycle after the final access pattern;
A data read storage processing unit for reading out pixel data from each bank for data initially arranged on a memory composed of a plurality of memory banks,
The data read / store processing unit reads data of one pixel on the access pattern and the same word line, and one of the ranges determined based on each position of the access pattern candidate is determined based on the moving direction of the access pattern. A data storage control device, wherein the read one pixel is stored in a bank in which data of pixels in adjacent ranges is stored.   When the data storage processing unit distributes and stores all data in a plurality of memory banks constituting the memory, the data to be stored is based on an access pattern indicating a plurality of desired data to be read simultaneously. Is the data corresponding to the access pattern, and if it matches the access pattern until the final access pattern candidate, the current bit line address and word line address values are stored in the bank. As the write bit line address and write word line address, the bank address is incremented and the pixel data is stored in the bank address. If the access pattern does not match, the bit line address is stored in the current bank address. By storing in the incremented position Data storage control apparatus according to claim 7, characterized in that initially arranged on a memory composed of all data from a plurality of memory banks. A data storage control method for controlling writing / reading of data to / from a memory composed of a plurality of memory banks,
When data is distributed and stored in a plurality of memory banks constituting the memory, data between access candidates is determined until the final access pattern candidate based on an access pattern indicating a plurality of desired data to be read simultaneously. Store in the same bank, and after the end of the access pattern, initial placement by switching the bank every predetermined cycle and storing data,
The access pattern and the data of one pixel on the same word line are read out from the data initially arranged on the memory composed of the plurality of memory banks, and the access is out of the range determined based on each position of the access pattern candidate. A data storage control method, wherein the one pixel read out is stored in a bank in which data of pixels in one adjacent range determined based on a pattern moving direction is stored.   When all the data is distributed and stored in a plurality of memory banks constituting the memory, the data to be stored corresponds to the access pattern based on an access pattern indicating a plurality of desired data to be read simultaneously. If it matches the access pattern until the final access pattern candidate, the value of the bit line address and the word line address at that time is written to the write bit line address and the write of the bank. Store as a word line address, increment the bank address to store the pixel data at the bank address, and if it does not match the access pattern, store the bit line address at the position where the current bank address is incremented The entire data can be stored in multiple memories. Data storage control method according to claim 9, wherein the initial placement on a memory composed of links. A data storage control program for executing, by a computer, data storage control for storing all data in a memory composed of a plurality of memory banks and simultaneously reading desired multiple data,
When data is distributed and stored in a plurality of memory banks constituting the memory, data between access candidates is determined until the final access pattern candidate based on an access pattern indicating a plurality of desired data to be read simultaneously. Stored in the same bank, and after the end of the access pattern, the data is stored by switching the bank every predetermined cycle, and the initial arrangement is performed on the data initially arranged on the memory composed of the plurality of memory banks. The data of one pixel on the same word line is read, and the data of the pixels in one adjacent range determined based on the moving direction of the access pattern among the ranges determined based on the positions of the access pattern candidates is stored. A data storage system characterized by storing the read one pixel in a bank Program.   When all the data is distributed and stored in a plurality of memory banks constituting the memory, the data to be stored corresponds to the access pattern based on an access pattern indicating a plurality of desired data to be read simultaneously. If it matches the access pattern until the final access pattern candidate, the value of the bit line address and the word line address at that time is written to the write bit line address and the write of the bank. Store as a word line address, increment the bank address to store the pixel data at the bank address, and if it does not match the access pattern, store the bit line address at the position where the current bank address is incremented The entire data can be stored in multiple memories. Claim 11, wherein the data storage control program, characterized in that initially placed on a memory composed of links.

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