JP2005303419A - Diplexer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance isolation between respective ports by eliminating coupling of the high-pass filter side and the low-pass filter side. <P>SOLUTION: On a circuit board, capacitors 4b-6b at a high-pass filter part 10 and capacitors 7b-9b at a low-pass filter part 11 are arranged oppositely, and inductance elements 4a-6a at the high-pass filter part 10 and inductance elements 7a-9a at the low-pass filter part 11 are arranged in the regions on the opposite sides of the region arranged with the capacitors 4b-9b while spaced apart from each other. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a diplexer used in a mobile communication device.

  A conventional diplexer will be described with reference to a circuit diagram of FIG. 6 and an exploded perspective view of FIG. In FIG. 6, the low-pass filter LPF has a first inductor L1 and first capacitors C11 and C12, and is connected between the first port P1 and the second port P2. The high-pass filter HPF includes a second inductor inductor L2 and second capacitors C21 to C23, and is connected between the second port P2 and the third port P3.

  In FIG. 7, capacitor electrodes Cp51 and Cp52, capacitor electrodes Cp53 and Cp54, and capacitor electrodes Cp55 and Cp56 are formed on the upper surfaces of the second, third and sixth sheet layers 512, 513 and 516, respectively. Stripline electrodes St51 and St52 are formed on the upper surface of the fourth sheet layer 514. A ground electrode Gp51 and a ground electrode Gp52 are formed on the top surfaces of the fifth and seventh sheet layers 515 and 517, respectively. In addition, a via-hole electrode Vh5 penetrating each of the sheet layers 512 to 515 is formed on the second to fifth sheet layers 512 to 515.

  The first to seventh sheet layers 511 to 517 are stacked and integrally sintered to form the multilayer substrate 51. The stripline electrode St51 and the capacitor electrodes Cp51, Cp53, and Cp55, and the stripline electrode St52 and the capacitor electrodes Cp54 and Cp56 are connected to each other through the via-hole electrode Vh5 inside the multilayer substrate 51. In addition, the side and front and back surfaces of the multilayer substrate 51 are electrically connected to the capacitor electrode Cp51, and are electrically connected to the external terminals T51 and T52 serving as the first and second ports P1 and P2 and the capacitor electrode Cp52. Then, the external terminal T53 that becomes the third port P3 and the external terminal T54 that is electrically connected to the ground electrodes Gp51 and Gp52 and becomes the ground terminal are formed.

  Then, the first and second inductors L1 and L2 are formed by the stripline electrodes St51 and St52, respectively. The capacitor electrodes Cp51 and Cp53 form the first capacitor C11, the capacitor electrode cp55 and the ground electrodes Gp51 and Gp52 form the first capacitor C12. Further, the capacitor electrode Cp51, Cp54 forms the second capacitor C21, the capacitor electrode Cp52, Cp54 forms the second capacitor c22, and the capacitor electrode Cp56 and the ground electrode Gp51, Gp52 form the second capacitor c23 (for example, patents) Reference 1).

Japanese Patent Laid-Open No. 2000-349581 (FIGS. 6 and 7)

  In the above configuration, the first inductor L1 constituting the low-pass filter LPF and the second inductor L2 constituting the high-pass filter HPF are formed by the stripline electrode St51 and the stripline St52, respectively. Since St51 and St52 are formed adjacent to each other on the fourth sheet layer 514, they are coupled to each other and the isolation between the first port P1 and the third port P3 is lowered.

  An object of the present invention is to improve isolation between ports by eliminating coupling between a high-pass filter side and a low-pass filter side.

  In response to the above problem, the present invention has an inductance element and a capacitive element, and has a high-pass filter portion interposed between the common terminal and the first input / output terminal, an inductance element and a capacitive element, A low-pass filter portion interposed between the common terminal and the second input / output terminal, and a circuit board on which the high-pass filter portion and the low-pass filter portion are disposed, The capacitive element of the high-pass filter unit and the capacitive element of the low-pass filter unit are arranged in parallel with a gap therebetween, and the inductance element of the high-pass filter unit and the inductance element of the low-pass filter unit are In addition, they are spaced apart from each other on both sides of the area where the capacitive element is formed.

  The high-pass filter unit includes a low-pass trap circuit that attenuates a low-frequency band below a predetermined frequency, and a high-pass filter that is inserted in series with the low-pass trap circuit, and the low-pass filter unit includes the predetermined low-pass filter unit. A high-frequency trap circuit for attenuating a high-frequency band above the frequency and a low-pass filter inserted in series with the high-frequency trap circuit, the low-frequency trap circuit, the high-pass filter, and the high-frequency trap circuit Each of the low-pass filters includes the inductance element and the capacitive element, and the low-pass filter has a region between the capacitive element of the low-frequency trap circuit and the capacitive element of the high-frequency trap circuit that are arranged in parallel with each other at an interval. On both sides, the inductance element of the low-frequency trap circuit and the inductance element of the high-frequency trap circuit are separated from each other. Arranged on both sides of a region of the capacitive element of the high-pass filter and the capacitive element of the low-pass filter, which are arranged in parallel with each other at a distance from each other, on the inductance element of the high-pass filter and the low-pass filter. The inductance elements are arranged apart from each other.

  A plurality of the low-frequency trap circuits are provided corresponding to the plurality of low-frequency bands in different bands, and a plurality of the high-frequency trap circuits are provided corresponding to the plurality of high-frequency bands in different bands. A low-frequency trap circuit corresponding to the low-frequency side frequency band close to the predetermined frequency side among the plurality of low-frequency trap circuits is disposed on the common terminal side, and among the plurality of high-frequency trap circuits, the A high frequency trap circuit corresponding to the high frequency band close to a predetermined frequency side is disposed on the common terminal side.

  Further, the inductance element and the capacitive element are formed of a thin film or a thick film.

  According to the diplexer according to claim 1, the capacitive element of the high-pass filter unit and the capacitive element of the low-pass filter unit are arranged in parallel with each other on the circuit board, and the inductance element of the high-pass filter unit and the low-pass filter are arranged. The inductance elements of the high-pass filter section and the inductance elements of the low-pass filter section are mutually connected. Therefore, mutual isolation between the first input / output terminal and the second input / output terminal is improved.

  According to the diplexer according to claim 2, the high-pass filter unit includes a low-pass trap circuit and a high-pass filter, and the low-pass filter unit includes a high-pass trap circuit and a low-pass filter. Each of the high-pass filter, the high-frequency trap circuit, and the low-pass filter has an inductance element and a capacitive element. The low-pass trap circuit capacitive element and the high-frequency trap circuit capacitive element arranged in parallel with each other at a distance from each other. On both sides, an inductance element of a low-pass trap circuit and an inductance element of a high-pass trap circuit are arranged separately from each other, and a capacitive element of a high-pass filter and a capacitive element of a low-pass filter that are arranged in parallel at a distance from each other On both sides of the area, the inductance element of the high-pass filter and the inductor of the low-pass filter Each Having disposed to separate the Nsu elements together, do not bind the mutual inductance element and the low trap circuits and high trap circuit. Further, the mutual inductance elements of the high pass filter and the low pass filter are not coupled.

  According to the diplexer of the third aspect, the low frequency trap circuit corresponding to the low frequency band close to the predetermined frequency side among the plurality of low frequency trap circuits is disposed on the common terminal side, and a plurality of high frequency trap circuits are provided. Since the high-frequency trap circuit corresponding to the high-frequency band close to the predetermined frequency side is arranged on the common terminal side, the high-pass filter section and the low-pass filter section have improved pass characteristics and are mutually compatible. This improves the isolation.

According to the diplexer of the fourth aspect, since the inductance element and the capacitive element are formed of a thin film or a thick film, the size can be reduced.
Improve.

  The diplexer of the present invention will be described with reference to FIGS. FIG. 1 is a circuit diagram showing an embodiment of a diplexer of the present invention, FIG. 2 is a transmission characteristic diagram, FIGS. 3 to 5 are pattern diagrams of a circuit board constituting the diplexer circuit of FIG. 1, and FIG. FIG. 4 is a pattern diagram of the inner layer surface, and FIG. 5 is a pattern diagram of the lower surface. 4 and 5 are perspective views seen from the upper surface side.

  First, in FIG. 1, a high frequency band higher than a predetermined frequency (for example, 2.2 GHz demultiplexing frequency) between the common terminal 1 for antenna connection and the first input / output terminal 2, for example, Bluetooth (abbreviated as BT) (registered trademark of Nokia, etc.) system transmission / reception frequency band (bandwidth is 2.4 GHz to 2.5 GHz) and wireless LAN system transmission / reception frequency band (bandwidth is 4.9 GHz to 6. GHz). 0 GHz) signal, and between the common terminal 1 and the second input / output terminal 3, a regular frequency band having a frequency lower than a predetermined frequency, for example, a GSM system transmission / reception frequency band (band is 806 MHz to 960 MHz) and signals in the DCS system and PCS system transmission / reception frequency bands (bandwidth is 1710 MHz to 1990 MHz).

  A high pass filter unit 10 is provided between the common terminal 1 and the first input / output terminal 2, and a low pass filter unit 11 is provided between the common terminal 1 and the second input / output terminal 3.

  The high-pass filter unit 10 includes two low-frequency trap circuits 4 and 5 and a high-pass filter 6 that are inserted in series. The first low-frequency trap circuit 4 is composed of a parallel resonant circuit of an inductance element 4a and a capacitive element 4b, and the resonant frequency is selected, for example, in the vicinity of 1900 MHz to attenuate the transmission / reception frequency bands of the DCS system and the PCS system. . The second low-frequency trap circuit 5 is also composed of a parallel resonant circuit of an inductance element 5a and a capacitive element 5b, and the resonant frequency is selected, for example, in the vicinity of 920 MHz to attenuate the transmission / reception frequency band of the GSM system.

  The first low-frequency trap circuit 4 is disposed on the common terminal 1 side, the high-pass filter 6 is disposed on the first input / output terminal 2 side, and the second low-frequency trap circuit 5 is disposed on the first low-frequency trap circuit. It is inserted between the circuit 4 and the high pass filter 6.

  The high-pass filter 6 has a half-section high-pass filter, the inductance element 6a constituting this is connected between the output terminal of the second low-frequency trap circuit 5 and the ground, and the capacitive element 6b is the second low-frequency filter. It is connected between the output terminal of the trap circuit and the first input / output terminal 2.

  The low-pass filter unit 11 includes two high-frequency trap circuits 7 and 8 and a low-pass filter 9 inserted in series. The first high-frequency trap circuit 7 is composed of a parallel resonant circuit of an inductance element 7a and a capacitive element 7b, and the resonance frequency thereof is selected, for example, in the vicinity of 2.45 GHz, and is a Bluetooth (registered trademark of Nokia Corporation) system. The transmission / reception frequency band is attenuated. The second high-frequency trap circuit 8 is also composed of a parallel resonance circuit of an inductance element 8a and a capacitance element 8b, and the resonance frequency is selected, for example, in the vicinity of 5.5 GHz to attenuate the transmission / reception frequency band of the wireless LAN system.

  The first high-frequency trap circuit 7 is disposed on the common terminal 1 side, the low-pass filter 9 is disposed on the second input / output terminal 3 side, and the second high-frequency trap circuit 8 is disposed on the first high-frequency trap circuit. It is inserted between the circuit 7 and the low-pass filter 9.

  The low-pass filter 9 has a half-section low-pass filter, and the inductance element 9a constituting the low-pass filter 9 is connected between the output terminal of the second high-frequency trap circuit 8 and the second input / output terminal 3, and the capacitive element 9b. Is connected between the output terminal of the second high-frequency trap circuit and the ground.

  In the above configuration, the first low frequency trap circuit 4 (1900 MHz), the first high frequency, and the wrap circuit 7 (2.45 GHz) close to the predetermined frequency are disposed on the common terminal 1 side. The isolation between the input / output terminal 2 and the second input / output terminal 3 is improved.

  The transmission characteristics between the common terminal 1 and the first input / output terminal 2 and the transmission characteristics between the common terminal 1 and the second input / output terminal 3 in the above configuration are as shown in FIGS. Become. Frequency points 1 to 4 in FIG. 2 indicate the positions of the center frequencies of the GSM system transmission / reception frequency band, the DCS system and PCS system transmission / reception frequency bands, the Bluetooth system transmission / reception frequency band, and the wireless LAN system transmission / reception frequency band, respectively.

  The attenuation poles A1 and A2 in the transmission characteristic A are due to the first low-frequency trap circuit 4 and the second low-frequency trap circuit 5, respectively. At the frequencies of the attenuation poles A1 and A2, signals in the transmission / reception frequency band of the GSM system and the transmission / reception frequency band of the DCS system / PCS system input to the common terminal 1 are transmitted by the first and second low-frequency trap circuits 4 and 5. Since these signals are reflected, those signals are efficiently output to the second input / output terminal 3. Therefore, as shown in the transmission characteristic B, the attenuation amount is extremely small at the frequency point 1 and the frequency point 2. Also, the transmission / reception frequency band signal of the Bluetooth system and the transmission / reception frequency band signal of the wireless LAN system are not disturbed by the transmission / reception frequency band signal of the GSM system and the transmission / reception frequency band signal of the DCS system / PCS system.

    The attenuation poles B1 and B2 in the transmission characteristic B are due to the first high-frequency trap circuit 7 and the second high-frequency trap circuit 8, respectively. At the frequencies of the attenuation poles B1 and B2, signals in the transmission / reception frequency band of the Bluetooth system and the transmission / reception frequency band of the wireless LAN system input to the common terminal 1 are reflected by the first and second high-frequency trap circuits 7 and 8. Therefore, those signals are efficiently output to the first input / output terminal 2. Therefore, as shown in the transmission characteristic A, the attenuation amount becomes extremely small at the frequency point 3 and the frequency point 4. Further, the signal in the transmission / reception frequency band of the GSM system and the signal in the transmission / reception frequency band of the DCS system / PCS system are not disturbed by the signal in the transmission / reception frequency band of the Bluetooth system and the signal in the transmission / reception frequency band of the wireless LAN system.

  The attenuation pole A3 in the transmission characteristic A is due to series resonance by the first high-frequency trap circuit 7, the second high-frequency trap circuit 8, and the capacitive element 9b in the low-pass filter 9, and this is the attenuation pole B1. Appears at a frequency between B2. Therefore, an unnecessary signal existing between the transmission / reception frequency band of the Bluetooth system and the transmission / reception frequency band of the wireless LAN system is attenuated, so that interference caused by this signal is reduced.

  Similarly, the attenuation pole B3 in the transmission characteristic B is due to series resonance by the inductance element 6a in the first low-frequency trap circuit 4, the second low-frequency trap circuit 5, and the high-pass filter 6, and this is the attenuation pole A1. And appear at a frequency between A2. Therefore, since unnecessary signals existing between the transmission / reception frequency band of the GSM system and the transmission / reception frequency band of the DCS system / PCS system are attenuated, the interference caused by this signal is reduced.

The diplexer having the above circuit configuration is configured on a rectangular circuit board 20 made of a plurality of laminated plates.
The circuit board (multilayer board) 20 is made of a material such as a low-temperature fired ceramic (LTCC), and is formed of two layers of laminates 20a and 20b. FIG. 1, the strip line 21 constitutes the inductance element 4a of FIG. 1, and an electrode 21a on one end side thereof and an electrode 21b on the other end side thereof are overlapped in the vertical direction, and between these electrodes 21a and 21b. Is provided with a dielectric made of an insulating material (not shown, the same applies hereinafter).
Accordingly, the capacitive element 4b of FIG. 1 is configured by the two electrodes 21a and 21b and the dielectric between them.

Further, the strip line 22 constitutes the inductance element 7a of FIG. 1, and the electrode 22a on one end side and the electrode 22b on the other end side overlap in the vertical direction, and between these electrodes 22a and 22b. A dielectric made of an insulating material is provided.
Therefore, the capacitive element 7b of FIG. 1 is configured by the two electrodes 22a and 22b and the dielectric between them.
The strip lines 21 and 22 are connected to each other at one end, the electrode 21a at one end of the strip line 21 is connected to the electrode 22a at one end of the strip line 22, and a via hole 23a in the vicinity thereof is provided. It has been.

  Then, the electrodes 21a and 21b of the strip line 21 and the electrodes 22a and 22b of the strip line 22 are arranged in parallel with a distance from each other, and the strip line 21 is disposed on both sides of the region with the juxtaposed region therebetween. And the strip line 22 are arranged in a separated state.

The strip line 24 constitutes the inductance element 5a of FIG. 1, and the electrode 24a on one end side thereof is connected to the electrode 21b on the other end side of the strip line 21 and is vertically connected to the electrode 24b on the other end side. A dielectric made of an insulating material is provided between the electrodes 24a and 24b.
Therefore, the capacitive element 5b of FIG. 1 is configured by the two electrodes 24a and 24b and the dielectric between them.
Further, the strip line 24 is formed in a spiral shape, and the other end side of the strip line 24 crossing the spiral portion is insulated from the spiral portion by a dielectric (not shown) made of an insulating material. It has become.

The strip line 25 constitutes the inductance element 8a of FIG. 1, and the electrode 25a on one end side thereof is connected to the electrode 22b on the other end side of the strip line 22 and is vertically connected to the electrode 25b on the other end side. A dielectric made of an insulating material is provided between the electrodes 25a and 25b.
Accordingly, the capacitive element 8b of FIG. 1 is configured by the two electrodes 25a and 25b and the dielectric between them.

  Then, the electrodes 24a and 24b of the strip line 24 and the electrodes 25a and 25b of the strip line 25 are arranged in parallel with a distance from each other, and the strip line 24 is provided on both sides of the juxtaposed region. And the strip line 25 are disposed in a separated state.

The strip line 26 constitutes the inductance element 6a of FIG. 1. The electrode 26a on one end side is connected to the electrode 24b on the other end side of the strip line 24, and a via hole 27a is provided on the other end side. .
In addition, an electrode 28 that overlaps the electrode 26 a in the vertical direction is provided, and a dielectric made of an insulating material is provided between the electrode 26 a and the electrode 28.
Accordingly, the electrode 26a, the electrode 28, and the dielectric between them constitute the capacitive element 6b of FIG. 1, and the electrode 28 is provided with a via hole 29a.

The strip line 30 constitutes the inductance element 9a of FIG. 1. The electrode 30a on one end side is connected to the electrode 25b on the other end side of the strip line 25, and a via hole 31a is provided on the other end side. .
And the electrode 32 which overlaps with the electrode 30a of one end side in the up-down direction is provided, and a dielectric made of an insulating material is provided between the electrode 30a and the electrode 32.
Accordingly, the electrode 30a, the electrode 32, and the dielectric between them constitute the capacitive element 9b of FIG. 1, and the electrode 32 is provided with a via hole 33a.

  The electrode 26a of the strip line 26 and the electrode 30a of the strip line 30 are disposed with a space between each other, and the strip line 26 and the strip line 30 are disposed on both sides of the region where the electrodes are disposed. Are disposed apart from each other.

As described above, the electrodes 21a / 21b, 24a / 24b, and 26a / 28, and the electrodes 22a / 22b, 25a / 25b, and 30a / 32 constituting the capacitive elements 4b to 9b are provided on the central side of the circuit board 20. Are arranged so as to be arranged in two rows, and on both sides of these electrodes, the strip lines 21, 24, 26 and the strip lines 22, 25, 30 are arranged in two rows while being separated from each other. It is arranged.
Therefore, since the strip lines 21, 24, and 26 constituting the high-pass filter unit 10 and the strip lines 22, 25, and 30 constituting the low-pass filter unit 11 are separated from each other, the first input / output is difficult to be coupled to each other. Mutual isolation between the terminal 2 and the second input / output terminal 3 is improved.

  Further, the strip lines 21, 24 and 26 constituting the high-pass filter unit 10, the strip lines 22, 25 and 30 constituting the low-pass filter unit 11, and the electrodes 21a / 21b and 24a / 24b constituting the respective capacitive elements 4b to 9b. 26a / 28, electrodes 22a / 22b, 25a / 25b, 30a / 32, and the dielectric are formed by thin film technology such as vapor deposition or sputtering, or thick film technology such as printing or coating.

  When these are formed by a thin film, the strip line and electrode are made of silver or aluminum, and the dielectric is made of silicon nitride, barium titanate, lead titanate, or the like. When these are formed by a thick film, the strip line and electrode are made of silver paste or silver-palladium paste, and the dielectric is made of silicon nitride, barium titanate, lead titanate, or the like. used.

FIG. 4 shows an inner layer pattern diagram provided on the upper surface of the second-layer laminate 20b. A via hole 23b is provided at one end of the lead-out line 41, and this via hole 23b corresponds to the first-layer via hole 23a. It is provided at a position and is connected to the via hole 23a via a connection conductor (not shown).
In addition, a via hole 42b is provided at the other end of the lead-out line 41, and this via hole 42b is provided in the vicinity of one side 20b1 of the laminated plate 20b and in the center of the side 20b1.

A via hole 29b is provided at one end of the lead-out line 43. The via hole 29b is provided at a position corresponding to the first-layer via hole 29a and is connected to the via hole 29a via a connection conductor (not shown). .
A via hole 44b is provided at the other end of the lead-out line 43, and this via hole 44b is provided in the vicinity of one corner on the side 20b2 facing the side 20b1 of the laminated plate 20b.

Also, a via hole 31b is provided at one end of the lead-out line 45, and this via hole 31b is provided at a position corresponding to the first-layer via hole 31a and is connected to the via hole 31a via a connection conductor (not shown). Is done.
A via hole 46b is provided at the other end of the lead line 45, and this via hole 46b is provided in the vicinity of another corner on the side 20b2.

The second layer laminate 20b is provided with via holes 27b and 33b. The via holes 27b and 33b are provided at positions corresponding to the first layer via holes 27a and 33a. The via hole 27b is connected to the via hole 27a. The via hole 33b is connected to the via hole 33a through a conductor (not shown) and connected to the via hole 33a.
The lead lines 41, 43, 45 are all formed by thick film technology, and are formed by printing or applying a silver paste, a silver-palladium paste, or the like.

FIG. 5 shows a pattern of the lower surface of the second laminated plate 20b. The lower surface of the laminated plate 20b has terminal electrodes 51 connected to via holes 42b, 44b and 46b via connection conductors (not shown), respectively. 52 and 53 are provided.
The terminal electrode 51 becomes the input terminal (common terminal) 1 in FIG. 1, the terminal electrode 52 becomes the first input / output terminal 2 in FIG. 1, and the terminal electrode 53 becomes the second input / output terminal 3 in FIG. A plurality of ground electrodes 54 and a large-area ground conductor 55 connected to the ground electrodes 54 are provided at appropriate positions near the peripheral edge of the laminated plate 20b. 33b and 29b are connected via a connection conductor (not shown).

With the above configuration, the strip line 21 and the strip line 22 are connected to the terminal electrode 51 via the via holes 23a and 23b, the lead line 41 and the via hole 42, and the electrode 28 is connected to the via holes 29a and 29b and the lead line 43. It is connected to the terminal electrode 52 through the via hole 44b.
The strip line 26 is connected to the ground conductor 55 via via holes 27a and 27b, the electrode 32 is connected to the ground conductor 55 via via holes 33a and 33b, and the strip line 30 is also connected to the via holes 31a and 31b. And connected to the terminal electrode 53 through the lead line 45 and the via hole 46b.

  The terminal electrodes 51, 52, 53, the ground electrode 54, and the ground conductor 55 provided on the lower surface of the laminate 20b are formed by a thin film technique such as vapor deposition or sputtering, or a thick film technique such as printing or coating. When formed by a thin film, silver or aluminum is used, and when formed by a thick film, silver paste, silver-palladium paste, or the like is used.

It is a circuit diagram of the diplexer of the present invention. It is a transmission characteristic figure of the diplexer of this invention. It is a pattern figure in the upper surface of the circuit board which comprises the diplexer of this invention. It is a pattern figure in the inner layer surface of the circuit board which comprises the diplexer of this invention. It is a pattern figure in the lower surface of the circuit board which comprises the diplexer of this invention. It is a circuit diagram of the conventional diplexer. It is a conventional exploded perspective view.

Explanation of symbols

1: Input terminal (common terminal)
2: first input / output terminal 3: second input / output terminal 4: first low-frequency trap circuit 5: second low-frequency trap circuit 6: high-pass filter 7: first high-frequency trap 8: second 9: Low-pass filter 4a-9a: Inductance element 4b-9b: Capacitance element 10: High-pass filter part 11: Low-pass filter part 20: Circuit board (multilayer board)
20a: Laminated board of the first layer 20b: Laminated board of the second layer 21, 22, 24, 25, 26, 30: Strip line 23, 27, 29, 31, 33, 42, 44, 46: Via hole 41, 43 45: Lead line 51-54: Terminal electrode

Claims (4)

In addition to having an inductance element and a capacitance element, the high-pass filter section interposed between the common terminal and the first input / output terminal, the inductance element and the capacitance element, and the common terminal and the second input / output A low-pass filter section interposed between the terminals, and a circuit board on the surface of which the high-pass filter section and the low-pass filter section are disposed, and on the circuit board, the high-pass filter section The capacitive element and the capacitive element of the low-pass filter unit are arranged side by side at a distance from each other, and the inductance element of the high-pass filter unit and the inductance element of the low-pass filter unit are formed in the region where the capacitive element is formed. A diplexer characterized in that the diplexers are disposed apart from each other on both sides of the sheet. The high-pass filter unit includes a low-pass trap circuit that attenuates a low-frequency band that is equal to or lower than a predetermined frequency, and a high-pass filter that is inserted in series with the low-frequency trap circuit, and the low-pass filter unit is equal to or higher than the predetermined frequency A high-frequency trap circuit for attenuating the high-frequency side frequency band and a low-pass filter interposed in series with the high-frequency trap circuit, the low-frequency trap circuit, the high-pass filter, the high-frequency trap circuit, Each of the low-pass filters has the inductance element and the capacitive element, and is provided on both sides of a region of the capacitive element of the low-frequency trap circuit and the capacitive element of the high-frequency trap circuit that are arranged in parallel at a distance from each other. The inductance element of the low-frequency trap circuit and the inductance element of the high-frequency trap circuit are spaced apart from each other. The inductance element of the high-pass filter and the low-pass filter are disposed on both sides of a region of the capacitive element of the high-pass filter and the capacitive element of the low-pass filter that are arranged in parallel and spaced apart from each other. The diplexer according to claim 1, wherein the inductance elements are spaced apart from each other. A plurality of low-frequency trap circuits are provided corresponding to a plurality of low-frequency bands in different bands; a plurality of high-frequency trap circuits are provided corresponding to a plurality of high-frequency bands in different bands; A low-frequency trap circuit corresponding to the low-frequency side frequency band close to the predetermined frequency side among the plurality of low-frequency trap circuits is disposed on the common terminal side, and the predetermined frequency among the plurality of high-frequency trap circuits The diplexer according to claim 2, wherein a high frequency trap circuit corresponding to the high frequency band close to the side is disposed on the common terminal side. 4. The diplexer according to claim 1, wherein the inductance element and the capacitive element are formed of a thin film or a thick film.

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