JP2005268696A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize higher current and higher voltage resistance whereas increase in ON-resistance is controlled, and also to realize high speed operation. <P>SOLUTION: An n-type elevated semiconductor layer 7 formed like a stripe along the travelling direction of current is laminated on an n-type offset drain layer 6, a trench 21a is formed to an insulating layer 21 on the n-type elevated semiconductor layer 7 formed like a stripe, and an embedding electrode 22 is embedded to the trench 21a via the insulating layer 21. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and is particularly suitable for application to a multi-resurf MOSFET (Metal Oxide Field Effective Transistor).

  A transistor used in a transmission / reception circuit of a mobile communication terminal device is required to have a large current and a high breakdown voltage without increasing the on-resistance. In order to realize such a ranger, for example, Patent Document 1 discloses a method of providing an offset drain having a multi-resurf structure on an SOI (Silicon On Insulator) substrate.

In the offset drain having the multi-resurf structure, the n-type region and the p-type region are arranged in a stripe shape along the current traveling direction. For this reason, in the off state where the gate voltage is 0 volt or less, the pn junction interface of the offset drain in which the n-type region and the p-type region are alternately arranged in a stripe shape, the n ⁺ of the p-type region of the offset drain and the drain electrode The depletion layer can be expanded at the junction interface with the n-type region, the junction interface between the n-type region of the offset drain and the p-type body, and the interface between the n-type region of the offset drain and the BOX layer. For this reason, the surface electric field of the offset drain can be relaxed by optimizing the concentration and depth of the n-type region and the p-type region of the offset drain. As a result, the impurity concentration in the n-type region of the offset drain can be increased without degrading the breakdown voltage, and a large current and a high breakdown voltage can be achieved without increasing the on-resistance.

Further, for example, in Patent Document 2, in an offset drain having a multi-resurf structure, a buried electrode is arranged instead of a p-type region, and the buried electrode covered with an n-type region and a silicon oxide film is used as a current traveling direction. A method of arranging the stripes in a striped manner is disclosed.
In the method disclosed in Patent Document 2, in the off state where the gate voltage is 0 volt or less, the interface between the n-type region of the offset drain and the silicon oxide film covering the buried electrode, the n-type region of the offset drain and the p-type body are used. The depletion layer can be expanded at the junction interface with the n-type region of the offset drain and the interface of the BOX layer. For this reason, the surface electric field of the offset drain can be relaxed by optimizing the concentration and depth of the n-type region of the offset drain. As a result, the impurity concentration in the n-type region of the offset drain can be increased without degrading the breakdown voltage, and a large current and a high breakdown voltage can be achieved without increasing the on-resistance.

Moreover, since the dielectric constant of the silicon oxide film is about 1/3 of the dielectric constant of silicon, the capacitance between the n-type region and the buried electrode is reduced compared to the junction capacitance between the n-type region and the p-type region. can do. For this reason, compared with the case where the multi-resurf structure in which n-type regions and p-type regions are alternately arranged is applied to the offset drain, the capacitance between the source / drain can be reduced and high-speed operation can be realized. Can do.
JP 2000-286417 A JP 2000-289866 A

However, in the method disclosed in Patent Document 1, a junction capacitance proportional to the junction area between the n-type region and the p-type region is generated in the offset drain, so that the source / drain capacitance increases. For this reason, there has been a problem that the output capacitance of the field effect transistor becomes large and high speed operation becomes difficult.
Further, in the method disclosed in Patent Document 2, when the upper silicon layer of the SOI structure is thinned, the thickness of the offset drain is thinned and the on-resistance is increased. On the other hand, when the impurity concentration in the n-type region of the offset drain is further increased to reduce the on-resistance, the source / drain region punch-through phenomenon, threshold voltage fluctuation, short channel effect known as an increase in standby current, etc. There was a problem that occurred.

  Further, since a buried electrode is formed by digging a trench in the silicon layer of the offset drain, there is a problem that defects are likely to occur in the silicon layers of the offset drain, the channel region, and the body region. Further, since the silicon oxide film covering the buried electrode is formed by LOCOS, there is a problem that these defects become more serious.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device capable of achieving a high current and a high breakdown voltage while realizing an increase in on-resistance while realizing high-speed operation. is there.

In order to solve the above-described problem, according to a semiconductor device of one embodiment of the present invention, in a semiconductor device in which a field effect transistor having a buried electrode in an offset drain is formed, the semiconductor layer provided with the offset drain Is thicker than the film thickness of the semiconductor layer on the source side.
As a result, the semiconductor layer on which the offset drain is formed can be made thick while the source-side semiconductor layer can be thinned, and the increase in the capacitance between the source and drain can be suppressed while the offset is increased. A depletion layer can be spread on the drain. For this reason, it is possible to reduce the on-resistance and output capacitance while suppressing an increase in the impurity concentration of the offset drain, and to reduce the electric field of the offset drain, while completely depleting the field effect transistor. It is possible to operate in the mode. As a result, it is possible to realize low power consumption and high speed of the field effect transistor, and it is possible to achieve a large current and a high breakdown voltage.

According to the semiconductor device of one embodiment of the present invention, a source tie structure is provided on the source side.
As a result, hot carriers accumulated in the body region can be released, and the field effect transistor can be operated in the full depletion mode, and deterioration of the drain breakdown voltage can be suppressed.

In addition, according to the semiconductor device of one embodiment of the present invention, the impurity concentration of the offset drain gradually decreases from the drain toward the gate.
As a result, it is possible to reduce the impurity concentration at the drain end of the body region while suppressing an increase in the drain resistance, and to reduce the electric field concentration at the drain end of the body region, thereby improving the drain withstand voltage. Can do.

In addition, according to the semiconductor device of one embodiment of the present invention, the field effect transistor is formed over an SOI substrate.
As a result, element isolation of the field effect transistor can be easily performed, latch-up can be prevented, and the source / drain junction capacitance can be reduced. It is possible to increase the speed.

In the semiconductor device according to one embodiment of the present invention, the embedded electrode is connected to a source.
Thus, when the field effect transistor is in an off state, a depletion layer is formed at the interface between the semiconductor layer of the offset drain and the insulating film covering the buried electrode, the junction interface between the offset drain and the body, and the interface between the semiconductor layer of the offset drain and the BOX layer. Can be spread. For this reason, the electric field of the offset drain can be relaxed, and the off breakdown voltage can be improved.

In the semiconductor device according to one embodiment of the present invention, the embedded electrode is connected to a gate.
Thus, when the field effect transistor is in an off state, a depletion layer is formed at the interface between the semiconductor layer of the offset drain and the insulating film covering the buried electrode, the junction interface between the offset drain and the body, and the interface between the semiconductor layer of the offset drain and the BOX layer. Can be spread. In addition, when the field effect transistor is in an on state, a voltage having the same potential as that of the gate can be applied to the embedded electrode. For this reason, not only when the field effect transistor is in the off state but also when the field effect transistor is in the on state, the electric field of the offset drain can be relaxed, and not only the off breakdown voltage but also the on breakdown voltage can be improved.

  In addition, according to the semiconductor device of one embodiment of the present invention, the semiconductor layer stacked over the insulator, the gate electrode formed over the semiconductor layer, the semiconductor layer provided in the semiconductor layer, and below the gate electrode A first conductive type body region disposed; a second conductive type source region disposed on one side of the gate electrode; and a second conductive layer disposed on the other side of the gate electrode. A conductivity type offset drain layer; a second conductivity type elevated semiconductor layer disposed on the second conductivity type offset drain layer and formed in a stripe shape along a current traveling direction; and the stripe shape A buried electrode embedded in the second conductivity type elevated semiconductor layer via an insulating film; and a second conductivity type drain region disposed at a predetermined distance from the gate electrode. And it features.

  As a result, the thickness of the semiconductor layer provided with the offset drain can be increased while the body region can be thinned, and damage to the second conductivity type offset drain layer can be suppressed while the second region is suppressed. A buried electrode can be formed on the conductive offset drain layer. For this reason, even when the field effect transistor is operated in the fully depleted mode, it is possible to reduce the on-resistance while suppressing the increase in the impurity concentration of the offset drain, and the second conductivity type offset drain layer. The surface electric field of the offset drain can be relaxed while suppressing an increase in defects and an increase in capacitance between the source / drain. As a result, it is possible to reduce the power consumption and speed of the field-effect transistor while suppressing the punch-through phenomenon of the source / drain region, the fluctuation of the threshold voltage, and the occurrence of the short channel effect. In addition, it is possible to increase the current and increase the breakdown voltage.

In addition, according to the semiconductor device of one embodiment of the present invention, the first conductivity type source body connection region provided in the second conductivity type source region and disposed so as to be in contact with the first conductivity type body region; And a contact disposed so as to straddle the second conductivity type source region and the first conductivity type source body connection region.
Thereby, even when the body region is divided by the source region and the drain region, it is possible to escape the hot carriers accumulated in the body region, while enabling the field effect transistor to operate in the full depletion mode, Degradation of the drain breakdown voltage can be suppressed.

  In addition, according to the method for manufacturing a semiconductor device of one embodiment of the present invention, a step of forming a gate electrode on the first conductivity type semiconductor layer formed on the insulator, and a drain side using the gate electrode as a mask A step of forming a second conductivity type offset drain layer by performing ion implantation into the first conductivity type semiconductor layer, a step of forming a sidewall on the side wall of the gate electrode, and a stripe along the direction of current flow Forming a second conductive type elevated semiconductor layer arranged in a shape on the second conductive type offset drain layer, and using the gate electrode and the sidewall as a mask to form the second conductive type semiconductor layer on the source side A step of forming a second conductivity type source region by ion implantation and a second conductivity type drain disposed at a predetermined distance from the gate electrode. Forming an insulating region, depositing an insulating film on the second conductive type elevated semiconductor layer, and forming a trench disposed in the gap between the second conductive type elevated semiconductor layer in the insulating film. And a step of forming a buried electrode embedded in the trench.

  As a result, the thickness of the semiconductor layer provided with the offset drain can be increased while the body region can be thinned, and damage to the second conductivity type offset drain layer can be suppressed while the second region is suppressed. A buried electrode can be formed on the conductive offset drain layer. For this reason, even when a field effect transistor is formed on an SOI substrate, it is possible to increase current and voltage while suppressing an increase in on-resistance, and to realize high-speed operation stably. It becomes possible to do.

  In addition, according to the method for manufacturing a semiconductor device of one embodiment of the present invention, a step of forming a gate electrode on the first conductivity type semiconductor layer formed on the insulator, and a drain side using the gate electrode as a mask Ion implantation is performed on the first conductive type semiconductor layer to form a second conductive type offset drain layer, and ion implantation is performed on the first conductive type semiconductor layer on the source side using the gate electrode as a mask. To form an offset source layer in which the first conductivity type region and the second conductivity type region are alternately arranged, a step of forming a sidewall on the side wall of the gate electrode, and a current traveling direction Forming a second conductive type elevated semiconductor layer arranged in a stripe shape on the second conductive type offset drain layer; and the second conductive type elevated semiconductor layer. Forming a first resist pattern covering the region near the gate and the first conductivity type region of the offset source layer; and performing ion implantation using the first resist pattern, the gate electrode and the sidewall as a mask, Forming a second conductivity type source region and a second conductivity type drain region; forming a second resist pattern covering the second conductivity type elevated semiconductor layer and the second conductivity type region of the offset source layer; Forming a first conductivity type source body connection region in the first conductivity type region of the offset source layer by performing ion implantation using the second resist pattern, the gate electrode and the sidewall as a mask; Depositing an insulating film on the two-conductivity type elevated semiconductor layer; and Forming a trench disposed in a gap between the type elevated semiconductor layers in the insulating film, forming a buried electrode embedded in the trench, the second conductivity type source region, and the first conductivity type Forming a contact disposed so as to straddle the source body connection region.

  As a result, it is possible to form a buried electrode on the second conductivity type offset drain layer while suppressing damage to the second conductivity type offset drain layer, and while suppressing the complication of the manufacturing process, A tie structure can be provided. For this reason, while suppressing an increase in on-resistance, it is possible to increase the current, increase the breakdown voltage, and increase the speed, and also allow the hot carriers accumulated in the body region to escape, thereby reducing the drain breakdown voltage. Can be suppressed.

  Further, according to the method of manufacturing a semiconductor device according to one aspect of the present invention, the step of forming the second conductivity type elevated semiconductor layer arranged in the stripe shape includes the step of forming a surface of the second conductivity type offset drain layer. Forming an oxide film patterned to be exposed; epitaxially growing an elevated semiconductor layer on the second conductivity type offset drain layer; and ion implantation of a second conductivity type impurity in the elevated semiconductor layer. By performing, a step of forming a second conductivity type elevated semiconductor layer and a step of etching the second conductivity type elevated semiconductor layer into a stripe shape are provided.

  This makes it possible to form a buried electrode on the second conductivity type offset drain layer without etching the second conductivity type offset drain layer. For this reason, it is possible to reduce the output capacitance of the field effect transistor while suppressing the occurrence of defects in the second conductivity type offset drain layer, and to reduce the electric field of the offset drain.

  Further, according to the method of manufacturing a semiconductor device according to one aspect of the present invention, the step of forming the second conductivity type elevated semiconductor layer arranged in the stripe shape includes the step of forming a surface of the second conductivity type offset drain layer. Forming an oxide film patterned to be exposed in a stripe shape; forming an elevated semiconductor layer arranged in a stripe shape on the offset drain layer by epitaxial growth using the oxide film as a mask; Forming a second conductivity type elevated semiconductor layer by performing ion implantation of a second conductivity type impurity into the elevated semiconductor layer.

  As a result, the second conductivity type elevated semiconductor layer can be formed in a stripe shape without etching the second conductivity type elevated semiconductor layer, and not only the second conductivity type offset drain layer but also the second conductivity type It is possible to form a buried electrode on the second conductivity type offset drain layer while suppressing damage to the conductivity type elevated semiconductor layer. Therefore, it is possible to reduce the output capacity of the field effect transistor while suppressing the occurrence of defects in the second conductivity type offset drain layer and the second conductivity type elevated semiconductor layer, and to reduce the electric field of the offset drain. It can be mitigated.

Further, according to the method for manufacturing a semiconductor device of one embodiment of the present invention, the semiconductor layer is Si, and the elevated semiconductor layer is SiGe or a stacked structure of Si and SiGe.
Thereby, the mobility of electrons can be improved while enabling lattice matching of the elevated semiconductor layer stacked on the semiconductor layer. For this reason, the resistance of the offset drain can be reduced while the elevated semiconductor layer can be stably formed on the semiconductor layer.

Hereinafter, a semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described with reference to the drawings.
1 is a plan view showing a schematic configuration of the semiconductor device according to the first embodiment of the present invention, FIG. 2A is a cross-sectional view taken along line A1-A2 of FIG. 1, and FIG. 1 is a cross-sectional view taken along line B1-B2 in FIG. 1, and FIG. 2C is a cross-sectional view taken along line C1-C2 in FIG.

In FIGS. 1 and 2, a p-type semiconductor layer 2 is formed on the BOX layer 1. As a material of the p-type semiconductor layer 2, for example, Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe, or the like can be used. As the BOX layer 1, for example, An insulating layer such as SiO ₂ , SION, or Si ₃ N ₄ or a buried insulating film can be used. Moreover, as a semiconductor substrate in which the p-type semiconductor layer 2 is formed on the BOX layer 1, for example, an SOI substrate can be used. As the SOI substrate, a SIMOX (Separation by Implanted Oxgen) substrate, a bonded substrate, or a laser is used. An annealed substrate or the like can be used. Further, as the BOX layer 1, an insulating substrate such as sapphire, glass or ceramic may be used. Further, as the p-type semiconductor layer 2, a single crystal semiconductor layer, a polycrystalline semiconductor layer, or an amorphous semiconductor layer may be used.

A gate electrode 4 is formed on the p-type semiconductor layer 2 via a gate insulating film 3, and side walls 10 a and 10 b are formed on the side walls of the gate electrode 4. In the p-type semiconductor layer 2 on the source side, n-type offset source layers 5a and p-type source body connection layers 5b are alternately arranged. The n-type offset source layer 5a and the p-type source body connection layer 5b can be arranged in a self-aligned manner with respect to the gate electrode 4, and the bottom surfaces of the n-type offset source layer 5a and the p-type source body connection layer 5b. Can be brought into contact with the BOX layer 1. In the n-type offset source layer 5a, an n ⁺ -type source layer 8a is formed in a self-aligned manner with the source-side sidewall 10a, and in the p-type source body connection layer 5b, the source-side sidewall 10a is self-aligned. A p ⁺ -type source body connection layer 8b is formed in a consistent manner. In the n ⁺ type source layer 8a and the p ⁺ type source body connection layer 8b, a contact K1 is formed so as to straddle the n ⁺ type source layer 8a and the p ⁺ type source body connection layer 8b. .

An n-type offset drain layer 6 is formed in the p-type semiconductor layer 2 on the drain side. The n-type offset drain layer 6 can be disposed in a self-aligned manner with respect to the gate electrode 4, and the bottom surface of the n-type offset drain layer 6 can be in contact with the BOX layer 1.
On the n-type offset drain layer 6, an n-type elevated semiconductor layer 7 formed in a stripe shape along the current traveling direction is laminated so as to separate the sidewall 10 b from the gate electrode 4. . An insulating layer 21 is stacked on the n-type elevated semiconductor layer 7 formed in a stripe shape. The insulating layer 21 is formed with a trench 21 a disposed between the n-type elevated semiconductor layers 7, and the buried electrode 22 is embedded in the trench 21 a through the insulating layer 21. An n ⁺ type drain layer 9 is formed in the n type elevated semiconductor layer 7 so as to be separated from the gate electrode 4 by a predetermined distance. The n ⁺ type drain layer 9 may be formed not only in the n type elevated semiconductor layer 7 but also in the n type offset drain layer 6. In the n ⁺ type drain layer 9, a contact K 2 for drawing an electrode from the n ⁺ type drain layer 9 is formed.

  Here, the n-type elevated semiconductor layer 7 is formed in a stripe shape on the n-type offset drain layer 6a, and the embedded electrode 22 is embedded in the n-type elevated semiconductor layer 7, thereby enabling the body region to be thinned. The semiconductor layer provided with the offset drain can be thickened, and a buried electrode can be formed on the n-type offset drain layer 6a while suppressing damage to the n-type offset drain layer 6a. it can. For this reason, even when the field effect transistor is operated in the fully depleted mode, it is possible to reduce the on-resistance while suppressing an increase in the impurity concentration of the offset drain, and the defect of the n-type offset drain layer 6a. And the surface electric field of the offset drain can be relaxed while suppressing the increase in capacitance and the increase in capacitance between the source and drain. As a result, it is possible to reduce the power consumption and speed of the field-effect transistor while suppressing the punch-through phenomenon of the source / drain region, the fluctuation of the threshold voltage, and the occurrence of the short channel effect. In addition, it is possible to increase the current and increase the breakdown voltage.

In addition, by raising the offset drain, even when hot carriers are generated in the offset drain, trapping of hot carriers at the interface between the semiconductor layer and the insulating film can be suppressed, and the on-resistance can be reduced. Can be suppressed.
Further, by connecting the buried electrode 22 to the n ⁺ -type source layer 8a, the interface between the n-type offset drain layer 6 and the insulating film 21 covering the buried electrode 22, n, as shown by the oblique lines in FIG. 1 and FIG. The depletion layer can be expanded at the junction interface between the n-type offset drain layer 6 and the p-type semiconductor layer 2 and at the interface between the n-type offset drain layer 6 and the BOX layer 1. For this reason, the electric field of the offset drain can be relaxed, and the off breakdown voltage can be improved.

  On the other hand, when the buried electrode 22 is connected to the gate electrode 4, the interface between the n-type offset drain layer 6 and the insulating film 21 covering the buried electrode 22, and the n-type offset drain layer in the off state where the gate voltage is 0 volts or less. The depletion layer can be expanded at the junction interface between the p-type semiconductor layer 2 and the interface between the n-type offset drain layer 6 and the BOX layer 1. When the gate voltage is higher than 0 volts, a voltage having the same potential as that of the gate electrode 4 can be applied to the embedded electrode 22. For this reason, not only when the field effect transistor is in the off state but also when the field effect transistor is in the on state, the electric field of the offset drain can be relaxed, and not only the off breakdown voltage but also the on breakdown voltage can be improved.

Further, by providing the p-type source body connection layer 5b and the p ⁺ -type source body connection layer 8b on the source side, a source tie structure can be formed. For this reason, hot carriers accumulated in the body region can be released, and the field effect transistor can be operated in the full depletion mode, and deterioration of the drain breakdown voltage can be suppressed.

Note that the impurity concentration of the n-type offset drain layer 6 and the n-type elevated semiconductor layer 7 may gradually decrease from the n ⁺ -type drain layer 9 toward the gate electrode 4.
Thereby, it is possible to reduce the impurity concentration at the body end or the drain end while suppressing an increase in the resistance of the offset drain. For this reason, even when the n-type elevated semiconductor layer 7 is provided in the offset drain, the electric field concentration at the body end or the drain end can be relaxed, and the drain breakdown voltage can be improved.

3 to 5 are cross-sectional views illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention.
In FIG. 3A1 to FIG. 3C1, a p-type semiconductor layer 2 is formed on the BOX layer 1. Then, the gate insulating film 3 is formed on the p-type semiconductor layer 2 by performing thermal oxidation of the p-type semiconductor layer 2. Then, a polycrystalline silicon layer is stacked on the p-type semiconductor layer 2 on which the gate insulating film 3 is formed by a method such as CVD, and the polycrystalline silicon layer is patterned by using a photolithography technique and a dry etching technique. The gate electrode 4 is formed on the gate insulating film 3.

  Then, by using a photolithography technique, a region where the p-type source body connection layer 5b is formed is covered with a first resist pattern. Then, by using the first resist pattern and the gate electrode 4 as a mask, impurities such as As and P are ion-implanted into the p-type semiconductor layer 2 to form the n-type offset source layer 5a on the source side, and n A type offset drain layer 6 is formed on the drain side.

  Next, after removing the first resist pattern, the region where the n-type offset source layer 5a and the n-type offset drain layer 6 are formed is covered with the second resist pattern by using a photolithography technique. Then, using the second resist pattern and the gate electrode 4 as a mask, an impurity such as B is ion-implanted into the p-type semiconductor layer 2 to form the p-type source body connection layer 5b on the source side.

  Next, after removing the second resist pattern, an insulating film is formed on the entire surface of the p-type semiconductor layer 2 by a method such as CVD. Then, the sidewalls 10a and 10b are formed on the side walls of the gate electrode 4 by etching back the insulating film using anisotropic etching such as RIE. Then, an oxide film 11 is formed on the entire surface by a method such as thermal oxidation, and the surface of the n-type offset drain layer 6 is exposed by patterning the oxide film 11 using a photolithography technique and a dry etching technique.

  Next, as shown in FIGS. 3A2 to 3C2, an elevated semiconductor layer is formed on the n-type offset drain layer 6 by epitaxial growth, and impurities such as As and P are formed in the elevated semiconductor layer. The n-type elevated semiconductor layer 7 is formed on the drain side by ion implantation. Here, the oxide film 11 is formed on the n-type offset source layer 5a and the p-type source body connection layer 5b, and epitaxial growth is performed with the surface of the n-type offset drain layer 6 exposed, whereby an n-type offset drain is formed. An elevated semiconductor layer can be selectively formed on the layer 6.

  The material of the n-type elevated semiconductor layer 7 includes, for example, group IV elements such as Si, Ge, SiGe, SiC, SiSn, and PbS, group III-V elements such as GaAs, GaN, InP, and GaP, ZnSe, and the like. II-VI group elements or IV-VI group elements. In particular, when the p-type semiconductor layer 2 is Si, the n-type elevated semiconductor layer 7 is formed on the n-type offset drain layer 6 by using a stacked structure of SiGe or Si and SiGe as the n-type elevated semiconductor layer 7. Can be formed stably, and the mobility of electrons can be improved, and the resistance of the offset drain can be reduced.

In addition, when ion implantation is performed in the elevated semiconductor layer, a thin oxide film may be formed on the surface of the elevated semiconductor layer. Thereby, the impurity concentration of the side wall portion of the n-type elevated semiconductor layer 7 can be made uniform.
Next, as shown in FIGS. 3A3 to 3C3, the oxide film 11 on the n-type offset source layer 5a and the p-type source body connection layer 5b is removed. Then, a third resist pattern that covers the p-type source body connection layer 5b and the n-type elevated semiconductor layer 7 is formed by using a photolithography technique. Then, impurities such as As and P are ion-implanted into the n-type offset source layer 5a using the third resist pattern, the gate electrode 4 and the sidewalls 10a and 10b as a mask, so that the n ⁺ -type source layer 8a is sourced. Form on the side.

Next, after removing the third resist pattern, a fourth resist pattern that covers the n-type offset source layer 5a and the n-type elevated semiconductor layer 7 is formed by using a photolithography technique. Then, by using the fourth resist pattern, the gate electrode 4 and the sidewalls 10a and 10b as a mask, impurities such as B are ion-implanted into the p-type source body connection layer 5b, thereby forming the p ⁺ -type source body connection layer 8b. Form on the source side.

Next, after removing the fourth resist pattern, a fifth resist pattern that exposes the n-type elevated semiconductor layer 7 is formed at a predetermined interval from the gate electrode 4 by using a photolithography technique. Then, the fifth resist pattern as a mask, As, by ion-implanting an impurity such as P to n-type elevated semiconductor layer 7, n ⁺ -type drain layer which is spaced from the gate electrode 4 by a predetermined distance 9 is formed.

  Next, after removing the fifth resist pattern, a sixth resist pattern that exposes the n-type elevated semiconductor layer 7 in a stripe shape is formed by using a photolithography technique. Then, by etching the n-type elevated semiconductor layer 7 using the sixth resist pattern as a mask, the n-type elevated semiconductor layer 7 is processed into a stripe shape.

  Here, by processing the n-type elevated semiconductor layer 7 into a stripe shape, the embedded electrode 22 can be formed on the n-type offset drain layer 6 without causing etching damage to the n-type offset drain layer 6. It becomes. For this reason, it is possible to reduce the output capacity of the field effect transistor while suppressing the occurrence of defects in the n-type offset drain layer 6 and to alleviate the electric field of the offset drain.

Next, as shown in FIGS. 4A1 to 4C1, after removing the sixth resist pattern, an insulating film 21 is deposited on the entire surface by a method such as CVD. For example, a silicon oxide film or the like can be used as the insulating film 21.
Next, as shown in FIGS. 4A2 to 4C2, a seventh resist that exposes the insulating film 21 in the gaps of the n-type elevated semiconductor layer 7 by using a photolithography technique. Form a pattern. Then, by performing half etching of the insulating film 21 using the seventh resist pattern as a mask, the trench 21a disposed corresponding to the gap of the n-type elevated semiconductor layer 7 is processed into the insulating film 21.

  Next, as shown in FIGS. 4A3 to 4C3, after removing the seventh resist pattern, a metal film such as Al is formed on the entire surface by a method such as sputtering. Then, by using a photolithography technique, an eighth resist pattern that covers the metal film embedded in the trench 21a is formed. Then, by etching the metal film using the eighth resist pattern as a mask, the embedded electrode 22 embedded in the trench 21 a is formed through the insulating film 21.

Note that an oxide film between the n-type elevated semiconductor layer 7 and the buried electrode 22 may be formed by oxidation of the surface of the n-type elevated semiconductor layer 7. Since the offset drain is raised, defects generated in the channel region due to oxidation can be reduced.
Next, as shown in FIGS. 5A to 5C, after removing the eighth resist pattern, an insulating film 23 is deposited on the entire surface by a method such as CVD. Then, by using a photolithography technique and an etching technique, an opening 23a exposing the surface of the embedded electrode 22 is formed in the insulating film 23, and the surfaces of the n ⁺ type source layer 8a and the p ⁺ type source body connection layer 8b An opening 23b that exposes is formed in the insulating film 23. Then, a metal film such as Al is formed on the entire surface by a method such as sputtering, and the n ⁺ type source layer 8a and the p ⁺ type source body connection layer are formed by patterning the metal film using a photolithography technique and an etching technique. A wiring layer 24 connecting 8b and the buried electrode 22 is formed.

  As a result, it is possible to form the buried electrode 22 on the n-type offset drain layer 6 while suppressing damage to the n-type offset drain layer 6, and while suppressing the complication of the manufacturing process, A structure can be provided. For this reason, while suppressing an increase in on-resistance, it is possible to increase the current, increase the breakdown voltage, and increase the speed, and also allow the hot carriers accumulated in the body region to escape, thereby reducing the drain breakdown voltage. Can be suppressed.

  Further, when a silicon oxide film is used as the insulating film 21 for embedding the buried electrode 22, the dielectric constant of the silicon oxide film is about 1/3 of the dielectric constant of silicon. Compared with the junction capacitance, the capacitance between the n-type offset drain layer 6 or the n-type elevated semiconductor layer 7 and the buried electrode 22 can be reduced. For this reason, compared with the case where the multi-resurf structure in which n-type regions and p-type regions are alternately arranged is applied to the offset drain, the capacitance between the source / drain can be reduced and high-speed operation can be realized. Can do.

FIG. 6 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the second embodiment of the present invention.
6A to 6C, when the buried electrode 22 is formed, the insulating film 25 is deposited on the entire surface by a method such as CVD. Then, using the photolithography technique and the etching technique, openings 25a and 25b exposing the surfaces of the buried electrode 22 and the gate electrode 4 are formed in the insulating film 25, respectively. Then, a metal film such as Al is formed on the entire surface by a method such as sputtering, and the metal film is patterned using a photolithography technique and an etching technique, thereby forming a wiring layer 26 for connecting the embedded electrode 22 and the gate electrode 4. Form.

Accordingly, the field of the offset drain can be relaxed not only when the field effect transistor is in the off state but also when the field effect transistor is in the on state, and not only the off breakdown voltage but also the on breakdown voltage can be improved.
FIG. 7 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the third embodiment of the present invention.
7 (a1) to 7 (c1), when the sidewalls 10a and 10b are formed on the sidewalls of the gate electrode 4, respectively, the oxide film 11 ′ is formed on the entire surface of the p-type semiconductor layer 2 by a method such as thermal oxidation. Form. Then, the surface of the n-type offset drain layer 6 is exposed in a stripe pattern by patterning the oxide film 11 ′ using a photolithography technique and a dry etching technique.

  Next, as shown in FIGS. 7A2 to 7C2, an elevated semiconductor layer is formed on the n-type offset drain layer 6 by epitaxial growth, and impurities such as As and P are formed in the elevated semiconductor layer. The n-type elevated semiconductor layer 7 is formed on the drain side by ion implantation. Here, by forming an oxide film 11 ′ on the n-type offset source layer 5 a and the p-type source body connection layer 5 b and performing epitaxial growth with the surface of the n-type offset drain layer 6 exposed in a stripe shape, An elevated semiconductor layer can be formed in stripes on the n-type offset drain layer 6. When the n-type elevated semiconductor layer 7 is formed in a stripe shape on the n-type offset drain layer 6, the oxide film 11 on the n-type offset source layer 5a and the p-type source body connection layer 5b is removed.

  As a result, the n-type elevated semiconductor layer 7 can be formed in a stripe shape without etching the n-type elevated semiconductor layer 7, and not only the n-type offset drain layer 6 but also the n-type elevated semiconductor. The embedded electrode 22 can be formed in the n-type elevated semiconductor layer 7 while suppressing damage to the layer 7. For this reason, it is possible to reduce the output capacity of the field effect transistor while suppressing the occurrence of defects in the n-type offset drain layer 6 and the n-type elevated semiconductor layer 7 and to relax the electric field of the offset drain. It becomes possible to do.

  In the above-described embodiment, an n-channel MOS transistor has been described as an example. However, the present invention may be applied to a p-channel MOS transistor. In the above-described embodiment, the field effect transistor formed on the SOI substrate has been described as an example. However, in addition to the field effect transistor formed on the SOI substrate, for example, a TFT (Thin Film Transistor) or the like. You may apply to. In the above-described embodiment, the method of providing the source tie structure on the source side has been described. However, the source tie structure may be omitted.

1 is a plan view showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention. 1 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment of this invention.

Explanation of symbols

1 BOX layer, 2 p-type semiconductor layer, 3 gate insulating film, 4 gate electrode, 5a n-type offset source layer, 5b p-type source body connection layer, 6 n-type offset drain layer, 7 n-type elevated semiconductor layer, 8a n ⁺ type source layer, 8b p ⁺ type source body connection layer, 9 n ⁺ type drain layer, 10a, 10b sidewall, K1, K2 contact, 11, 11 ′ oxide film, 21, 23, 25 insulating film, 21a trench 22 embedded electrode, 23a, 23b, 25a, 25b opening, 24, 26 wiring layer

Claims (13)

In a semiconductor device in which a field effect transistor having a buried electrode in an offset drain is formed,
A semiconductor device, wherein a thickness of a semiconductor layer provided with the offset drain is larger than a thickness of a semiconductor layer on a source side.   The semiconductor device according to claim 1, wherein a source tie structure is provided on the source side.   3. The semiconductor device according to claim 1, wherein the impurity concentration of the offset drain gradually decreases from the drain toward the gate.   The semiconductor device according to claim 1, wherein the field effect transistor is formed on an SOI substrate.   The semiconductor device according to claim 1, wherein the embedded electrode is connected to a source.   The semiconductor device according to claim 1, wherein the embedded electrode is connected to a gate. A semiconductor layer stacked on an insulator;
A gate electrode formed on the semiconductor layer;
A first conductivity type body region provided in the semiconductor layer and disposed under the gate electrode;
A second conductivity type source region provided on the semiconductor layer and disposed on one side of the gate electrode;
A second conductivity type offset drain layer disposed on the other side of the gate electrode;
A second conductivity type elevated semiconductor layer disposed on the second conductivity type offset drain layer and formed in a stripe shape along a current traveling direction;
Embedded electrodes embedded in the second conductive type elevated semiconductor layer formed in the stripe shape through an insulating film;
A semiconductor device comprising: a second conductivity type drain region disposed at a predetermined interval from the gate electrode. A first conductivity type source body connection region provided in the second conductivity type source region and disposed so as to be in contact with the first conductivity type body region;
8. The semiconductor device according to claim 7, further comprising a contact disposed so as to straddle the second conductivity type source region and the first conductivity type source body connection region. Forming a gate electrode on the first conductivity type semiconductor layer formed on the insulator;
Forming a second conductivity type offset drain layer by ion-implanting the first conductivity type semiconductor layer on the drain side using the gate electrode as a mask;
Forming a sidewall on the sidewall of the gate electrode;
Forming a second conductivity type elevated semiconductor layer disposed in a stripe shape along the current traveling direction on the second conductivity type offset drain layer;
Forming a second conductivity type source region by performing ion implantation into the second conductivity type semiconductor layer on the source side using the gate electrode and the sidewall as a mask;
Forming a second conductivity type drain region disposed at a predetermined distance from the gate electrode;
Depositing an insulating film on the second conductivity type elevated semiconductor layer;
Forming a trench disposed in the gap between the second conductivity type elevated semiconductor layers in the insulating film;
And a step of forming a buried electrode buried in the trench. Forming a gate electrode on the first conductivity type semiconductor layer formed on the insulator;
Forming a second conductivity type offset drain layer by ion-implanting the first conductivity type semiconductor layer on the drain side using the gate electrode as a mask;
Forming an offset source layer in which first conductivity type regions and second conductivity type regions are alternately arranged by performing ion implantation on the first conductivity type semiconductor layer on the source side using the gate electrode as a mask; ,
Forming a sidewall on the sidewall of the gate electrode;
Forming a second conductivity type elevated semiconductor layer disposed in a stripe shape along the current traveling direction on the second conductivity type offset drain layer;
Forming a first resist pattern covering a region near the gate of the second conductivity type elevated semiconductor layer and a first conductivity type region of the offset source layer;
Forming a second conductivity type source region and a second conductivity type drain region by performing ion implantation using the first resist pattern, the gate electrode and the sidewall as a mask;
Forming a second resist pattern covering the second conductivity type elevated semiconductor layer and the second conductivity type region of the offset source layer;
Forming a first conductivity type source body connection region in the first conductivity type region of the offset source layer by performing ion implantation using the second resist pattern, the gate electrode and the sidewall as a mask;
Depositing an insulating film on the second conductivity type elevated semiconductor layer;
Forming a trench disposed in the gap between the second conductivity type elevated semiconductor layers in the insulating film;
Forming a buried electrode embedded in the trench;
Forming a contact disposed so as to straddle the second conductivity type source region and the first conductivity type source body connection region. The step of forming the second conductivity type elevated semiconductor layer arranged in the stripe shape,
Forming an oxide film patterned to expose the surface of the second conductivity type offset drain layer;
Epitaxially growing an elevated semiconductor layer on the second conductivity type offset drain layer;
Forming a second conductivity type elevated semiconductor layer by implanting ions of a second conductivity type impurity into the elevated semiconductor layer;
11. The method of manufacturing a semiconductor device according to claim 9, further comprising a step of etching the second conductivity type elevated semiconductor layer in a stripe shape. The step of forming the second conductivity type elevated semiconductor layer arranged in the stripe shape,
Forming an oxide film patterned so that the surface of the second conductivity type offset drain layer is exposed in a stripe pattern;
Forming an elevated semiconductor layer arranged in stripes on the offset drain layer by epitaxial growth using the oxide film as a mask;
11. The method of manufacturing a semiconductor device according to claim 9, further comprising a step of forming a second conductivity type elevated semiconductor layer by performing ion implantation of a second conductivity type impurity into the elevated semiconductor layer. Method.   13. The method of manufacturing a semiconductor device according to claim 9, wherein the semiconductor layer is Si, and the elevated semiconductor layer is SiGe or a stacked structure of Si and SiGe.

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