JP2005260235A - トレンチ内に独立制御可能な制御ゲートを有する埋込ビット線型不揮発性浮遊ゲートメモリセル、そのアレイ、及び製造方法 - Google Patents

トレンチ内に独立制御可能な制御ゲートを有する埋込ビット線型不揮発性浮遊ゲートメモリセル、そのアレイ、及び製造方法 Download PDF

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Publication number
JP2005260235A
JP2005260235A JP2005065101A JP2005065101A JP2005260235A JP 2005260235 A JP2005260235 A JP 2005260235A JP 2005065101 A JP2005065101 A JP 2005065101A JP 2005065101 A JP2005065101 A JP 2005065101A JP 2005260235 A JP2005260235 A JP 2005260235A
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Japan
Prior art keywords
region
trench
floating gate
forming
gate electrode
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JP2005065101A
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Japanese (ja)
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JP2005260235A5 (enExample
Inventor
Dana Lee
リー ダナ
Bomy Chen
チェン ボミー
Sohrab Kianian
キアニアン ソーラブ
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Silicon Storage Technology Inc
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Silicon Storage Technology Inc
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Publication date
Priority claimed from US10/797,296 external-priority patent/US7307308B2/en
Application filed by Silicon Storage Technology Inc filed Critical Silicon Storage Technology Inc
Publication of JP2005260235A publication Critical patent/JP2005260235A/ja
Publication of JP2005260235A5 publication Critical patent/JP2005260235A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs

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  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
JP2005065101A 2004-03-09 2005-03-09 トレンチ内に独立制御可能な制御ゲートを有する埋込ビット線型不揮発性浮遊ゲートメモリセル、そのアレイ、及び製造方法 Pending JP2005260235A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/797,296 US7307308B2 (en) 2003-04-07 2004-03-09 Buried bit line non-volatile floating gate memory cell with independent controllable control gate in a trench, and array thereof, and method of formation

Publications (2)

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JP2005260235A true JP2005260235A (ja) 2005-09-22
JP2005260235A5 JP2005260235A5 (enExample) 2008-04-24

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JP2005065101A Pending JP2005260235A (ja) 2004-03-09 2005-03-09 トレンチ内に独立制御可能な制御ゲートを有する埋込ビット線型不揮発性浮遊ゲートメモリセル、そのアレイ、及び製造方法

Country Status (4)

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JP (1) JP2005260235A (enExample)
KR (1) KR20060043534A (enExample)
CN (1) CN1691336A (enExample)
TW (1) TW200601461A (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016515771A (ja) * 2013-04-16 2016-05-30 シリコン ストーリッジ テクノロージー インコーポレイテッドＳｉｌｉｃｏｎ Ｓｔｏｒａｇｅ Ｔｅｃｈｎｏｌｏｇｙ， Ｉｎｃ． 自己整列浮遊及び消去ゲートを有する不揮発性メモリセル及びその製造方法
CN110010606A (zh) * 2018-01-05 2019-07-12 硅存储技术公司 衬底沟槽中具有浮栅的双位非易失性存储器单元
WO2025074208A1 (ja) * 2023-10-04 2025-04-10 株式会社半導体エネルギー研究所 半導体装置

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4868629A (en) * 1984-05-15 1989-09-19 Waferscale Integration, Inc. Self-aligned split gate EPROM
US5160986A (en) * 1988-12-05 1992-11-03 Sgs-Thomson Microelectronics S.R.L. Matrix of EPROM memory cells with a tablecloth structure having an improved capacitative ratio and a process for its manufacture
US5278439A (en) * 1991-08-29 1994-01-11 Ma Yueh Y Self-aligned dual-bit split gate (DSG) flash EEPROM cell
US5412600A (en) * 1991-10-09 1995-05-02 Mitsubishi Denki Kabushiki Kaisha Non-volatile semiconductor device with selecting transistor formed between adjacent memory transistors
US5414693A (en) * 1991-08-29 1995-05-09 Hyundai Electronics Industries Co., Ltd. Self-aligned dual-bit split gate (DSG) flash EEPROM cell
US5786612A (en) * 1995-10-25 1998-07-28 Mitsubishi Denki Kabushiki Kaisha Semiconductor device comprising trench EEPROM
US6331721B1 (en) * 1996-12-09 2001-12-18 Mosel Vitelic Inc Memory cell with built in erasure feature
US20030223296A1 (en) * 2002-04-05 2003-12-04 Hu Yaw Wen Self-aligned method of forming a semiconductor memory array of floating gate memory cells with buried source line and floating gate, and a memory array made thereby

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4868629A (en) * 1984-05-15 1989-09-19 Waferscale Integration, Inc. Self-aligned split gate EPROM
US5160986A (en) * 1988-12-05 1992-11-03 Sgs-Thomson Microelectronics S.R.L. Matrix of EPROM memory cells with a tablecloth structure having an improved capacitative ratio and a process for its manufacture
US5278439A (en) * 1991-08-29 1994-01-11 Ma Yueh Y Self-aligned dual-bit split gate (DSG) flash EEPROM cell
US5414693A (en) * 1991-08-29 1995-05-09 Hyundai Electronics Industries Co., Ltd. Self-aligned dual-bit split gate (DSG) flash EEPROM cell
US5412600A (en) * 1991-10-09 1995-05-02 Mitsubishi Denki Kabushiki Kaisha Non-volatile semiconductor device with selecting transistor formed between adjacent memory transistors
US5786612A (en) * 1995-10-25 1998-07-28 Mitsubishi Denki Kabushiki Kaisha Semiconductor device comprising trench EEPROM
US6331721B1 (en) * 1996-12-09 2001-12-18 Mosel Vitelic Inc Memory cell with built in erasure feature
US20030223296A1 (en) * 2002-04-05 2003-12-04 Hu Yaw Wen Self-aligned method of forming a semiconductor memory array of floating gate memory cells with buried source line and floating gate, and a memory array made thereby

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016515771A (ja) * 2013-04-16 2016-05-30 シリコン ストーリッジ テクノロージー インコーポレイテッドＳｉｌｉｃｏｎ Ｓｔｏｒａｇｅ Ｔｅｃｈｎｏｌｏｇｙ， Ｉｎｃ． 自己整列浮遊及び消去ゲートを有する不揮発性メモリセル及びその製造方法
CN110010606A (zh) * 2018-01-05 2019-07-12 硅存储技术公司 衬底沟槽中具有浮栅的双位非易失性存储器单元
EP3735705A4 (en) * 2018-01-05 2022-01-26 Silicon Storage Technology, Inc. DOUBLE-BIT NON-VOLATILE MEMORY CELLS WITH FLOATING GATES IN SUBSTRATE TREES
CN110010606B (zh) * 2018-01-05 2023-04-07 硅存储技术公司 衬底沟槽中具有浮栅的双位非易失性存储器单元
EP4301107A3 (en) * 2018-01-05 2024-04-03 Silicon Storage Technology Inc. Twin bit non-volatile memory cells with floating gates in substrate trenches
WO2025074208A1 (ja) * 2023-10-04 2025-04-10 株式会社半導体エネルギー研究所 半導体装置

Also Published As

Publication number Publication date
KR20060043534A (ko) 2006-05-15
TW200601461A (en) 2006-01-01
CN1691336A (zh) 2005-11-02

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