JP2005260235A5 - - Google Patents

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Publication number
JP2005260235A5
JP2005260235A5 JP2005065101A JP2005065101A JP2005260235A5 JP 2005260235 A5 JP2005260235 A5 JP 2005260235A5 JP 2005065101 A JP2005065101 A JP 2005065101A JP 2005065101 A JP2005065101 A JP 2005065101A JP 2005260235 A5 JP2005260235 A5 JP 2005260235A5
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JP
Japan
Prior art keywords
trench
region
bottom wall
sidewall
along
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2005065101A
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English (en)
Japanese (ja)
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JP2005260235A (ja
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Publication date
Priority claimed from US10/797,296 external-priority patent/US7307308B2/en
Application filed filed Critical
Publication of JP2005260235A publication Critical patent/JP2005260235A/ja
Publication of JP2005260235A5 publication Critical patent/JP2005260235A5/ja
Pending legal-status Critical Current

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JP2005065101A 2004-03-09 2005-03-09 トレンチ内に独立制御可能な制御ゲートを有する埋込ビット線型不揮発性浮遊ゲートメモリセル、そのアレイ、及び製造方法 Pending JP2005260235A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/797,296 US7307308B2 (en) 2003-04-07 2004-03-09 Buried bit line non-volatile floating gate memory cell with independent controllable control gate in a trench, and array thereof, and method of formation

Publications (2)

Publication Number Publication Date
JP2005260235A JP2005260235A (ja) 2005-09-22
JP2005260235A5 true JP2005260235A5 (enExample) 2008-04-24

Family

ID=35085603

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005065101A Pending JP2005260235A (ja) 2004-03-09 2005-03-09 トレンチ内に独立制御可能な制御ゲートを有する埋込ビット線型不揮発性浮遊ゲートメモリセル、そのアレイ、及び製造方法

Country Status (4)

Country Link
JP (1) JP2005260235A (enExample)
KR (1) KR20060043534A (enExample)
CN (1) CN1691336A (enExample)
TW (1) TW200601461A (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9293204B2 (en) * 2013-04-16 2016-03-22 Silicon Storage Technology, Inc. Non-volatile memory cell with self aligned floating and erase gates, and method of making same
CN110010606B (zh) * 2018-01-05 2023-04-07 硅存储技术公司 衬底沟槽中具有浮栅的双位非易失性存储器单元
WO2025074208A1 (ja) * 2023-10-04 2025-04-10 株式会社半導体エネルギー研究所 半導体装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4868629A (en) * 1984-05-15 1989-09-19 Waferscale Integration, Inc. Self-aligned split gate EPROM
IT1227989B (it) * 1988-12-05 1991-05-20 Sgs Thomson Microelectronics Matrice di celle di memoria eprom con struttura a tovaglia con migliorato rapporto capacitivo e processo per la sua fabbricazione
US5278439A (en) * 1991-08-29 1994-01-11 Ma Yueh Y Self-aligned dual-bit split gate (DSG) flash EEPROM cell
ATE238609T1 (de) * 1991-08-29 2003-05-15 Hyundai Electronics Ind Selbstjustierende flash-eeprom-zelle mit doppelbit-geteiltem gat
JPH05211338A (ja) * 1991-10-09 1993-08-20 Mitsubishi Electric Corp 不揮発性半導体装置
JP3403877B2 (ja) * 1995-10-25 2003-05-06 三菱電機株式会社 半導体記憶装置とその製造方法
US5963806A (en) * 1996-12-09 1999-10-05 Mosel Vitelic, Inc. Method of forming memory cell with built-in erasure feature
US6952034B2 (en) * 2002-04-05 2005-10-04 Silicon Storage Technology, Inc. Semiconductor memory array of floating gate memory cells with buried source line and floating gate

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