JP2005258991A - Standby control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize low power consumption at standby state of a device using only a main microcomputer and without the need of supplying power to an external ROM at the standby state. <P>SOLUTION: This standby control method, for a system which is composed of the microcomputer B01 having a built-in RAM B04, the external ROM B06, and a power source B07 driving the microcomputer B01 and the external ROM B06, and which has a program for performing processing for entering the standby state and processing recovering from the standby state on the external ROM B06, includes: a process for developing the program on the external ROM B06 to the built-in RAM B04; a process for changing an execution address for entering the standby state from the external ROM B06 to the built-in RAM B04; a process for turning power to the external ROM B06 OFF; a process for changing a program execution address at the time of recovery from the standby from the external ROM B06 to the built-in RAM B04; and a process for stopping a clock and entering the standby state. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a standby state control method for a system having a program in an external ROM and having a microcomputer with a built-in RAM.

  FIG. 15 is a configuration diagram of the conventional system, and FIG. 16 is a flowchart of the process for shifting to the standby state and the process for returning from the standby state in the conventional system. The conventional process will be described below.

  As shown in FIG. 15, the conventional method in the microcomputer A01 is executed by a program in the external ROM A06 and is always processed with an execution address on the external ROM A06 when an interrupt occurs, and has a function (ROM collection A05) for changing the program execution address. Explain.

  Conventionally, the microcomputer A01 that executes a program stored in the external ROM A06 executes processing on the external ROM A06 even when shifting to a standby state. As shown in FIG. 16, all interrupts are prohibited so that other interrupt processing does not enter during the transition to the standby state (C01), only interrupts necessary for returning from the standby state are permitted (C02), The clock is stopped (C03) and a transition is made to a standby state (C04).

  At this time, since the program on the external ROM A06 is also executed when returning from the standby state, it is necessary to supply power to the external ROM A06 even in the standby state.

  When returning from the standby state, an interrupt for returning to the standby state occurs (C05), the processing on the external ROMA06 is executed, and initialization processing such as permission of interruption necessary for normal processing is performed (C06) normal processing Migrate to

On the other hand, in order to realize low power consumption of the entire device during standby, measures such as installing a dedicated sub-microcomputer during standby that consumes less power than the combined power consumption of both the main microcomputer and the external ROM device are available. (For example, refer to Patent Document 1).
JP 2001-145355 A

  However, installing a sub-microcomputer separately from the main microcomputer creates a risk in terms of board area and cost.

  Accordingly, an object of the present invention is to provide a standby state control method that uses only the main microcomputer and does not require power supply to the external ROM in the standby state, and can realize low power consumption in the standby state of the apparatus. It is to be.

  In order to solve the above problems, a standby state control method according to claim 1 of the present invention comprises a microcomputer having an internal RAM, an external ROM, and a power source for driving the microcomputer and the external ROM. And a standby state control method for a system having a program in which a program for executing a process for entering the standby state on the external ROM and a process for returning from the standby state is developed in the built-in RAM, and enters the standby state. A program execution address for changing from the external ROM to the built-in RAM, a step of turning off the power to the external ROM, and a program execution address when returning from a standby state from the external ROM to the built-in RAM And a step of stopping the clock and entering a standby state.

  The standby state control method according to claim 2 is the standby state control method according to claim 1, wherein the microcomputer in the standby state is restored and the clock stop is canceled by processing of the built-in RAM, and the power supply to the external ROM And a step of shifting from the built-in RAM to the processing of the external ROM.

  The standby state control method according to claim 3 is the standby state control method according to claim 1, wherein the size of the internal RAM and the processing to be expanded in the internal RAM are expanded before the processing of the external ROM is expanded in the internal RAM. When the size of the process to be expanded is large, the process of expanding the process of the external ROM in the internal RAM is not performed and the clock is stopped and released by the process of the external ROM.

  The standby state control method according to claim 4 is the standby state control method according to claim 1 or 2, which is necessary for developing the processing of the external ROM before developing the processing of the external ROM in the built-in RAM. The process of saving the address and value of the data distributed on the internal RAM to secure the area, and the value of the saved data is set to the address before waiting when returning from the standby state. Restoring the built-in RAM data.

  The standby state control method according to claim 5 is the standby state control method according to claim 1 or 2, wherein before the processing of the external ROM is expanded in the internal RAM, the unused size of the internal RAM and the internal RAM If the size of the process to be expanded is compared, and if the size of the process to be expanded is large, a plurality of processes having a size that can be accommodated in the unused size of the built-in RAM including the minimum steps necessary for returning from the standby state A step of selecting from among them and expanding the built-in RAM.

  According to the standby state control method of the first aspect of the present invention, a step for developing a program for executing a process for entering the standby state on the external ROM and a process for returning from the standby state into the built-in RAM, and entering the standby state Changing the program execution address for the external ROM from the internal RAM, turning off the power to the external ROM, and changing the program execution address at the time of return from the standby state from the external ROM to the internal RAM And the step of stopping the clock and entering the standby state, the power supply to the external ROM during standby can be cut off, and the entire apparatus can realize low power consumption in the standby state.

  According to a second aspect of the present invention, the microcomputer in the standby state is restored, the process of releasing the clock stop by the process of the internal RAM, the process of turning on the power to the external ROM, and the process of shifting from the internal RAM to the process of the external ROM Therefore, it is possible to return from the standby state to normal processing by the external ROM.

  According to a third aspect of the present invention, before expanding the processing of the external ROM in the internal RAM, the size of the internal RAM is compared with the size of the processing expanded in the internal RAM. Since the clock is stopped and released in the processing of the external ROM without performing the steps after the processing of expanding the processing, if the size of the processing to be expanded is larger, power is supplied to the external ROM even in the standby state as before. The process shifts to the standby state, and processing is performed in the external ROM even when the standby state is restored.

  According to a fourth aspect of the present invention, before expanding the processing of the external ROM in the internal RAM, the step of saving the addresses and values of the data distributed on the internal RAM in order to secure an area necessary for expanding the processing of the external ROM. And restoring the data stored in the built-in RAM by setting the value of the saved data to the address before the standby when returning from the standby state. It is possible to solve the problem when there is necessary internal RAM data and a continuous area for expanding the external ROM cannot be secured in the internal RAM.

  According to a fifth aspect of the present invention, before the processing of the external ROM is expanded in the internal RAM, the unused size of the internal RAM is compared with the size of the processing expanded in the internal RAM. Low processing consumption even when the built-in RAM is small, because it includes a process of selecting from a plurality of processes the size of a process that fits in the unused size of the built-in RAM, including the minimum process required for recovery. Power control can be performed.

  A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a system configuration diagram in the standby state control method of the first embodiment of the present invention, and FIG. 2 is a flowchart of the first embodiment.

  As shown in FIG. 1, the microcomputer B01 has a built-in RAM B04, has an execution program in an external ROM B06, and operates by receiving power supply from a power supply B07. The microcomputer B01 has a function of changing the program execution address (hereinafter referred to as ROM collection B05), and returns from the standby state to the normal state by an external interrupt B03.

  As shown in FIG. 2, before entering the standby state for stopping the clock, the microcomputer B01 expands the process for entering the standby state and the process for returning from the standby state to the normal state from the external ROM B06 to the built-in RAM B04 (D01). A jump is made to the processing on the expanded internal RAM B04 (D02), and the processing for entering the standby state is performed on the internal RAM B04 (D03).

  As a process for entering the standby state, first, all interrupts are prohibited so that no interrupt process occurs during the transition to the standby state (D04), and the power supply from the power source B07 to the external ROM B06 is turned off (D0 / 5). Since it is already operating on the built-in RAM B04, it operates without any problem even if no power is supplied to the external ROM B06. Since the power to the external ROM B06 is cut, the terminal is set to prevent malfunction of the terminal connected to the external ROM B06 to the microcomputer B01 (D06).

  Next, the ROM collection B05 is set so that the program on the internal RAM B04 is executed when returning from the standby state (D07). That is, the program execution address at the return from the standby state is changed from the external ROM B06 to the built-in RAM B04. An interrupt necessary for returning from the standby state is permitted (D08), the clock is stopped (D09), and the standby state is entered (D10). Since power supply from the power supply B07 to the external ROM B06 is cut off, lower power consumption than in the prior art can be realized in the standby state.

  Further, the order of the steps from the step of turning off the power supply to the external ROM B06 (D05) to the step of setting the ROM collection B05 (D07) may be switched.

  Here, the ROM collection will be described. FIG. 3 is a block diagram of the ROM collection. The ROM address P08 designated by the instruction pointer (IP) of the CPUP01 is always monitored by the coincidence detection circuit P02, and when it matches the address set in the correction address register P05, the previous correction address is substituted for the output data from the ROMP07. The correction ROM data from the correction data register P06 paired with is supplied to the CPUP01.

  Using this function, the access to the execution address on the external ROM B06 is normally replaced with the jump process to the internal RAM B04 by the external interrupt B03. Thus, the program execution address can be changed to the built-in RAM B04 instead of the external ROM B06.

  As described above, according to the present embodiment, before the microcomputer enters the standby state, the processing for entering the standby state into the internal RAM and the processing necessary until the main power is turned on are expanded and the execution address is changed to the internal RAM. Further, the function for changing the program execution address is used to change the program execution address to be accessed by an external interrupt for returning to the standby state to the area of the built-in RAM and enter the standby state. As a result, power supply to the external ROM during standby can be cut, and low power consumption in the standby state can be realized as the entire apparatus.

  A second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a flowchart of the standby state control method according to the second embodiment of the present invention.

  As shown in FIG. 4, in the first embodiment, when an interrupt occurs during standby, the program on the internal RAM B04 is executed by the ROM collection B05 set before entering the standby state, and the clock stop is released. .

  Terminal settings are made to operate the external ROM B06 (E01), the power supply to the external ROM B06 is turned on (E02), and a jump is made from the built-in RAM B04 to the processing on the external ROM B06 (E03).

  Initialization processing from the standby state to the normal state such as permission of interruption is performed (E04), and the processing returns to the normal processing.

  The order of terminal setting (E01) and power supply (E02) of the external ROMB06, jump to the external ROMB06 (E03), and initialization processing (E04) may be switched. The initialization process (E04) may be an external ROM or a built-in RAM.

  A third embodiment of the present invention will be described with reference to FIGS. FIG. 5 is an image diagram showing a third embodiment of the present invention, and FIG. 6 is a flowchart showing an outline of the third embodiment.

  In the first embodiment, when the processing on the external ROM is expanded to the built-in RAM, there is a problem when the size of the processing on the external ROM is larger than the size of the built-in RAM. This embodiment can solve this problem.

  That is, as shown in FIGS. 5 and 6, in the first embodiment, before the processing on the external ROM is expanded to the internal RAM, the size of the expansion processes F03 and F06 and the size of the internal RAM F01 and F04 are compared. Is performed (G01).

  When the size of the built-in RAM F01 is larger, the processing step F03 is expanded to the built-in RAM F01 (G04), and the steps after D03 in FIG. 2 are performed on the built-in RAM F01 (G06).

  If the size of the process F06 to be expanded is larger, the expansion to the built-in RAM F04 is not performed (G02), and power is supplied to the external ROM F05 (B06) even in the standby state as before, and the external ROM B06 is restored even after returning to the standby state. The clock is stopped and released at (G03).

  A fourth embodiment of the present invention will be described with reference to FIGS. 7 and 8 are image diagrams showing a fourth embodiment of the present invention, and FIGS. 9 and 10 are flowcharts showing an outline of the fourth embodiment.

  In the first embodiment, when the processing on the external ROM is expanded to the internal RAM, when the data on the internal RAM necessary for returning from the standby state is left, if the data is left at the address as it is, the data on the external ROM is stored. There may be a case where a continuous area in the built-in RAM necessary for developing the processing cannot be secured. This embodiment can solve this problem.

  That is, as shown in FIG. 7, as data necessary for the standby state, for example, in a TV system, there are image quality information data AH07 such as contrast and audio information data BH08 such as volume. In the normal state, these data H07 and H08 are in the built-in RAM H02. If these data H07 and H08 are left at the same addresses, the processing H03 on the external ROM required for recovery from the standby state is expanded. It is assumed that a continuous area of the built-in RAM H02 necessary for the above cannot be secured (H04, H11). Therefore, before the processing of the external ROM H01 is expanded in the internal RAM H02 in the first embodiment, the address and value of the data distributed on the internal RAM H02 are saved, and the data is saved when returning from the standby state. Restoring the data stored in the built-in RAM H02 by setting the data value to the address before standby.

  Specifically, as shown in FIGS. 7 and 9, the data addresses H09 and H10 and the data values H07 and H08 necessary for returning from the standby state are acquired (J01), and the continuous area of the built-in RAM H02 is obstructed. Evacuate to an area that does not become necessary (J02, H05). By saving the data H07 and H08 necessary for the restoration, it is possible to secure a continuous area of the built-in RAM necessary for developing the processing H03 on the external ROM necessary for the restoration from the standby state (H06). As a result, the processing H03 of the external ROM is expanded to the built-in RAM (J03, H12), and processing to a standby state after D03 in FIG. 2 is performed.

  As shown in FIGS. 8 and 10, when returning from the standby state, in the initialization (K06) after changing the execution address of the return process from the internal RAMB04 to the external ROMB06 (K03) (E03, E04 in FIG. 4) (Similar process), the addresses I05 and I07 and the data values I06 and I08 saved before entering the standby state are acquired (K04), and the data I06 and I08 are restored to the addresses I05 and I07 (K05).

  As a result, there is a built-in RAM data necessary for returning from the standby state, and it is possible to solve a problem in a case where a continuous area for developing the external ROM cannot be secured in the built-in RAM.

  A fifth embodiment of the present invention will be described with reference to FIGS. FIG. 11 is an image diagram showing a fifth embodiment of the present invention, and FIG. 12 is a flowchart showing an outline of the fifth embodiment.

  In the third embodiment, since there is only two choices of returning from the standby state with the built-in RAM or returning with the external ROM as usual, if the built-in RAM is small, the possibility of realizing low power consumption control is reduced. End up. With this embodiment, the possibility of performing low power consumption control can be increased.

  As shown in FIG. 11 and FIG. 12, the processing on the external ROMs L02 and L08 developed in the first embodiment includes a plurality of patterns including processes L03 and L09 that are necessary for returning from the internal RAMs L01 and L07 in advance. Steps (L04, L05, L10, L11) are prepared. Before the processing on the external ROM L02 is expanded to the internal RAMs L01 and L07 (M04), the size of each expansion process (L03, L04, L05, L09, L10, L11) and the unused size of the internal RAMs L01 and L07 are compared. Perform (M01).

  If the unused size of the built-in RAMs L01 and L07 is larger, select a process of a size that fits in the unused size of the built-in RAM including the minimum steps necessary to return from the standby state from among a plurality of processes. Expand to built-in RAM. In this case, the optimal processing (L03 + L04 + L05 for L01 and L09 + L10 for L07) is expanded to the built-in RAMs L01 and L07 (M04, L06, L12), and processing in a standby state after D03 in FIG. 2 is performed.

  If the size of all processes to be expanded is larger, expansion to the internal RAMs L01 and L07 is not performed (M02), and power is supplied to the external ROMs L02 and L08 even in the conventional standby state, and after the standby state is restored. The operation is performed in the external ROMs L02 and L08 (M03).

  Next, the difference in processing between the case where only the minimum steps L03 and L09 necessary for return from the internal RAM and the interrupt processing are also on the internal RAM in the present embodiment will be described.

  FIG. 13 shows an example of return by remote control interrupt when only the minimum steps necessary for return from the built-in RAM B04 are developed in the fifth embodiment of the present invention.

  As shown in FIG. 13, the external interrupt N01 of the remote controller returns from the standby state, the power supply to the external ROM B06 is turned on by the processing on the internal RAM B04 (N02), and a jump is made to the processing of the external ROM B06 (N03). Since the internal RAM B04 has only the minimum steps necessary for returning from the standby state, the external ROM B06 decodes and checks the remote controller (N04).

  If the code of the remote control is a power source, the normal processing on the external ROM B06 is performed as it is (N05). However, if the remote control code is other than the power supply, the processing on the external ROMB06 is expanded again to the internal RAMB04 (N06), and after jumping to the processing on the internal RAMB04 (N07), the power supply to the external ROMB06 is turned off (N08). ) The process to the standby state must be performed on the built-in RAM B04 (N09). That is, when a remote control code that is not a return from the standby state is received, the power supply to the external ROM B06 is turned ON / OFF every time.

  If the decoding process of the remote controller is also on the built-in RAM B04, such a problem does not occur. FIG. 14 shows an example of return by remote control interrupt when the decoding process of the remote controller is also expanded to the built-in RAM B04 in addition to the minimum necessary steps in the fifth embodiment of the present invention.

  As shown in FIG. 14, the remote control returns from the standby state by an external interrupt O01, and the remote control is decoded and checked by processing on the built-in RAM B04 (O02).

  If the remote control code is a power supply, the power supply of the external ROMB06 is turned ON (O03), a jump is made to the processing of the external ROMB06 (O04), and normal processing is performed on the external ROMB06 (O05).

  However, if the code of the remote controller is other than the power source, the standby state is again entered (O07). Since the processing is executed on the built-in RAM B04, the clock can be stopped (O06) and a standby state can be entered (O07) without operating the power supply of the external ROM B06.

  The standby state control method according to the present invention has the effect of realizing low power consumption of the entire apparatus without the need to supply power to the external ROM in a standby state in a microcomputer that is equipped with a built-in RAM and operates by a program on an external ROM. In a device having a large-capacity ROM such as an AV device such as a television or a DVD recorder, it is useful as a device that enters a standby state and returns to normal processing due to an external factor such as a remote controller.

It is a system configuration figure in the standby state control method of a 1st embodiment of the present invention. It is a flowchart of the 1st Embodiment of this invention. It is a block diagram of ROM collection. It is a flowchart of the standby state control method of the 2nd Embodiment of this invention. It is an image figure which shows the 3rd Embodiment of this invention. It is a flowchart which shows the outline | summary of the 3rd Embodiment of this invention. It is an image figure which shows the 4th Embodiment of this invention. It is an image figure which shows the 4th Embodiment of this invention. It is a flowchart which shows the outline | summary of the 4th Embodiment of this invention. It is a flowchart which shows the outline | summary of the 4th Embodiment of this invention. It is an image figure which shows the 5th Embodiment of this invention. It is a flowchart which shows the outline | summary of the 5th Embodiment of this invention. It is a flowchart which shows the example of the return by remote control interruption at the time of expand | deploying only the minimum process required for the return from built-in RAM in the 5th Embodiment of this invention. It is a flowchart which shows the example of the return by remote control interruption when the decoding process of a remote control is also expand | deployed to built-in RAM in addition to the minimum required process in the 5th Embodiment of this invention. It is a system configuration diagram of a conventional example. It is a flowchart of a prior art example.

Explanation of symbols

B01 Microcomputer B02 CPU core B04 Microcomputer built-in RAM
B05 Function to change program execution address B06 External ROM
B07 power supply

Claims (5)

  A standby state control method for a system having a program on the external ROM, comprising a microcomputer having a built-in RAM, an external ROM, and a power source for driving the microcomputer and the external ROM, the standby state on the external ROM A step of developing a program for performing a process for entering and a process for returning from a standby state into the internal RAM, a step for changing a program execution address for entering the standby state from the external ROM to the internal RAM, and the external RAM Standby state control including a step of turning off the power to the ROM, a step of changing the program execution address when returning from the standby state from the external ROM to the built-in RAM, and a step of stopping the clock and entering the standby state Method.   A step in which the microcomputer in the standby state is restored and the clock stop is canceled by the processing of the internal RAM; a step of turning on the power to the external ROM; and a step of shifting from the internal RAM to the processing of the external ROM. The standby state control method according to claim 1.   Before expanding the processing of the external ROM in the internal RAM, the size of the internal RAM is compared with the size of the processing expanded in the internal RAM. When the size of the expansion processing is large, the external ROM is stored in the internal RAM. 2. The standby state control method according to claim 1, wherein the clock is stopped and released by the processing of the external ROM without performing the step of expanding the processing of the above.   Before expanding the processing of the external ROM in the internal RAM, the step of saving the addresses and values of the data distributed on the internal RAM in order to secure an area necessary for expanding the processing of the external ROM; 3. The standby state control according to claim 1, further comprising a step of restoring the data stored in the built-in RAM by setting the value of the saved data to an address before standby when returning from the standby state. Method.   Before expanding the processing of the external ROM in the internal RAM, the unused size of the internal RAM is compared with the size of the processing expanded in the internal RAM. When the size of the expansion processing is large, the process returns from the standby state. 3. The standby state control according to claim 1, further comprising: selecting from among a plurality of processes a process having a size that can be accommodated in an unused size of the built-in RAM, including a minimum necessary process, and expanding the process into the built-in RAM. Method.

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