JP2001084151A - Central processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a central processing unit capable of accelerating the preserving operation and restoring operation of a register in a central processing unit at the time of task switching. SOLUTION: This central processing unit 10 is provided with an arithmetic part 12 for operating each kind of arithmetic processing, an instruction fetch/ decode part 14 for controlling the arithmetic part 12, plural registers 16 for temporarily storing data necessary for the arithmetic processing of the arithmetic part 12 or the arithmetic result of the arithmetic part 12, and a register transferring device 18 connected with the register 16 and an outside bus 24 for controlling data transfer between the register 16 and the outside bus 24, and for successively executing the preservation or restoration of the value of the register 16 when any dead space is generated in the outside bus 24 and inside buses 20 and 22.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a real-time
The present invention relates to a central processing unit used in a computer system managed by an operating system. In particular, the present invention relates to a technique for accelerating the operation of saving and restoring registers in the central processing unit.

[0002]

2. Description of the Related Art In a control device such as an engine control device of an automobile or an industrial device, it is ensured that an input signal from the outside or a request from a program is processed immediately (in real time) or within a predetermined time. Need to end.
An operating system suitable for such real-time processing is a real-time operating system (OS).

Many control programs for control equipment and industrial equipment are configured in units of a plurality of programs called "tasks". The real-time OS manages tasks that are being executed on the central processing unit, suspends currently executing tasks according to changes in the state of control devices, etc.,
Start running another task. Thus, the real-time OS frequently switches the task to be executed. At the time of this switching, it is necessary to temporarily store the state of the central processing unit immediately before the switching of the task, that is, the value of the register in the central processing unit in the external storage device so that the execution of the interrupted task can be resumed later. is there. For this reason,
When the real-time OS executes task switching,
Transfer the value of the register immediately before switching to the external storage device,
Must be saved (register save operation). Furthermore, in order to execute the next task, the value of the register at the time of the interruption of the task must be read from the external storage device into the register (register return operation).

As described above, at the time of task switching, the operation of saving and restoring registers in the central processing unit is repeated by the number of registers. These operations are always inserted at the time of task switching. Therefore, there is a problem that the operation start of a new task is delayed. Also,
During the task switching, all the functions corresponding to the change in the state of the device are often stopped, and shortening the task switching time is a very important issue.

For this reason, there has been proposed a technique for shortening the task switching time with the support of improving the real-time OS and implementing the task switching function as hardware. For example, there is an example in which a dedicated storage device for register storage is provided in the central processing unit. In the case of this example, when the task switching request is generated, all the register values in the central processing unit are automatically and collectively stored in the register storage dedicated storage device. However, the number of tasks that can be handled is limited due to storage device capacity limitations. In addition, since values of registers that do not need to be stored are immediately stored in a lump, there are also problems such as a low use rate of the dedicated storage device and consumption of time required for storing and restoring unnecessary registers.

[0006]

SUMMARY OF THE INVENTION An object of the present invention is to provide a central processing unit capable of solving the above-mentioned problems and speeding up the operation of saving and restoring registers in the central processing unit at the time of task switching. And

[0007]

Means for Solving the Problems In order to solve the above problems, a feature of the present invention is to provide an arithmetic unit for performing various arithmetic processes,
An instruction fetch / decode unit that fetches / decodes an instruction and controls an operation unit, and a plurality of storage circuits (registers) that temporarily store data necessary for operation processing of the operation unit and operation results of the operation unit. A register transfer device connected to the temporary storage unit (register unit), the register unit and the external bus, and controlling data transfer between the register unit and the external bus, the internal bus between the external bus and the arithmetic unit and the register unit. Is a central processing unit having a register transfer unit for sequentially executing data transfer when a vacancy occurs.

According to a feature of the present invention, the processing executed by the central processing unit is to store the value of the register unit indicating the state of the task to be interrupted and to restore the value of the register unit indicating the state of another task to be started. And apparently executed in parallel. Therefore, the time required for the task switching process is reduced, and the speed of the central processing unit is increased.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a central processing unit according to an embodiment of the present invention. In FIG. 1, a central processing unit according to this embodiment is a central processing unit 10 managed by a real-time OS,
U (Arithmetic and Logic Unit) and the like, which performs various arithmetic and logical operations, an instruction fetch / decode unit 14 for fetching instructions and decoding the fetched instructions, and read data And a plurality of registers (register units) 16 for temporarily storing the operation results of the operation unit 12, and a register transfer device 18 for controlling data transfer between the registers 16 and the external storage device 40.
It is composed of Operation unit 12 and register unit 1
6, an internal bus (referred to as a “first internal bus”) 20 for transferring data from the arithmetic unit 12 to the register unit 16;
And an internal bus (referred to as a “second internal bus”) 22 for transferring data from the register unit 16 to the operation unit 12. Normally, the second internal bus 22 is provided with two channels for efficient data reading. On the other hand, the register unit 16 and the external bus 24 include an internal bus (referred to as a “storage channel”) 26 for transferring data from the register unit 16 to the external bus 24 and an internal bus 26 for transferring data from the external bus 24 to the register unit 16. They are connected by a bus (called a “return channel”). The register unit 16 is connected to one of the first internal bus 20 and the return channel 28 by a switching circuit (referred to as a “first switching circuit”) 30, and the switching circuit (“the second switching circuit”). 32) is connected to either the second internal bus 22 or the storage channel 26.

Here, the register transfer unit 18 includes a transfer control unit 3 for controlling data transfer of the register unit 16.
8 is built-in. The transfer control unit 38 receives the bus use information c from the instruction fetch / decode unit 14, and sends a control signal d to the first switching circuit 30 based on the information c.
A control signal e is output to the second switching circuit 32 to control the switching operation thereof. Then, the register unit 16 is connected to the return channel 28 or the save channel 26 to execute data transfer between the register 16 and the external storage device 40. The transfer control unit 38 controls the transfer flag register 3 that specifies the register 16 in which the data transfer is performed.
4 and a transfer address register 36 for designating the storage destination or the return source position of the register 16. The transfer flag register 34 includes a register “ch1” corresponding to the save channel 26 and a register “ch2” corresponding to the return channel 28. The bit widths of the registers “ch1” and “ch2” constituting the register 34 match the number of the registers 16, and their bit numbers correspond to the register numbers. Therefore, the register 16 to be saved or restored can be variously selected as needed. Whether or not data transfer is performed is indicated by the state of each bit. For example, a bit corresponding to the register 16 in which data transfer is performed may be set to “1”, and the other bits may be set to “0”. In the transfer address register 36, the position of the data storage destination or the position of the return source of the register 16 in which the data transfer is performed is designated. In this embodiment, the value of the register 16 is stored in the external storage device 40 connected to the external bus 24. Therefore,
In the transfer address register 36, the address of the storage destination or the return source of the register 16 in the data storage area in the external storage device 40 is specified. Normally, the values of the transfer flag register 34 and the transfer address register 36 are set by the real time OS.

Next, the operation of the register transfer device 18 of the central processing unit 10 according to the embodiment of the present invention will be described. First, a basic operation of the central processing unit 10 will be briefly described. Usually, when the system is powered on or when the system is reset, a desired instruction a is fetched by the instruction fetch / decode unit 14 from outside the central processing unit 10. And the instruction a
Is decoded by the instruction fetch / decode unit 14, generates a control signal corresponding to the instruction, and outputs the control signal to the arithmetic unit 12. The calculation unit 12 performs various calculations based on the control signal b. At the time of the operation, necessary data is stored in the register 16
And the result of the operation is stored in the register 16. Similarly, the central processing unit 10 sequentially executes predetermined instructions.

Next, the register storing operation of the register transfer device 18 will be described. FIG. 2 shows a register transfer device 1
8 is a diagram for explaining a register saving operation of FIG. FIG.
9 is a flowchart showing a processing procedure of a register saving operation of the register transfer device 18. The central processing unit 1
The number of the registers 16 in 0 is 16, and the transfer flag register 34 and the transfer address register 36 are specified by the OS. As shown in FIG. 3, when the system is powered on or the system is reset, the register transfer device 18 determines a transfer flag register (ch2) 34 corresponding to the storage channel 26 in advance. Bit search is started in the set direction (step S1).
01). When the system is in operation, a bit search is constantly performed, and when a set bit is found, the register transfer device 18 enters a data transfer standby state of the register 16 corresponding to the set bit. In FIG. 2, for example, the bit search is performed from the rightmost bit (bit “0”), which is the least significant bit of the transfer flag register (ch2) 34, to the most significant bit (most signifi).
When the operation is performed toward the leftmost bit (bit “15”), which is a cant bit, bit 2 is found first (step S102: YES). The register transfer device 18 obtains the bus use information c from the instruction fetch / decode circuit 14, and always acquires the first and second internal buses 20, 22,
The usage status of the external bus 24 is monitored. And the second
Is available in the internal bus 22 (step S103YE).
S), if the external bus 24 becomes free (step S104 YES), the register transfer device 18 outputs the control signal e to the second switching circuit 32 and connects the storage channel 26 to the register unit 16 (step S104). S1
05). Then, the register transfer device 18 selects the register (R2) 16 corresponding to the set bit “2” of the transfer flag register 34 (Step S106). The register transfer device 18 selects the selected register (R2) 1
6 through the storage channel 26 to the external storage device 40.
Transfer to The value of the selected register (R2) is stored in the address of the external storage device 40 indicated in the transfer address register 36 (step S107). When the data transfer of the register (R2) 16 is completed, the register transfer device 18 sends the control signal e to the second switching circuit 32.
And outputs the register unit 16 to the second internal bus 22.
Is connected again (step S108). Finally, the bit “2” of the transfer flag register 34 is reset to “0”. Further, the value of the transfer address register 36 is automatically updated so that the transfer address register 36 indicates the storage destination of the register 16 where the data transfer is performed next. For example, every time data transfer is completed, the transfer address register 3
6 may be automatically moved up or down. As shown in FIG. 2, selection between carry-up and carry-down is performed by setting the transfer address register 36 to one of a plurality of inputs.
A multiplexer 42 for selecting one may be provided, and the selection may be made according to the channel number.

When all the bits of the transfer flag register 34 are reset to "0", the register saving operation is completed, and the register transfer device 18 executes a register return operation.

Next, the register return operation of the register transfer device 18 will be described. FIG. 4 shows the register transfer device 1
8 is a diagram for explaining a register return operation of FIG. FIG.
9 is a flowchart showing a processing procedure of a register return operation of the register transfer device 18. As shown in FIG. 5, when the system is powered on or the system is reset, the register transfer device 18 transfers the transfer flag register (ch1) 34 corresponding to the return channel 28.
, A bit search is started in a predetermined direction (step S201). When the system is in operation, a bit search is constantly performed, and when a set bit is found, the register transfer device 18 enters a data transfer standby state of the register 16 corresponding to the set bit. In FIG. 4, for example, when a bit search is performed from the most significant bit (bit “15”) to the least significant bit (bit “0”) of transfer flag register (ch2) 34, bit 15 is found first. (Step S2
02YES). The register transfer unit 18 receives the instruction fetch /
The bus usage information c is obtained from the decoding circuit 14, and
The usage status of the first and second internal buses 20, 22 and the external bus 24 is monitored. Then, the first internal bus 20
Is available (step S203 YES), and if an external bus 24 is available (step S204YE).
S), the register transfer device 18 uses the first switching circuit 30
The control signal d is output to the register unit 16 and the return channel 28 is connected to the register unit 16 (step S205). Then, the register transfer device 18 stores the register (R1) corresponding to the set bit “15” of the transfer flag register 34.
5) 16 is selected (step S206). The register transfer device 18 transfers the value of the selected register (R15) 16 from the external storage device 40 via the return channel 28. The value of the selected register (R15) is stored in the address of the external storage device 40 indicated in the transfer address register 36 (Step S207). When the data transfer of the register (R15) 16 is completed, the register transfer device 18 outputs a control signal d to the first switching circuit 30, and connects the register unit 16 to the first internal bus 20 again (step S208). Finally, the bit “15” of the transfer flag register 34 is reset to “0”. Further, the value of the transfer address register 36 is automatically updated so that the transfer address register 36 indicates the storage destination of the register 16 where the data transfer is performed next.

When all the bits of the transfer flag register 34 are reset to "0", the register return operation ends, and the task switching has been executed.

Next, FIG. 6 shows an example for explaining the effect of the register transfer device 18 of the central processing unit 10 according to the embodiment of the present invention. FIG. 6 is a diagram showing a difference between the task switching time according to the related art and the task switching time according to the present invention. The example illustrated in FIG. 6 illustrates a situation in which task A is suspended and task B is resumed. The horizontal axis indicates the elapsed time from the start of the task switching process.

First, in the task switching according to the prior art of the prior art, when the task switching process starts, information on the task A to be interrupted and the usage status of various resources are checked ("system management"). Then, the operation of saving the value of the register of the task A to be interrupted is executed (“save the register of the task A”). Next, the task B to be executed next is selected from the task execution priority ("scheduling"). After the task B is selected, “system management” is performed again, and then, the operation of restoring the value of the register of the task B is performed (“restoration of the register of the task B”). Finally, after “system management” is performed, the task switching process ends.

On the other hand, in the subsequent task switching according to the present invention, the register transfer operation of the register A of the task A and the operation of restoring the register of the task B are executed. That is, in the task switching according to the present invention, the register saving operation and the register restoring operation are apparently executed in parallel with other processes executed by the central processing unit 10, so that the task switching time is shortened as a whole. ("Reduce task switching time"). As shown in FIG. 6, when the task switching process starts, the OS sets the values of the transfer flag register 34 and the transfer address register 36 for saving the register of the task A. Then, the central processing unit 10 sequentially executes “system management” and “scheduling” as in the related art. At the same time, the register transfer device 18 monitors the bus use status as described above, and executes the register saving operation of the task A independently using the period in which the bus is free. When the next task B to be executed is selected by “scheduling”, the central processing unit 10 immediately sets a value for the return operation of the task B in the transfer flag register 34 and the transfer address register 36, respectively. The register transfer device 18 executes the return operation of the task B independently based on the values of the transfer flag register 34 and the transfer address register 36. Then, when the “system management” by the central processing unit 10 and the “task B register return operation” by the register transfer unit 18 are completed, the execution of the task B is resumed.

[0019]

According to the present invention, a central processing unit capable of reducing the time required for task switching can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of a central processing unit according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining a register storing operation of the register transfer device according to the embodiment of the present invention.

FIG. 3 is a flowchart showing a processing procedure of a register saving operation of the register transfer device according to the embodiment of the present invention.

FIG. 4 is a diagram for explaining a register return operation of the register transfer device according to the embodiment of the present invention;

FIG. 5 is a flowchart showing a processing procedure of a register saving operation of the register transfer device according to the embodiment of the present invention.

FIG. 6 is a diagram showing a difference between a task switching time according to the related art and a task switching time according to the present invention.

[Explanation of symbols]

 Reference Signs List 10 central processing unit 12 arithmetic unit 14 instruction fetch / decode unit 16 register unit 18 register transfer device 20 first internal bus 22 second internal bus 24 external bus 26 storage channel 28 return channel 30 first switching circuit 32 Second switching circuit 34 Transfer flag register 36 Transfer address register 38 Transfer control unit 40 External storage device 42 Multiplexer

Claims (6)

[Claims] An arithmetic unit for performing various arithmetic processing; an instruction fetch / decode unit for fetching / decoding an instruction and controlling the arithmetic unit; A temporary storage unit composed of a plurality of storage circuits for temporarily storing operation results; a register transfer device connected to the temporary storage unit and an external bus, for controlling data transfer between the temporary storage unit and the external bus A central processing unit, comprising: a register transfer unit that sequentially executes the data transfer when an empty space occurs in the external bus and the internal bus between the arithmetic unit and the temporary storage unit. 2. The method according to claim 1, wherein the register transfer unit interrupts a process currently being executed by the central processing unit and, when starting another process, stores the value of the temporary storage unit indicating a state of the interrupted process. 2. The central processing unit according to claim 1, wherein a value stored in the temporary storage unit, which indicates a state of a process to be started, is externally restored after being stored outside. 3. The first transfer unit for transferring data from the temporary storage unit to the external bus and storing a value in the temporary storage unit, and transferring the data from the external bus to the temporary storage unit. And a second channel for transferring the value of the temporary storage unit and restoring the value of the temporary storage unit, wherein saving and restoring of the temporary storage unit are not performed simultaneously.
A central processing unit according to item 1. 4. The register transfer unit specifies a first specification unit that specifies at least one of the plurality of storage circuits to be stored or restored, and a storage destination or a restoration source of the specified storage circuit. The central processing unit according to claim 3, further comprising a second designation unit. 5. The central processing unit according to claim 4, wherein an external storage device is connected to the external bus, and the storage destination or the restoration source is a data storage area in the external storage device. 6. The register transfer section disconnects the temporary storage section from the arithmetic section when storing the temporary storage section, connects the temporary storage section to the first channel, and stores the temporary storage section when returning the temporary storage section. 4. The central processing unit according to claim 3, wherein the central processing unit is separated from the arithmetic unit and connected to the second channel.