JP3767529B2 - Microprocessor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a microprocessor, and more particularly to a microprocessor that enables task switching with low temporal overhead, for example. In particular, the present invention relates to a microprocessor suitable for a processor that requires various different processing such as demodulation processing, error correction processing, and protocol processing, such as software radio technology.
[0002]
[Prior art]
In recent years, the advancement of electronic devices has progressed, and further advancement and efficient processing have been demanded for microprocessors incorporated in electronic devices. That is, there is a need for a high-speed microprocessor that executes a large amount of programs.
[0003]
In general, an embedded microprocessor is often required to perform real-time processing. In a complicated program, a timing-constrained part can be executed reliably and within a predetermined time, and a program can be executed. It is strongly desired to predict whether the processing time will be in time when the change is made.
[0004]
On the other hand, with recent advances in semiconductor technology, it is possible to use more circuits in microprocessors than before, and if advanced and efficient processing requirements are met, In many cases, the increase in the circuit amount is allowed.
[0005]
In addition, because of the advancement of semiconductor technology, the integration density of circuits has been improved, so it is possible to integrate memory, etc., which was a separate chip from the microprocessor, on the same chip, which limits the number of pins on the package. The bus width between the microprocessor and the memory, which has been limited by receiving, can be greatly increased. Therefore, the restrictions on the increase in bus width and the number of buses are greatly relaxed.
[0006]
By the way, when executing real-time processing in a microprocessor, it is possible to receive an irregular or periodic input of an interrupt control signal from an external peripheral circuit and execute a program (so-called interrupt service) corresponding to various interrupts.
[0007]
At this time, since there is no continuity between the program being executed and the interrupt service, the internal state of the microprocessor (for example, the pipeline flip-flop used in the arithmetic circuit) is saved or executed. The interrupt service does not change the operation result of the program that has been executed so far, depending on whether the program is stalled.
[0008]
Here, an internal configuration of a conventional microprocessor will be described with reference to FIG.
[0009]
The program counter 1 is a register for storing the address of an instruction (task) to be executed next, and supplies the stored address of the instruction to be executed next to the instruction memory 2. The instruction memory 2 supplies the instruction read out based on the address supplied from the program counter 1 to the arithmetic circuit 3. The instruction cache 7 is a buffer for performing pseudo-high-speed data access using access locality when the data input / output speed of the instruction memory 2 is slower than that of the arithmetic circuit 3. Memory.
[0010]
This microprocessor is assumed to be composed of a 5-stage pipelined RISC (Reduced Instruction Set Computer) processor of stages 11 to 15.
[0011]
The stage 11 reads an instruction (task) stored in the instruction memory 2 (IF: Instruction Fetch) and stores it in the storage element 20. The stage 12 reads out the instruction stored in the storage element 20 and the data stored in the register file 4, decodes (ID: Instruction Decode), and stores it in the storage element 21.
[0012]
The stage 13 reads and executes an instruction stored in the storage element 21 (EX: Execution), and stores data calculated by the instruction in the storage element 22.
[0013]
The stage 14 reads out data stored in the storage element 22 and stores it in the storage element 23. The stage 14 also causes the data relating to the internal state in the arithmetic circuit 3 and the contents of the register file 4 to be written to the data memory 5 (MEM: Memory access), and also reads the data written in the data memory 5 to read out the arithmetic circuit 3 And the register file 4 is restored. The stage 15 reads the data stored in the storage element 23 and writes it back to the register file 4 (WB: Write Back). Between the data memory 5 and the stage 14, there is generally a data cache 6 for performing pseudo high-speed data access.
[0014]
FIG. 2 is a diagram for explaining the task switching timing operation by the interrupt service in the microprocessor shown in FIG.
[0015]
As shown in the figure, at time T 1, the stage 11 reads out the task 1 stored in the instruction memory 2 and stores it in the storage element 20. At time T2, the stage 12 reads the task 1 stored in the storage element 20, decodes it, and stores it in the storage element 21. At time T3, the stage 13 reads the task 1 stored in the storage element 21, executes it, and stores the calculation result in the storage element 22. At time T <b> 4, the stage 14 reads out data stored in the storage element 22 and stores it in the storage element 23. At time T5, the stage 15 reads the data stored in the storage element 23 and writes it back to the register file 4.
[0016]
Thus, the signal input to the stage (for example, the stage 11) is supplied to the next stage (in this case, the stage 12) after the clock time T has elapsed. Thereafter, even if there is a next input in this stage (stage 11), this signal is supplied to the next stage (stage 12) after the clock time T has elapsed. Therefore, the next stage (stage 12) can supply the current signal to the next stage (in this case, stage 13) before being affected by the input of the previous stage (stage 11). .
[0017]
When a task switching control signal (interrupt service) is generated at time T7, the microprocessor counters the program counter 1 to supply the instruction memory 2 with the address of the next instruction (task 2) to be executed at time T8. Control address switching. Thereafter, since pipeline installation is generated in the arithmetic circuit 3, it waits until a register save instruction is generated.
[0018]
At time T12, when data is written back to the register file 4 by the stage 15 (when all tasks 1 are discharged), a register save instruction is generated, and the stage 14 stores the data in the arithmetic circuit 3 in the data memory 5. Data relating to the internal state and the contents of the register file 4 are saved.
[0019]
At time T15 when the data saving of the stage 11 ends, the task 2 stored in the instruction memory 2 is read, and the execution of the task 2 is started. Thereafter, the same operation as the above-described task 1 is repeatedly executed.
[0020]
At time T52 when execution of task 2 in stage 11 ends, a register return instruction is generated, and the internal state of arithmetic circuit 3 and the contents of register file 4 in the execution of task 1 are restored from data memory 5. At time T55 when the data restoration of the stage 11 ends, the microprocessor controls the address return of the program counter 1 so that the instruction memory 2 is supplied with the address of the instruction (task 1) to be executed next. Thereafter, the arithmetic circuit 3 waits until pipeline installation is generated and the data restoration of the stage 15 is completed. When the data restoration of stage 15 is completed at time T59, the execution of task 1 is resumed and the above-described operation is repeated.
[0021]
In this way, the internal state of the arithmetic circuit 3 being executed and the contents of the register file 4 are saved before accepting the interrupt service so that the contents of the register file 4 are not destroyed by the execution of the interrupt service program. When returning from the interrupt service, by restoring the saved internal state of the arithmetic circuit 3 and the contents of the register file 4, the operation result of the program executed before by the interrupt service is changed. Is prevented.
[0022]
Further, as shown in FIG. 3, two register files 4-1 and 4-2 are provided, and the task can be switched instantaneously by switching the register file when executing the interrupt service. There is also a processor. Note that portions corresponding to those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted as appropriate.
[0023]
In the configuration of FIG. 3, when an interrupt service is received in a state where a task stored in one register file 4-1 is being executed, the task stored in the other register file 4-2 is instantaneously stored. Since the switches 31 and 32 are switched so as to select the register file 4-2 from the register file 4-1 so that they can be executed, the overhead for saving data does not occur.
[0024]
FIG. 4 is a diagram for explaining the task switching timing operation by the interrupt service in the microprocessor shown in FIG.
[0025]
As shown in the figure, when a task switching control signal (interrupt service) is generated at time T7, the microprocessor assigns the address of the next instruction (task 2) to be executed at time T8 to the instruction memory 2. To control the address switching of the program counter 1. Thereafter, pipeline installation occurs in the arithmetic circuit 3, and at time T12, when data is written back to the register file 4-1 by the stage 15 (when all tasks are discharged), the switches 31 and 32 are simultaneously turned on. Switching is made so that the register file 4-2 is selected from the register file 4-1, and the task 2 stored in the instruction memory 2 is read and executed.
[0026]
Thus, by providing two systems of register files, task 1 and task 2 can be switched instantaneously.
[0027]
[Problems to be solved by the invention]
However, in the example of FIGS. 1 and 2, dozens of clocks must be used for saving the internal state of the register file and installing the pipeline, and each time an interrupt service occurs, a relatively large time overhead is generated. There was a problem that occurred.
[0028]
In the case of the example of FIGS. 3 and 4, when there are multiple interrupt services more than the register file group prepared in advance (two in the case of FIG. 3), the register is also registered as in the case of the example of FIG. There has been a problem that a time overhead for saving the internal state of the file 4 and pipeline installation occurs.
[0029]
Furthermore, providing a large number of register files that must operate at the highest speed in the memory hierarchy in the microprocessor means that the circuit scale increases and the wiring increases, and the clock of the microprocessor is increased. There was a problem that hindered speed improvement.
[0030]
The present invention has been made in view of such a situation, and enables task switching with little temporal overhead and realizes almost unlimited interrupt multiplexing without providing a large number of register files. It is something that can be done.
[0031]
[Means for Solving the Problems]
  The microprocessor according to the present invention includes a plurality of stages, and by sequentially executing a plurality of instructions while shifting the plurality of instructions in the plurality of stages, at least one system of arithmetic means for simultaneously calculating data, and arithmetic meansCorresponding to the multiple tasks in the multiple stages that make upTo remember, every stageIn association with 1 For the systemStorage means provided in at least two systems;When the first task is executed, it is assumed that each state in a plurality of stages is stored.Of the storage means provided in at least two systems, for each stageAny storage meansDuring execution of the first task using the control means for controlling to select and the storage means selected by the control means,Storage means not used for execution of first taskOn the second task held inStates in multiple stagesEvacuation means for evacuating,During the execution of the first task using the storage means selected by the control means, it is saved in the saving meansAbout the third taskStates in multiple stagesTheStorage means not used for execution of first taskAnd a restoring means for restoring the data.
[0032]
  When a task switching control signal is generated in the control means,Not used to perform current taskStorage meansAs a memory for each state of multiple stages of a new taskCan be controlled to chooseThe timing of selecting the storage means can be controlled to be different for each storage means provided in association with each stage.The
[0033]
  When the control means receives an interrupt control signal from the outside,Not used to perform current taskStorage meansAs a memory for each state of multiple stages of a new taskCan be controlled to chooseThe timing of selecting the storage means can be controlled to be different for each storage means provided in association with each stage.The
[0034]
  When an interrupt control signal is received while data is being saved by the saving means, the control means holds the interrupt control signal until the saving of data is completed by the saving means, and when saving of the data is completed ,Not used to perform current taskStorage meansAs a memory for each state of multiple stages of a new taskCan be controlled to chooseThe timing of selecting the storage means can be controlled to be different for each storage means provided in association with each stage.The
[0035]
  When receiving the interrupt control signal in the middle of restoring the data by the restoration means, the control means stops the restoration of the data,Not used to perform current taskStorage meansAs a memory for each state of multiple stages of a new taskCan be controlled to chooseThe timing of selecting the storage means can be controlled to be different for each storage means provided in association with each stage.The
[0036]
  The storage means stores the register file.furtherIt can be included.
  Also,The storage means may further include a program counter.
[0037]
There are a plurality of retracting means, and they can be connected to each other.
[0038]
  Memory existing outside the microprocessor for savingas well asMemory that is connected to one system of computing means and the saving means exists outside the microprocessorofIt can be operated as a cache.
  The saving means can be connected to a memory existing outside the microprocessor and one system of calculating means, and the saving means can be operated as a substitute for the memory existing outside the microprocessor.
[0039]
  In the microprocessor according to the present invention, a plurality of instructions are shifted and sequentially executed in a plurality of stages, thereby being simultaneously operated in parallel.Matching the status of multiple stages to multiple tasksTo remember, every stageIn association with 1 For the systemWhile any one of the storage paths provided in at least two systems is selected and the first task is executed using the selected storage paths,Not used to execute the first taskRegarding the second task held in the memory pathStates in multiple stagesIs saved in the memory and the third task saved in the memory isStates in multiple stagesBut,Not used to execute the first taskRestored to the storage path.
[0040]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0041]
FIG. 5 is a block diagram showing an internal configuration example of a microprocessor to which the present invention is applied. In addition, the same code | symbol is attached | subjected to the part corresponding to the past, and the description is abbreviate | omitted suitably. In the present invention, the program counter 1, the register file 4, and the storage elements 20 to 23 in the arithmetic circuit 3 are each constituted by two systems, but of course, it may be constituted by two or more plural systems. . On the other hand, the stages 11 to 15 are composed of only one system. Strictly speaking, the instruction memory 2 and the data memory 5 are not included in the microprocessor, and the other part is referred to as a microprocessor core.
[0042]
The task switching control unit 41 controls the switches 51 to 70 in the microprocessor to be switched by a task switching control signal generated every predetermined time, or to be switched by input of an external interrupt control signal. . In the initial state, the task switching control unit 41 controls the switch 52 so that the program counter 1-1 is selected from the program counters 1-1 and 1-2, and the two pipelines in the arithmetic circuit 3 are controlled. Among them, the switches 57 to 60 are controlled so as to select the memory elements 20-1, 21-1, 22-1 and 23-1, respectively, and the register file 4-1 of the register files 4-1 and 4-2 is selected. The switches 68 and 69 are respectively controlled so as to select.
[0043]
The switch 51 is a switch (selection device) for reading for saving, and the address supplied from the program counter 1-1 or 1-2 is transferred to the first saving memory 42 under the control of the task switching control unit 41. Supply. The switch 52 supplies the instruction memory 2 with the address supplied from the program counter 1-1 or 1-2 under the control of the task switching control unit 41.
[0044]
The instruction memory 2 supplies an instruction (task) read based on the address supplied from the program counter 1-1 or 1-2 via the switch 52 to the arithmetic circuit 3.
[0045]
The arithmetic circuit 3 is composed of a 5-stage pipelined RISC processor of stages 11 to 15 and two storage elements are provided, so that the arithmetic circuit 3 has two pipelines. In the embodiment of the present invention, an example in which the pipeline has five stages is shown, but the number of stages is arbitrary, and may be larger or smaller.
[0046]
The stage 11 reads an instruction (task) stored in the instruction memory 2 and stores it in the storage element 20-1 or 20-2. The stage 12 reads the instruction stored in the storage element 20-1 or 20-2 via the switch 57, and reads the data stored in the register file 4-1 or 4-2 via the switch 68 or 69. Are read out, decoded, and stored in the storage element 21-1 or 21-2.
[0047]
The stage 13 reads the instruction stored in the storage element 21-1 or 21-2 via the switch 58, executes the read instruction, and stores the data calculated by the instruction in the storage element 22-1 or 22- 2 is memorized.
[0048]
The stage 14 reads the data stored in the storage element 22-1 or 22-2 through the switch 59 and stores it in the storage element 23-1 or 23-2. The stage 14 also causes the data obtained by the execution of the task to be written into the data memory 5, reads out the data written in the data memory 5, and stores it in the storage element 23-1 or 23-2.
[0049]
The stage 15 reads the data stored in the storage element 23-1 or 23-2 via the switch 60 and writes it back to the register file 4-1 or 4-2.
[0050]
The switch 53 is a switch (selection device) for reading for saving, and commands (tasks) read from the storage element 20-1 or 20-2 under the control of the task switching control unit 41 are stored in the first saving memory. 42. The switch 54 is a switch for reading for saving, and supplies data read from the storage element 21-1 or 21-2 to the first saving memory 42 under the control of the task switching control unit 41. The switch 55 is a switch for reading for saving, and supplies data read from the storage element 22-1 or 22-2 to the first saving memory 42 under the control of the task switching control unit 41. The switch 56 is a switch for saving reading, and supplies data read from the storage element 23-1 or 23-2 to the first saving memory 42 under the control of the task switching control unit 41.
[0051]
The switch 61 is a switch for restoring writing, and supplies data (address) supplied from the first save memory 42 to the program counter 1-1 or 1-2. The switch 62 is a switch for restoration writing, and supplies data (command) supplied from the first save memory 42 to the storage element 20-1 or 20-2. The switch 63 is a switch for restoration writing, and supplies data supplied from the first save memory 42 to the storage element 21-1 or 21-2. The switch 64 is a switch for writing for restoration, and supplies data supplied from the first save memory 42 to the storage element 22-1 or 22-2. The switch 65 is a switch for restoration writing, and supplies data supplied from the first save memory 42 to the storage element 23-1 or 23-2.
[0052]
The switch 66 is a switch for writing operation data, and supplies data written back from the stage 15 to the register file 4-1 or 4-2 under the control of the task switching control unit 41.
[0053]
The switch 67 is a switch for writing for restoration, and supplies data supplied from the first save memory 42 to the register file 4-1 or 4-2 under the control of the task switching control unit 41.
[0054]
The switches 68 and 69 are switches for reading operation data, and supply data read from the register file 4-1 or 4-2 to the stage 12 under the control of the task switching control unit 41.
[0055]
The switch 70 is a switch for saving reading, and supplies data read from the register file 4-1 or 4-2 to the first saving memory 42 under the control of the task switching control unit 41.
[0056]
The first save memory 42 includes save data from the program counter 1-1 or 1-2 supplied via the switch 51, save data from the arithmetic circuit 3 supplied via the switches 53 to 56, and The save data from the register file 4-1 or 4-2 supplied via the switch 70 is written. The written save data is read at the time of restoration. In addition to the first save memory 42, it is more preferable that the second save memory 43 exists. For example, the first save memory 42 is a memory having a small capacity (capacity) but a fast transfer rate (High Access bandwidth), and the second save memory 43 has a large capacity but a slow transfer rate (Low Access bandwidth). ) In this case, multi-stage processing such as saving data that does not need to be processed immediately in the second save memory 43 becomes possible.
[0057]
In addition, the instruction memory 2 existing outside the microprocessor is connected to the first save memory 42 and the second save memory 43, and the input / output thereof is bidirectionally connected to the stage 11, so that the first save is performed. The memory 42 or the second save memory 43 can also be used as the instruction cache 7 (FIG. 1). Similarly, the data memory 5 existing outside the microprocessor is connected to the first save memory 42 and the second save memory 43, and the input / output thereof is bidirectionally connected to the stage 14, so that the first The save memory 42 or the second save memory 43 can also be used as the data cache 6 (FIG. 1). As described above, the mounting efficiency (area efficiency) can be improved by using both the save memory and the cache.
[0058]
Further, by connecting the instruction memory 2 to the first save memory 42 and the second save memory 43, the save memory can be used as the instruction memory 2. When this is applied to the above-described example, the first save memory 42 having a small capacity but a fast transfer speed is substituted for the instruction cache 7, and the second save memory 43 having a large capacity but a slow transfer speed is designated as the instruction memory 2. It is also possible to substitute. With such a configuration, mounting efficiency (area efficiency) can also be improved.
[0059]
The second save memory 43 may be inside the microprocessor or outside.
[0060]
Note that the save data is multiplexed and sequentially written, or simultaneously written in parallel. Similarly, the data to be restored is multiplexed and read, or is read simultaneously in parallel.
[0061]
FIG. 6 is a diagram for explaining the task switching timing operation by the interrupt service in the microprocessor shown in FIG. Here, it is assumed that tasks 1, 2, and 3 are scheduled to be executed in this order, and among these tasks 1 to 3, task 3 has previously been interrupted during task execution. It is assumed that there is saved data in the first save memory 42, and there is no saved data in the first save memory 42, and task 2 restores the saved data at the start of execution of task 2. Is explained as not necessary. Note that the register file currently used for the calculation is appropriately referred to as “front”, and the register file not currently used for the calculation is appropriately referred to as “back”.
[0062]
As shown in the figure, when task 1 is executed in the initial state and a task switching control signal is generated at time T7, task switching control unit 41 starts from program counter 1-1 at time T8. The switch 52 is controlled to select the program counter 1-2. At time T9, the task switching control unit 41 controls the switches 68 and 69 to switch from the register file 4-1 to the path of the register file 4-2. As a result, the register file 4-1 is switched from “front” to “back”, the register file 4-2 is switched from “back” to “front”, and the task 2 stored in the instruction memory 2 is executed. Be started. Thereafter, the same operation as task 1 is repeatedly executed.
[0063]
That is, the task switching control unit 41 switches the switch 57 to select the storage element 20-2 at time T8, switches the switch 58 to select the storage element 21-2 at time T9, and at time T10. The switch 59 is switched so as to select the storage element 22-2, and the switch 60 is switched so as to select the storage element 23-2 at time T11. As described above, the task 1 is switched to the task 2 for each stage.
[0064]
At time T12, when the data is written back to the register file 4-1 by the stage 15 (when all tasks 1 are discharged), the task switching control unit 41 writes the data back to the register file 4-2. Thus, the switch 66 is switched. As a result, the register file 4-1 becomes “back” (standby state), so that the time is used to store the contents of the register file 4-1 and the operation circuit in the execution of the task 1. 3 is saved, and the task to be executed next is restored.
[0065]
In this case, the task 3 is scheduled to be executed next to the task 2, and therefore the data of the task 1 is saved and the data of the task 3 is restored during the execution of the task 2.
[0066]
Specifically, at time T13, the task switching control unit 41 causes the switch 51, the switches 53 to 56, and the switch 70 to be “back”, the program counter 1-1, the storage element 20-1, 21-1, 21-1 and 23-1 and the register file 4-1 are switched to select the program counter 1-1 and the memory elements 20-1, 21-1, and 2-1 of the arithmetic circuit 3. And 23-1, and the data stored in the register file 4-1, are saved in the first save memory 42. Then, when the data saving is completed at time T32, the data of the task 3 saved in the first saving memory 42 at time T34 is stored in the program counter 1-1 and the arithmetic circuit 3 that become “back”. The data is written and restored in the storage elements 20-1, 21-1, 22-1 and 23-1, and the register file 4-1.
[0067]
As described above, during the execution of the task 2, the “counter” program counter 1-1, the storage elements 20-1, 21-1, 22-1 and 23-1 of the arithmetic circuit 3, and the register file 4-1. Since the data at the time of the previous switching of task 3 is restored, the switching from task 2 to task 3 is instantaneously performed in the same manner as switching from task 1 to task 2.
[0068]
In addition, during the execution of task 3, it is stored in the register file 4-2 that is the "back", the program counter 1-2, and the storage elements 20-2, 21-2, 22-2, and 23-2 of the arithmetic circuit 3. The task switching data (task switching) can be executed without time overhead by saving the data of the task 2 being saved in the first saving memory 42 and restoring the task 1 to be executed next.
[0069]
Furthermore, a plurality of tasks can be freely switched and executed according to the storage capacity of the first save memory 42.
[0070]
In the above description, it has been described that the task switching control signal is given at an appropriate timing. However, for example, by generating the task switching control signal by a self-running counter, it is possible to equally give execution time to each task it can.
[0071]
Also, a preloadable down counter is provided, and a task switching control signal is generated at the timing when the value of the down counter becomes 0, and the preload value is loaded into the down counter when the task switching control signal is generated. With this configuration, the task switching interval can be made variable simply by changing the preload value set in advance.
[0072]
Further, by providing a plurality of registers for holding preload values to be loaded into the down counter and setting in what order these registers are loaded by a program, flexible task switching can be realized.
[0073]
In the above description, the case where the task switch can be predicted in advance has been described. However, even in the external interrupt service, task switching can be executed without time overhead.
[0074]
Although the case where the first save memory 42 is provided in the microprocessor has been described as an example, the present invention is not limited to this. For example, a cache memory (not shown) may be used as the save memory.
[0075]
FIG. 7 is a diagram for explaining the task switching timing operation by the external interrupt service. In the case of this example, since there is an interrupt service at a timing when data saving and data restoration are not executed, it can be handled in the same way as normal task switching.
[0076]
As shown in the figure, when the task 1 data evacuation performed during the execution of task 2 ends at time T32 and then an interrupt control signal input is received from the outside at time T33, the task switching control unit 41 Controls the switch 52 so that the program counter 1-1 is selected from the program counter 1-2 at time T34, and the memory elements 20-1, 21-1, 22-1 and 23-1 of the arithmetic circuit 3 are controlled. The switches 61 to 65 are controlled so as to select each of them. At time T35, the task switching control unit 41 controls the switches 68 and 69 to switch from the register file 4-2 to the path of the register file 4-1.
[0077]
Thereby, the data of the task 3 saved in the first save memory 42 is stored in the program counter 1-1, the storage elements 20-1, 21-1, 22-1 and 23-1, and the register of the arithmetic circuit 3. Each of the files is restored to the file 4-1, the task 3 is executed, and the task 2 that has been executed is interrupted. That is, the contents of the register file 4-1 and the data related to the internal state of the arithmetic circuit 3 in the execution of the task 1 have already been saved in the first save memory 42, so that the task 3 can be executed immediately.
[0078]
At time T38, when data is written back to the register file 4-1 by the stage 15 (when all tasks 2 are discharged), the task switching control unit 41 writes back task 3 to the register file 4-1. As described above, the switch 66 is switched.
[0079]
At the time T40 when the execution of the task 3 of the stage 11 ends, the task switching control unit 41 controls the switches 68 and 69 so as to switch from the register file 4-1 to the path 4-2. As a result, the execution of the task 2 suspended by the interruption is resumed.
[0080]
At time T41, the task switching control unit 41 causes the switches 61 to 65 and the switch 67 to be the “back” program counter 1-1, the storage elements 20-1, 21-1, 22-1 of the arithmetic circuit 3, and 23-1 and the register file 4-1 are selected, and the data saved in the first save memory 42 is stored in the register file 4-1, the program counter 1-1, and the arithmetic circuit 3. It is written and restored in the elements 20-1, 21-1, 22-1 and 23-1.
[0081]
As described above, the program counter 1-1, the storage elements 20-1, 21-1, 22-1 and 23-1, and the register file 4-1 of the arithmetic circuit 3, which are not currently used, are transferred to the interrupted task. Therefore, it is not necessary to save the state of task 2 that has been interrupted and suspended. That is, data saving and data restoration are unnecessary.
[0082]
FIG. 8 is a diagram for explaining a task switching timing operation by another external interrupt service. In this example, an operation when there is an interrupt service during data saving will be described.
[0083]
As shown in the figure, when the input of the interrupt control signal is received from the outside at time T31 in the middle of the data saving performed during the execution of the task 2, the task switching control unit 41 temporarily holds the reception, Wait until data saving is complete.
[0084]
When the data saving performed during the execution of the task 2 is completed at time T32, the task switching control unit 41 receives an input of the interrupt control signal that is suspended at time T33. At time T34, the task switching control unit 41 controls the switch 52 so as to select the program counter 1-1 from the program counter 1-2, and also stores the memory elements 20-1, 21-1, and 22 of the arithmetic circuit 3. The switches 61 to 65 are controlled to select 1 and 23-1. At time T35, the task switching control unit 41 controls the switches 68 and 69 to switch from the register file 4-2 to the path of the register file 4-1.
[0085]
Thereby, the data of the task 3 saved in the first save memory 42 is stored in the program counter 1-1, the storage elements 20-1, 21-1, 22-1 and 23-1, and the register of the arithmetic circuit 3. Each of the files is restored to the file 4-1, the task 3 is executed, and the task 2 that has been executed is interrupted.
[0086]
At time T38, when data is written back to the register file 4-2 by the stage 15 (when all tasks 2 are discharged), the task switching control unit 41 writes back task 3 to the register file 4-1. As described above, the switch 66 is switched. At time T39, the task switching control unit 41 causes the switch 51, the switches 53 to 56, and the switch 70 to be “back”, the program counter 1-2, and the storage elements 20-1, 21-2, and 22 of the arithmetic circuit 3. -2 and 23-2 and the register file 4-2 are selected, respectively, and the program counter 1-2, the storage elements 20-2, 21-2, 22-2 and 23-2 of the arithmetic circuit 3, In addition, the data stored in the register file 4-2 is saved in the first save memory 42.
[0087]
In this way, if an interrupt occurs while saving data, the interrupt control signal reception is suspended until the saving is completed, so that data can be saved reliably and there is no time overhead. Task switching can be executed.
[0088]
FIG. 9 is a diagram for explaining a task switching timing operation by another external interrupt service. In this example, the operation when there is an interrupt service during data restoration will be described.
[0089]
As shown in the figure, when an input of an interrupt control signal is accepted from the outside at time T11 in the middle of data restoration performed during the execution of task 2, the data restoration is stopped, and task switching control is performed at time T12. The unit 41 controls the switch 52 so as to select the program counter 1-1 from the program counter 1-2, and controls the switches 68 and 69 so as to switch the path from the register file 4-2 to the register file 4-1. To do.
[0090]
Thereby, the data of the task 3 saved in the first save memory 42 is stored in the program counter 1-1, the storage elements 20-1, 21-1, 22-1 and 23-1, and the register of the arithmetic circuit 3. Each of the files is restored to the file 4-1, the task 3 is executed, and the task 2 that has been executed is interrupted. Note that the data restored to the middle is overwritten by the interrupted task 3.
[0091]
When the interrupt service ends at time T19, at time T20, the task switching control unit 41 controls the switches 68 and 69 to switch from the register file 4-1 to the path of the register file 4-2. As a result, the suspended task 2 is resumed, and the restoration of the data suspended by the interruption is resumed at time T20.
[0092]
In this way, if an interrupt occurs during data restoration, the restoration is stopped, and when the interruption service ends, the restoration can be performed reliably, and the data can be restored reliably. Task switching can be performed without overhead.
[0093]
As described above, after the data of the back register file that is not used for the operation is saved in the first save memory 42, the data to be executed next is restored from the first save memory 42 there. Thus, task switching can be realized without time overhead for an almost unlimited interrupt service.
[0094]
【The invention's effect】
  According to the microprocessor of the present invention, a plurality of instructions are shifted in a plurality of stages and sequentially executed, thereby being simultaneously operated in parallel.Matching the status of multiple stages to multiple tasksTo remember, every stageIn association with 1 For the systemWhile selecting one of the storage paths provided in at least two systems and executing the first task using the selected storage path,Not used to execute the first taskRegarding the second task held in the memory pathStates in multiple stagesIs saved in the memory, and the third task saved in the memory isStates in multiple stagesIs restored to the other storage path, so that task switching can be realized without time overhead for an almost unlimited interrupt service. By eliminating the overhead, it is possible to efficiently perform high-speed switching of processing having different properties (such as demodulation and error correction) required by software radio.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating an internal configuration example of a conventional microprocessor;
FIG. 2 is a diagram for explaining a task switching timing operation by an interrupt service in the microprocessor of FIG. 1;
FIG. 3 is a diagram illustrating an internal configuration example of another conventional microprocessor;
4 is a diagram for explaining a task switching timing operation by an interrupt service in the microprocessor of FIG. 2; FIG.
FIG. 5 is a block diagram showing an example of the internal configuration of a microprocessor to which the present invention is applied.
6 is a diagram for explaining a task switching timing operation by an interrupt service in the microprocessor of FIG. 5; FIG.
7 is a diagram for explaining a task switching timing operation by an external interrupt service in the microprocessor of FIG. 5; FIG.
8 is a diagram illustrating task switching timing operation by another external interrupt service in the microprocessor of FIG. 5; FIG.
FIG. 9 is a diagram illustrating task switching timing operation by another external interrupt service in the microprocessor of FIG. 5;
[Explanation of symbols]
1-1, 1-2 Program counter, 2 instruction memory, 3 arithmetic circuit, 4-1, 4-2 register file, 5 data memory, 6 data cache, 7 instruction cache, 11 to 15 stages, 20-1, 20 -2, 21-1, 21-2, 22-1, 22-2, 23-1, 23-2 storage element, 41 task switching control unit, 42 first save memory, 43 second save memory, 51 70 switches

Claims (10)

A plurality of stages, and by sequentially executing a plurality of instructions while shifting the plurality of instructions in the plurality of stages, at least one calculation means for calculating data in parallel,
Storage means provided in at least two systems for one system of the computing means in association with each stage in order to store the states in the plurality of stages constituting the computing means in association with a plurality of tasks. When,
If the first task is executed, as storing respective states of the plurality of the stages, of the storage means provided at least two systems, so as to select one of said storage means for each said stage Control means for controlling;
During execution of the first task using said storage means selected by said control means, a plurality of related second task which is held by the first of said storage means is not used for execution of the task Retreating means for retreating the state in the stage ;
While the first task is being executed using the storage means selected by the control means, the states in the plurality of stages related to the third task saved in the saving means are displayed in the first task. A microprocessor comprising: a restoring unit that restores the storage unit that is not used for execution . When the task switching control signal is generated, the control means selects the storage means that is not used for the execution of the current task as a storage state of each state in the plurality of stages of a new task. 2. The microprocessor according to claim 1 , wherein the timing of selection of the storage means is controlled to be different for each of the storage means provided in association with each stage . When receiving an interrupt control signal from the outside, the control means selects the storage means that is not used for execution of the current task as one for storing the states of the new tasks in the plurality of stages. 2. The microprocessor according to claim 1 , wherein the timing of selecting the storage means is controlled so as to be different for each of the storage means provided in association with each stage . When receiving the input of the interrupt control signal while the data is being saved by the saving means, the control means holds the interrupt control signal until the saving of the data is completed by the saving means, When the saving of data is finished, the storage means that is not used for the execution of the current task is controlled to be selected as the storage state of each state in the plurality of stages of the new task, and the storage means 4. The microprocessor according to claim 3 , wherein the selection timing is controlled so as to be different for each of the storage units provided in association with each stage . When the interrupt control signal is received while the data is being restored by the restoration means, the control means stops the restoration of the data and is not used for execution of the current task. Are selected so as to store the respective states of the new tasks in the plurality of stages , and the storage means is selected in correspondence with the respective storage means provided for each stage. 4. The microprocessor according to claim 3, wherein the microprocessors are controlled differently . The microprocessor according to claim 1, wherein the storage unit further includes a register file. The microprocessor according to claim 1, wherein the storage unit further includes a program counter. The microprocessor according to claim 1, wherein a plurality of the evacuation units are provided and connected to each other. Connecting the evacuation means to a memory outside the microprocessor and the one-system arithmetic means;
The microprocessor according to claim 1, wherein the saving unit is operated as a cache of a memory existing outside the microprocessor. Connecting the evacuation means to a memory outside the microprocessor and the one-system arithmetic means;
The microprocessor according to claim 1, wherein the saving unit is operated as a substitute for a memory existing outside the microprocessor.

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