JP2009230410A - Information processor and radio communication equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption of an information processor. <P>SOLUTION: A main program P1 including a remap instruction and a jump instruction is recorded in a first memory 10. A sub-program P2 including the remap instruction and the jump instruction is recorded in a second memory 12. A CPU 14 executes a program of one memory selected from among the first and second memories 10 and 12. A bus 16 exchanges data between the first and second memories 10 and 12, and the CPU 14. The CPU 14 selects the first memory 10 and executes the main program P1 (state 1). Then, the CPU 14 changes a memory for executing the program to the second memory 12 by the remap instruction of the selected first memory 10, then jumps to the sub-program P2 recorded in the changed second memory 12 by the jump instruction of the selected first memory 10 to execute the jumped sub-program P2 (state 2). When shifting from the state 1 to the state 2, the CPU 14 turns off power of the first memory 10 which does not execute the program. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an information processing apparatus and a wireless communication apparatus that execute a program in one memory selected from a plurality of memories, and more particularly to an information processing apparatus and a wireless communication apparatus that can reduce power consumption.

  2. Description of the Related Art A wireless device including a reception circuit that receives a signal, a transmission circuit that transmits a signal, and a communication control circuit that controls the reception circuit and the transmission circuit is used (see, for example, Patent Document 1). The communication control circuit of such a wireless device includes a plurality of memories, a CPU that executes a program of one memory selected from the plurality of memories, and a bus that exchanges data between the two. Yes.

JP 7-264118 A

  FIG. 5 is a diagram illustrating a reference example of the information processing apparatus. In the first memory 100, a large main program P1 and a common program are recorded. In the second memory 102, a small subprogram P2 is recorded. The CPU 104 executes a program in one memory selected from the first memories 100 and 102. The bus 106 exchanges data between the first memories 100 and 102 and the CPU 104. The common program in the first memory 100 includes a remapping instruction for switching between the first memory 100 and the second memory 102, and is recorded at an address that does not overlap with the addresses of the main program P1 and the subprogram P2.

FIG. 6 is a diagram illustrating changes in the memory space of the CPU of the information processing apparatus of FIG. The operation of the information processing apparatus in FIG. 5 will be described with reference to FIG.
First, the CPU 104 selects the first memory 100 and executes the main program P1 (state 1). Then, the CPU 104 moves to the common program in the first memory 100, and changes the memory for executing the program to the second memory 102 by the remap instruction of the common program. As a result, the subprogram P2 holds and transfers the address information in the memory space.

  Next, the CPU 104 executes the subprogram P2 of the second memory 102 (state 2). Then, the CPU 104 shifts to the common program in the first memory 100 and changes the memory for executing the program to the first memory 100 by a remapping instruction of the common program. As a result, the main program P1 stores and transfers the address information in the memory space. Next, the CPU 104 executes the main program P1 of the first memory 100 (state 3).

  In the above operation, if the first memory 100 is turned off when the subprogram P2 of the second memory 102 is executed, the power consumption can be reduced. However, since a common program is written in the first memory 100, the power of the first memory 100 cannot be turned off. Therefore, it is conceivable to write a common program in the second memory 102, but the amount of memory in the second memory 102 increases by the amount of the common program.

  In the wireless communication apparatus, the microcomputer has a standby function, so that power consumption can be reduced. However, the power consumption of the flash ROM during the intermittent reception period has had a great influence on the service life of the battery.

  SUMMARY An advantage of some aspects of the invention is that it provides an information processing apparatus and a wireless communication apparatus that can reduce power consumption.

  An information processing apparatus according to the present invention includes a plurality of memories each storing a program including at least a remapping instruction and a jump instruction, a CPU for executing a program in one memory selected from the plurality of memories, a plurality of memories, And a bus for exchanging data with the CPU. The CPU changes the memory for executing the program by the remap instruction of the selected memory, and is recorded in the changed memory by the jump instruction of the selected memory. Jump to an arbitrary program, execute the jumped program, and turn off the power of at least one of the plurality of memories that does not execute the program. Other features of the present invention will become apparent below.

  According to the present invention, power consumption can be reduced.

Embodiment 1 FIG.
FIG. 1 is a diagram illustrating the information processing apparatus according to the first embodiment. In the first memory 10, a large main program P1 including a remap instruction and a jump instruction is recorded. In the second memory 12, a small subprogram P2 including a remap instruction and a jump instruction is recorded. The CPU 14 executes a program in one memory selected from the first and second memories 10 and 12. The bus 16 exchanges data between the first and second memories 10 and 12 and the CPU 14.

FIG. 2 is a diagram illustrating changes in the memory space of the CPU of the information processing apparatus of FIG. The operation of the information processing apparatus in FIG. 1 will be described with reference to FIG.
First, the CPU 14 selects the first memory 10 and executes the main program P1 (state 1). Then, the CPU 14 changes the memory for executing the program to the second memory 12 in accordance with the selected remapping instruction of the first memory 10. As a result, the subprogram P2 holds and transfers the address information in the memory space. Here, “transfer” means that it is imaged as such in the memory space of the CPU 14, and does not mean that data is actually moved.

  Next, the jump instruction of the selected first memory 10 jumps to the subprogram P2 recorded in the changed second memory 12, and the jumped subprogram P2 is executed (state 2). When shifting from the state 1 to the state 2, the CPU 14 turns off the power of the first memory 10 that does not execute the program.

  Next, the CPU 14 changes the memory for executing the program to the first memory 10 by the selected remapping instruction of the second memory 12. As a result, the address information is reserved in the memory space and transferred to the main program P1 in place of the subprogram P2. Furthermore, the jump instruction of the selected second memory 12 jumps to the main program P1 recorded in the changed first memory 10, and the jumped main program P1 is executed (state 3). When shifting from the state 2 to the state 3, the CPU 14 turns on the power of the first memory 10.

  As described above, since there is no common program area in the first memory 10 and the second memory 12, after switching the memory for executing the program by the remap instruction and the jump instruction, the power source of the switching source memory is turned off. can do. Thereby, power consumption can be reduced. This is particularly effective when using a memory with high power consumption such as a flash ROM.

Embodiment 2. FIG.
FIG. 3 is a diagram illustrating a wireless communication apparatus according to the second embodiment. The wireless communication apparatus includes a reception circuit 18 that receives a signal, a transmission circuit 20 that transmits a signal, and a communication control circuit 22 that controls the reception circuit and the transmission circuit.

  The communication control circuit 22 includes a microcomputer 24 and a flash ROM 26 (external memory) provided outside the microcomputer 24. In the flash ROM 26, a large main program P1 including a remapping instruction and a jump instruction is recorded.

  Inside the microcomputer 24, there are provided an SRAM 28 (internal memory), a CPU 14, and a flash ROM 26 and a bus 16 for transferring data between the SRAM 28 and the CPU 14. In the SRAM 28, a small subprogram P2 including a remap instruction and a jump instruction is recorded.

  In the above configuration, since it is not easy to provide a large program memory inside the microcomputer 24, the flash ROM 26 is provided outside. On the other hand, the SRAM 28 can be provided inside the microcomputer 24. Further, the power consumption of the flash ROM 26 is large, but the power consumption of the SRAM 28 is relatively small.

The operation of the wireless device of FIG. 3 will be described with reference to FIG.
During the transmission / reception period in which the reception circuit 18 and the transmission circuit 20 are operated, the CPU 14 turns on the power of the flash ROM 26 and executes the main program P 1 of the flash ROM 26.

  During the intermittent reception period in which the reception circuit 18 is operated at a predetermined timing, the CPU 14 executes the subprogram P2 of the SRAM 28. Here, the reception processing in the intermittent reception period has a smaller processing amount than the processing in the transmission / reception period, and therefore can be executed with a small subprogram P2.

  When moving from the intermittent reception period to the transmission / reception period, the CPU 14 changes the memory for executing the program to the flash ROM 26 by the remapping instruction of the SRAM 28 and turns on the power of the flash ROM 26. Then, the jump instruction of the SRAM 28 jumps to the main program P1 recorded in the flash ROM 26, and the jumped main program P1 is executed.

  When moving from the transmission / reception period to the intermittent reception period, the CPU 14 changes the memory for executing the program to the SRAM 28 in accordance with the remapping instruction of the flash ROM 26. Then, the jump instruction of the flash ROM 26 jumps to the subprogram P2 recorded in the SRAM 28, and the jumped subprogram P2 is executed.

  While the subprogram P2 is being executed, the power source of the flash ROM 26 with high power consumption is turned off. Thereby, the power consumption during the intermittent reception period can be reduced, and the service life of the battery can be extended.

1 is a diagram illustrating an information processing apparatus according to Embodiment 1. FIG. It is a figure which shows the change of the memory space of CPU of the information processing apparatus of FIG. 6 is a diagram showing a wireless communication apparatus according to Embodiment 2. FIG. It is a figure for demonstrating operation | movement of the radio | wireless apparatus of FIG. It is a figure which shows the reference example of information processing apparatus. It is a figure which shows the change of the memory space of CPU of the information processing apparatus of FIG.

Explanation of symbols

10 First memory (memory)
12 Second memory (memory)
14 CPU
16 Bus 18 Reception circuit 20 Transmission circuit 22 Communication control circuit 24 Microcomputer 26 Flash ROM (external memory)
28 SRAM (internal memory)

Claims (2)

A plurality of memories each storing a program including at least a remap instruction and a jump instruction;
A CPU for executing a program in one memory selected from the plurality of memories;
A bus for exchanging data between the plurality of memories and the CPU;
The CPU
The memory to execute the program is changed by the remap instruction of the selected memory.
Jumps to an arbitrary program recorded in the changed memory by executing the jump instruction of the selected memory, executes the jumped program,
An information processing apparatus comprising: turning off power to at least one memory that does not execute a program among the plurality of memories. A receiving circuit for receiving a signal;
A transmission circuit for transmitting a signal;
A communication control circuit for controlling the receiving circuit and the transmitting circuit;
The communication control circuit includes a microcomputer and an external memory provided outside the microcomputer,
Inside the microcomputer, there is an internal memory, a CPU that executes a program of one memory selected from the external memory and the internal memory, and data exchange between the external memory and the internal memory and the CPU. And a bus to perform,
In the external memory and the internal memory, programs each including at least a remapping instruction and a jump instruction are recorded,
In the transmission / reception period for operating the receiving circuit and the transmitting circuit, the CPU executes the program in the external memory,
In the intermittent reception period in which the reception circuit is operated at a predetermined timing, the CPU executes the program in the internal memory,
When moving from the intermittent reception period to the transmission / reception period, the CPU changes a memory for executing a program to the external memory, turns on the external memory, and turns on the internal memory in response to a remap command for the internal memory. To jump to an arbitrary program recorded in the external memory, execute the jumped program,
When moving from the transmission / reception period to the intermittent reception period, the CPU changes a memory for executing a program to the internal memory by a remap instruction of the external memory, and stores the internal memory by a jump instruction of the external memory. A wireless communication apparatus that jumps to an arbitrary recorded program, executes the jumped program, and turns off the power of the external memory.

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