JP2006227969A - Semiconductor integrated circuit and information processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit and an information processing apparatus, which can improve the performance of interrupt processing if reference targets for storage position information on interrupt handlers are fixed to interrupt vectors in a ROM. <P>SOLUTION: When receiving an interrupt signal from a specified device, if a CPU 11 specifies an address within interrupt vectors in a ROM 13, and requires a data read, a combination circuit 14d switches the data read request to the ROM 13 to a RAM 12. In addition, a memory controller 14e switches the address within the interrupt vectors in the ROM 13 to an address in an area of the RAM 12 storing information copied from the interrupt vectors to read out the information from the RAM 12 and then transmits it to the CPU 11. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention includes a semiconductor integrated circuit having a function of controlling data exchange between a CPU [Central Processing Unit], a ROM [Read Only Memory], and a RAM [Random Access Memory], and the semiconductor integrated circuit is incorporated. The present invention relates to an information processing apparatus.

  As is well known, interrupt processing refers to processing performed by interrupting the processing that has been performed by the CPU that has received the interrupt signal from the device. When the CPU interrupts processing upon receiving an interrupt signal, the CPU refers to an area (interrupt vector) in which storage location information (address) of an instruction code (program) called an interrupt handler is recorded, and then reads the target interrupt handler to obtain a predetermined The routine is executed.

  By the way, among the devices that perform the interrupt processing as described above, there is one in which the reference destination of the storage location information of the interrupt handler is fixed to the ROM interrupt vector. In this case, the CPU refers to the information in the interrupt vector by accessing the ROM after receiving the interrupt signal.

  However, since the access speed to the ROM is lower than the access speed to the RAM, it is possible for some consumers to interrupt the storage by referring to the storage location information of the interrupt handler through the RAM access. Some people have asked if processing performance can be improved.

  The present invention has been made in view of the above-mentioned conventional circumstances, and its problem is to improve the performance of interrupt processing when the reference destination of the storage location information of the interrupt handler is fixed to the ROM interrupt vector. It is to improve.

  A semiconductor integrated circuit invented to solve the above problems is an information processing apparatus comprising a CPU, a ROM, a RAM, and a copy means for copying information in an area mapped as an interrupt vector in the ROM to the RAM. Is incorporated into the CPU to control the exchange of data between the CPU and the ROM and the RAM, and the data read request to the ROM is designated together with the designation of the address in the interrupt vector of the ROM. When the request accepting unit that accepts from the CPU and the request accepting unit accepts the read request from the CPU, information copied from the interrupt vector of the ROM to the RAM is read from the RAM by the copying unit, and It is necessary to provide a vector reading unit that is handed over to the CPU. It is set to.

  With this configuration, even when the reference destination of the interrupt handler storage location information is fixed to the ROM interrupt vector, the interrupt handler storage location information itself has a higher access speed than the ROM. Since the data is read from the RAM, the interrupt processing performance is improved as compared with the conventional access to the ROM.

  An information processing apparatus invented to solve the above problems includes a CPU, a ROM, a RAM, and a semiconductor integrated circuit for controlling the exchange of data between the CPU and the ROM and the RAM. And a copy means for copying information in an area mapped as an interrupt vector in the ROM to the RAM, wherein the semiconductor integrated circuit is configured to specify the address in the interrupt vector of the ROM together with the ROM. A request accepting unit that accepts a data read request from the CPU, and information that is copied from the interrupt vector of the ROM to the RAM by the copying unit when the request accepting unit accepts the read request from the CPU. Is read from the RAM and delivered to the CPU The Rukoto, is characterized.

  Therefore, this information processing apparatus functions in the same manner as the information processing apparatus incorporating the semiconductor integrated circuit of the present invention described above.

  As described above, according to the present invention, even when the reference destination of the storage location information of the interrupt handler is fixed to the ROM interrupt vector, the interrupt processing performance is improved.

  Hereinafter, an information processing apparatus which is one embodiment for carrying out the present invention will be described with reference to the accompanying drawings.

  FIG. 1 is a simple internal configuration diagram of an information processing apparatus 10 according to the present embodiment. The information processing apparatus 10 is a device such as a computer or a printer, and includes a CPU 11, a RAM 12, a ROM 13, and an ASIC 14 as main components.

  The CPU 11 is a circuit that controls the information processing apparatus 10 as a whole. The RAM 12 is a volatile memory in which the work area of the CPU 11 is expanded.

  The ROM 13 is a non-volatile memory in which various programs and data for controlling the information processing apparatus 10 are recorded. In the present embodiment, several interrupt handlers are recorded in the ROM 13, and storage location information (address) of these interrupt handlers is recorded in an area mapped as an interrupt vector in the ROM 13. The ROM 13 stores a program for causing the CPU 11 to copy the storage location information of the interrupt handler to a predetermined area in the RAM 12 when the information processing apparatus 10 is activated.

  FIG. 2 is a diagram showing a memory map of this embodiment. As shown in FIG. 2, addresses after 0x0000_0000 are assigned to the ROM 13, and addresses after 0x8000_0000 are assigned to the RAM 12. The area from 0x0000_0000 to 0x0000_0FFF in the ROM 13 is an area as the above interrupt vector, and the area from 0x8000_0000 to 0x80000_0FFF in the RAM 12 is the storage location of the interrupt handler recorded in the interrupt vector. It is an area where information is copied.

  The ASIC 14 is a semiconductor integrated circuit that functions as at least an interface between the CPU 11 and the RAM 12 and an interface between the CPU 11 and the ROM 13 and includes a plurality of circuit modules.

  Specifically, a part of the configuration of the ASIC 14 will be described. As shown in FIG. 1, the ASIC 14 includes a switching register 14a, an address decoding circuit 14b, a main state circuit 14c, a combinational circuit 14d, and a memory controller 14e. , Including.

  The switching register 14a is a storage element in which information defining whether the storage position information delivered to the CPU 11 is in the ROM 13 or the RAM 12 is recorded. In the present embodiment, the information in the switching register 14 a is “0 (ROM)” by default, and the CPU 11 according to the program in the ROM 13 stores the interrupt handler storage location from the interrupt vector in the ROM 13. After the information is copied to the RAM 12, the information in the switching register 14a is switched from “0 (ROM)” to “1 (RAM)”. When “0 (ROM)” is recorded in the switching register 14a, the signal output from the INTMODE terminal is set to LOW, and when “1 (RAM)” is recorded, the signal is output from the INTMODE terminal. Signal to be HIGH.

  The address decoding circuit 14b is a circuit module that performs processing when a request to read data from the RAM 12 or the ROM 13 is received from the CPU 11.

  The processing performed by the address decode circuit 14b will be described in detail. In the normal state, the address decode circuit 14b keeps the signal output from the INTV_DEC terminal in the LOW state, and the CPU 11 transmits a data read request through the control bus. At the same time, when an address in the range (interrupt vector) from 0x0000_0000 to 0x0000_0FFF in the ROM 13 is designated through the address bus, a HIGH pulse is generated in the INTV_DEC signal.

  In the normal state, the address decode circuit 14b keeps the signal output from the RAM_DEC terminal in the LOW state, the CPU 11 transmits a data read request through the control bus, and any one of the RAM 12 in the RAM 12 through the address bus. When an address is designated, a HIGH pulse is generated in the RAM_DEC signal.

  Further, in a normal state, the address decode circuit 14b keeps the signal output from the ROM_DEC terminal in the LOW state, and the CPU 11 transmits a data read request through the control bus, and any one of the ROMs 13 in the ROM 13 through the address bus. When an address is designated, a HIGH pulse is generated in the ROM_DEC signal.

  Therefore, when the CPU 11 transmits a data read request and designates an address in the RAM 12, a HIGH pulse is generated in the RAM_DEC signal, and a HIGH pulse is not generated in the ROM_DEC signal and the INTV_DEC signal.

  In addition, when the CPU 11 transmits a data read request and designates an address other than the address in the interrupt vector of the ROM 13, a HIGH pulse is generated in the ROM_DEC signal, and no HIGH pulse is generated in the RAM_DEC signal and the INTV_DEC signal. .

  When the CPU 11 transmits a data read request and designates an address in the interrupt vector of the ROM 13, a HIGH pulse is not generated in the RAM_DEC signal, and a HIGH pulse is simultaneously generated in the ROM_DEC signal and the INTV_DEC signal.

  The main state circuit 14c is a circuit module that detects that the CPU 11 has transmitted a data read request through the control bus. The processing performed by the main state circuit 14c will be described in detail. In the normal state, the main state circuit 14c keeps the signal output from the REQ terminal in the LOW state, and the CPU 11 transmits a data read request through the control bus. When this occurs, a HIGH pulse is generated in the REQ signal. Therefore, when the address decode circuit 14b generates a HIGH pulse in the RAM_DEC signal or generates a HIGH pulse in the ROM_DEC signal, a HIGH pulse is generated in the REQ signal.

  The address decoding circuit 14b and the main state circuit 14c described above correspond to the request accepting unit described above.

  The combinational circuit 14d is a circuit module for changing the states of the RAM_REQ signal and the ROM_REQ signal input to the memory controller 14e based on the INTMODE signal, the INTV_DEC signal, the RAM_DEC signal, the ROM_DEC signal, and the REQ signal.

  The processing performed by the combinational circuit 14d will be specifically described. In the combinational circuit 14d, the RAM_DEC signal and the REQ signal are HIGH (at this time, the ROM_DEC signal and the INTV_DEC signal are both LOW as described above). In some cases, whether the INTMODE signal is LOW or HIGH, the RAM_REQ signal is set to HIGH and the ROM_REQ signal is set to LOW.

  The combinational circuit 14d determines that the INTMODE signal is LOW when the ROM_DEC signal and the REQ signal are HIGH and the INTV_DEC signal is LOW (at this time, the RAM_DEC signal is LOW as described above). Whether the signal is HIGH or HIGH, the RAM_REQ signal is set to LOW and the ROM_REQ signal is set to HIGH.

  Further, the combinational circuit 14d is configured such that when the ROM_DEC signal, the INTV_DEC signal, and the REQ signal are all HIGH (as described above, the RAM_DEC signal is LOW), the RAM_REQ signal is output when the INTMODE signal is LOW. Is set to LOW, the ROM_REQ signal is set to HIGH, and when the INTMODE signal is HIGH, the RAM_REQ signal is set to HIGH and the ROM_REQ signal is set to LOW.

  The memory controller 14e is a circuit module for controlling reading / writing of data to / from the RAM 12 and reading of data from the ROM 13. The RAM_REQ signal and the ROM_DEC signal are input to the memory controller 14e from the combinational circuit 14d. ing.

  The processing performed by the memory controller 14e will be specifically described. When the RAM_REQ signal becomes HIGH, the memory controller 14e receives data from the address in the RAM 12 when the address in the RAM 12 is designated through the address bus. Read out and deliver to CPU11.

  In addition, when the ROM_REQ signal becomes HIGH and the address in the ROM 13 is designated through the address bus, the memory controller 14e reads data from the address in the ROM 13 and delivers it to the CPU 11.

  In addition, when the RAM_REQ signal becomes HIGH, the memory controller 14e, when any address in the range (interrupt vector) from 0x0000_0000 to 0x0000_0FFF in the ROM 13 is designated through the address bus, only the lower address thereof is designated. Since no reference is made, the corresponding address in the range from 0x8000_0000 to 0x8000_0FFF in the RAM 12 is accessed, and the storage location information of the address is read and transferred to the CPU 11.

  The switching register 14a, the combinational circuit 14d, and the memory controller 14e described above correspond to the vector reading unit described above. The program in the ROM 13 and the CPU 11 correspond to the above-described copying means.

  In the information processing apparatus 10 configured as described above, the information in the interrupt vector is copied to the RAM 12 and “1 (RAM)” is recorded in the switching register 14a at the time of startup, and the INTMODE signal is always HIGH. become.

  In such a state, the CPU 11 that has received an interrupt signal from a device (not shown) designates any address in the range (interrupt vector) from 0x0000_0000 to 0x0000_0FFF in the ROM 13 and requests to read data. Only in the above case, the combinational circuit 14d always sets the RAM_REQ signal to HIGH and the ROM_REQ signal to LOW as described above. Then, as described above, the memory controller 14e recognizes that the RAM_REQ signal has become HIGH despite the address in the interrupt vector of the ROM 13 being specified by the CPU 11, and stores the storage location information of the interrupt handler. Is read from the RAM 12, and the storage location information is read from the RAM 12 and delivered to the CPU 11.

  Therefore, according to the information processing apparatus 10 of this embodiment, even when the reference destination of the interrupt handler storage location information is fixed to the interrupt vector of the ROM 13, the interrupt handler storage location information itself is stored in the ROM 13. Compared to the conventional access from the ROM 13, the interrupt processing performance is improved because the RAM 12 having a higher access speed is copied to the RAM 12 at the time of startup and read from the RAM 12 at the time of reading. . However, the CPU 11 does not have to be aware that the storage location information of the interrupt handler is also stored in the RAM 12.

  Even if the switching register 14a, the address decoding circuit 14b, the main state circuit 14c, and the combinational circuit 14d are designed and manufactured so as to be newly incorporated in the ASIC 14, the circuit modules 14a to 14d have a gate scale. Since it is extremely small, it hardly increases the design and manufacturing cost of the ASIC 14.

Simple internal configuration diagram of the information processing apparatus according to the present embodiment The figure which shows the memory map of this embodiment

Explanation of symbols

10 Information processing apparatus 11 CPU
12 RAM
13 ROM
14 ASIC
14a switching register 14b address decoding circuit 14c main state circuit 14d combinational circuit 14e memory controller

Claims (4)

The CPU, the ROM, the RAM, and the information processing apparatus provided with a copy unit that copies the information in the area mapped as an interrupt vector in the ROM to the RAM. A semiconductor integrated circuit for controlling the exchange of data between them,
A request accepting unit for accepting from the CPU a request to read data from the ROM together with designation of an address in the interrupt vector of the ROM; and
When the request accepting unit accepts the read request from the CPU, the copy reading unit includes a vector reading unit that reads information copied from the interrupt vector of the ROM from the RAM to the RAM and delivers it to the CPU. A semiconductor integrated circuit. The vector read unit switches the read request to the ROM to the read request to the RAM, and the address designation in the interrupt vector of the ROM is copied with the information in the interrupt vector in the RAM. 2. The semiconductor integrated circuit according to claim 1, wherein the information is read from the RAM by switching to designation of an address in the area. An information processing apparatus comprising a CPU, a ROM, a RAM, and a semiconductor integrated circuit for controlling data exchange between the CPU and the ROM and the RAM,
Copying means for copying information in an area mapped as an interrupt vector in the ROM to the RAM;
The semiconductor integrated circuit is
A request accepting unit for accepting from the CPU a request to read data from the ROM together with designation of an address in the interrupt vector of the ROM; and
When the request accepting unit accepts the read request from the CPU, the copy reading unit includes a vector reading unit that reads information copied from the interrupt vector of the ROM from the RAM to the RAM and delivers it to the CPU. A characteristic information processing apparatus. 4. The information processing apparatus according to claim 3, wherein the copying unit copies information in an area mapped as the interrupt vector in the ROM to the RAM when main power is turned on.