JP2007094528A - Method for using memory of multiprocessor system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multiprocessor system having a main processor and a plurality of subprocessors and whose costs can be reduced, the processors sharing memory with one another. <P>SOLUTION: The program of the subprocessors is divided into an initialized part, a common part to different operations, and characteristic parts for the different operations. The overwrite of the initialized part and the common part is inhibited once they are stored in memory. Of the characteristic parts, only those required for the operations of the subprocessors are stored in memory. The overwrite of the characteristic parts stored in memory is permitted when the subprocessors stop. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for using a memory, particularly in a multiprocessor system that includes a main processor and a plurality of sub-processors and shares the memory among the processors.

  In recent years, system LSIs are generally equipped with a plurality of processors in order to realize high functions and high performance. An example of such a system is shown in FIG. A system LSI 1 implemented as a single chip includes a main processor 10 and a sub processor 11, and shares a RAM controller 13 and an external RAM 22 via independent buses. When the power is turned on, only the main processor 10 operates, and a program is loaded from the external ROM 21 via the ROM controller 12 and executed. The main processor 10 controls the start / stop of the sub processor 11 and stores the program for the sub processor 11 in the external RAM 22. The sub processor 11 loads and executes a program from the external RAM 22 in response to a start command from the main processor 10. Further, the sub-processor 11 is activated only when processing is necessary to suppress power consumption, and stops when the processing is completed.

For example, Patent Document 1 can be cited as a conventional example.
JP 11-338833 A

  When the system LSI 1 is incorporated in a device, the main processor 10 writes the program for the sub processor 11 to the external RAM 22 that greatly affects the performance of the entire device. For example, if the number of times the program for the sub processor 11 is written is only one, the influence on the entire device is minimal. To realize this, it is sufficient not to change the area in which the program for the sub processor 11 is once written. A large capacity external RAM 22 is required, which increases the cost of the equipment.

  When the sub processor 11 is stopped, if the main processor 10 releases the area in which the sub processor 11 program is written so that the main processor 10 can be changed, the sub processor 11 must be written when the sub processor 11 is restarted. In other words, there is a problem that it takes time to start up the sub processor 11 and the performance of the entire apparatus is lowered.

  The present invention has been made to solve such a problem. A multiprocessor system capable of reducing the cost by efficiently using an external RAM without significantly degrading the performance of the entire device is provided. The purpose is to provide.

  A method for using a memory of a multiprocessor system according to claim 1 comprises a main processor, a plurality of sub-processors, and a memory shared among the processors, and the sub-processor reads a program from the memory and operates. In addition, the sub-processor program can be stored in the memory only by the main processor, and the sub-processor program is initialized in a multiprocessor system that repeatedly starts, operates, and stops during system operation. The initializing part and each operation common part are prohibited from being overwritten once stored in the memory, and each operation specific part is an operation of the sub-processor. Is stored in the memory, only what is necessary for the The operation specific part is permitted to be overwritten when the sub-processor is stopped.

  As a result, when the sub processor is started for the second time or later, the main processor only needs to store the initialization portion and the operation specific portion excluding each operation common portion in the memory, so that the start time of the sub processor can be shortened.

  Further, since the operation specific part is permitted to be used by other processors when the sub processor is stopped, the memory can be used efficiently, and the capacity of the mounted memory does not have to be increased.

According to the memory usage method in the multiprocessor system according to claim 1,
Even if the capacity of the memory mounted on the system is not increased, the startup time of the sub-processor can be shortened, and a low-cost multiprocessor system can be realized in which the performance is not significantly reduced.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing a multiprocessor system to which the memory usage method of the present invention is applied.

  Reference numeral 1 denotes a system LSI in which a plurality of processors and various circuits are configured as one chip.

  The main processor 10 controls the entire system LSI 1, reset is released immediately after the system power is turned on, starts its operation, and does not stop during system operation. At startup, a program is loaded from the external ROM 21 via the ROM controller 12 and executed. After startup, the program can be stored in the external RAM 22 via the RAM controller 13 and loaded from the RAM 22 for execution.

  The sub-processor 11 is stopped in a reset state immediately after the system is turned on. When the reset is released by the main processor 10, the program is loaded from the RAM 22 and executed. When the predetermined operation ends, the main processor 10 is notified of the end, and the main processor 10 sets the reset state again.

  The ROM controller 12 controls the ROM 21 so that the main processor 10 can read data in the external ROM 21.

  The RAM controller 13 controls the RAM 22 so that the main processor 10 and the sub processor 11 can read and write data to the external RAM 22.

  The sub processor control circuit 14 has a function of controlling a reset signal of the sub processor 11 and a notification function from the sub processor 11 to the main processor 10.

  The ROM 21 is a nonvolatile memory in which programs for the main processor 10 and the sub processor 11 are stored.

  The RAM 22 is a volatile memory that can hold data during system operation. It is used as a program storage or work area for the main processor 10 and the sub processor 11.

  FIG. 2 shows a program for the sub-processor 11 stored in the ROM 21.

  The program of the sub processor 11 depends on the initialization portion 31 that is executed only once when the sub processor 11 is started, the operation common portions 32 that are executed in common during each operation without depending on the specific operation, and the specific operation. It is divided into each operation specific part 33 to be executed.

  Next, the operation will be described.

  In the multiprocessor system to which the memory usage method of the present invention is applied, the reset of the main processor 10 is released after the system is turned on, the program stored in the ROM 21 is executed, and the initialization of the entire system is started. In the initialization process, the main processor 10 initializes various circuits, initializes an area used by the RAM 22 itself, and the like.

  While the system is operating, the main processor 10 controls the various circuits, and starts up the sub-processor 11 as necessary to perform predetermined processing and stop the operation. For example, when a processor-intensive process such as image processing is necessary, the sub-processor 11 performs the process, and stops when the process is completed. By controlling the sub processor 11 in this way, power consumption due to the operation of the sub processor 11 can be suppressed.

  FIG. 3 is a flowchart from start to stop of the sub processor 11.

  The main processor 10 determines whether or not the sub processor 11 is activated for the first time (step S11). In the first activation (YES in step S11), the initialization portion 31 and each operation common portion 32 of the sub processor program are loaded from the ROM 21 and stored in a predetermined area of the RAM 22 (step S12). In this process, the sub processor program stored in the RAM 22 is not changed during system operation. Therefore, in the case of the second or subsequent activation (NO in step S11), the above-described process is omitted, and the activation process of the sub processor 11 is shortened.

  Next, in order to cause the sub-processor 11 to perform a predetermined operation, a necessary part from the operation specific part 33 of the program is stored in the RAM 22 (step S13). The main processor 10 operates the sub processor control circuit 14 to release the reset of the sub processor 11 (step S14). The main processor 10 waits for an operation end notification of the sub processor 11 while performing other processes during the operation of the sub processor 11 (step S15). When the predetermined operation ends, the sub processor 11 notifies the main processor 10 of the end via the sub processor control circuit 14. The main processor 10 receives an operation end notification from the sub processor 11 (YES in step S15), and operates the sub processor control circuit 14 to reset the sub processor 11 (step S16).

  The area of the RAM 22 in which the operation specific part of the sub processor program is temporarily stored is allowed to be used by the main processor 10 while the sub processor 11 is stopped. By permitting, the RAM 22 can be used efficiently, and the capacity of the RAM 22 installed in the system can be reduced.

  The above description is for the case where there is one sub-processor, but the memory usage method of the present invention can be similarly applied even when there are a plurality of sub-processors.

1 is a configuration diagram showing a multiprocessor system to which a memory usage method of the present invention is applied. Sub-processor 11 program stored in ROM 21 Flow chart from start to stop of sub-processor 11

Explanation of symbols

1 1-chip system LSI
10 Main processor 11 Sub processor 12 ROM controller 13 RAM controller 14 Sub processor control circuit 21 ROM
22 RAM
31 Initialization part of subprocessor program 32 Common operation part of subprocessor program 31 Specific operation part of subprocessor program

Claims (1)

A main processor;
Multiple sub-processors;
It has a memory shared between each processor,
The sub-processor reads and operates a program from the memory; and
The sub processor program can be stored in the memory only by the main processor, and
In the multiprocessor system in which the sub-processor is repeatedly started, operated, and stopped during system operation,
The sub processor program is divided into an initialization part, an operation common part, and an operation specific part,
The initialization part and each operation common part are prohibited from overwriting once stored in the memory,
Each operation specific part is stored in the memory only for the operation of the sub-processor,
A method of using a memory in a multiprocessor system, wherein the operation specific part stored in the memory is allowed to be overwritten when the sub processor is stopped.

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