JP2005258453A - Drive circuit for display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a drive circuit with which a practical 8-bit digital driver is realized without any increase in circuit scale. <P>SOLUTION: The drive circuit for a display device is provided with a voltage dividing circuit 10 which generates a plurality of first interpolating voltages between a plurality of gradation voltages that are obtained by dividing a plurality of gradation voltages provided externally, a logic circuit 42 which selects a first voltage and a second voltage, different from the first voltage, from the plurality of gradation voltages and the plurality of the first interpolating voltages in accordance with the first bit portion of digital data, a voltage dividing circuit 42 which generates a plurality of second interpolating voltages between the first voltage and the second voltage by dividing the first and the second voltages and a logic circuit 43 which selects at least one of the first voltage or the second voltage and one of the plurality of the second interpolating voltages in accordance with the second bit portion of the digital data. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a drive circuit for an active matrix type flat display device, and more particularly to a drive circuit for a liquid crystal display device that realizes gradation display of 256 gradations or more.

  FIG. 15 shows a configuration of a conventional drive circuit. This drive circuit is a circuit corresponding to one output in a 3-bit digital driver.

  The drive circuit shown in FIG. 15 includes a sampling storage unit 131, a holding storage unit 132, and an output circuit 133. In response to the rising edge of the sampling pulse Tsmp, 3-bit digital data D0 to D2 are stored in the sampling storage unit 131. The digital data stored in the sampling storage unit 131 is moved to the holding storage unit 132 in response to the rising edge of the output pulse OP and held there. The output circuit 133 outputs one of the gradation voltages V0 to V7 supplied from the outside as the output voltage Out in accordance with the value of the digital data stored in the storage unit 132.

  FIG. 16 shows the configuration of the output circuit 133. The output circuit 133 includes a 3-to-8 decoder 141 and eight analog switches ASW0 to ASW7. The decoder 141 turns on one of the analog switches ASW0 to ASW7 in accordance with the value of the digital data. As a result, the gradation voltage supplied to the analog switch that is turned on is output as the output voltage Out.

  The digital driver having the configuration shown in FIG. 15 and FIG. 16 has the advantage that the power consumption of the circuit itself is small in addition to the simple structure, and has been widely used conventionally. The digital driver having such a configuration is described in the following document, for example.

Development of a Low Voltage SourceDriver for Large TFT-LCD System for Computer Applications
H. Okada et al. 1991 International Di
spray Research Conference p. 111-p. 114
The digital driver having the above-described configuration requires the same number of gradation power supplies as the number of gradations to be displayed. This is not a problem for 3-bit digital drivers, but can be a problem for digital drivers with more bits. This is because the number of gradation power sources becomes too large. In particular, it can be said that it is substantially impossible to realize a high multi-gradation of 6 bits or more using the digital driver having the above-described configuration.

  In order to solve such a problem, various methods for realizing multi-gradation by generating an interpolation voltage between gradation voltages given from the outside have been proposed.

  For example, Japanese Patent Laid-Open No. 5-273520 shows one such technique. Japanese Patent Application Laid-Open No. 5-273520 shows a circuit that generates an interpolation voltage between gradation voltages using a resistance inside a driver. This circuit selects one of the gradation voltage and the interpolation voltage, and outputs the selected voltage to the data line of the display body via the buffer amplifier.

  FIG. 17 shows a configuration of the drive circuit 151 and the voltage dividing circuit 152 disclosed in Japanese Patent Laid-Open No. 5-273520. The drive circuit 151 is a circuit corresponding to one output in the 4-bit digital driver.

  The voltage dividing circuit 152 divides five gradation voltages V0, V4, V8, V12, and V15 given from the outside using resistors, thereby generating one or more interpolated voltages between adjacent gradation voltages. To do. As a result, a total of 16 voltages V0 to V15 of 5 gradation voltages and 11 interpolation voltages are supplied to the drive circuit 151.

  The drive circuit 151 selects any one of the 16 voltages V0 to V15 supplied from the voltage dividing circuit 152 according to the value of the digital data, and the selected voltage is passed through the buffer amplifier 157. Output.

  Hereinafter, the configuration of the drive circuit 161 and the voltage dividing circuit 162 when the technique disclosed in Japanese Patent Laid-Open No. 5-273520 is applied to a 6-bit digital driver will be described with reference to FIGS.

  FIG. 18A shows the configuration of the voltage dividing circuit 162. The voltage dividing circuit 162 divides the nine gradation voltages V0, V8, V16, V24, V32, V40, V48, V56, and V64 given from the outside by using a resistor, so that the adjacent gradation voltages are divided. Seven interpolation voltages are generated for each. As a result, a total of 64 voltages V0 to V63 of 8 gradation voltages and 56 interpolation voltages are supplied to the drive circuit 161.

  FIG. 18B shows a resistance arrangement between the gradation voltage V0 and the gradation voltage V8 shown in FIG. Eight resistors R connected in series are provided between the gradation voltage V0 and the gradation voltage V8. The same applies to the resistance arrangement between the other gradation voltages.

  FIG. 19 shows the configuration of the drive circuit 161. The drive circuit 161 is a circuit corresponding to one output in the 6-bit digital driver.

  FIG. 20 shows the configuration of the output circuit 173 (FIG. 19). The output circuit 173 includes a 6-to-64 decoder 181 and 64 analog switches ASW0 to ASW63. 64 voltage voltages V0 to V63 supplied from the voltage dividing circuit 162 are input to the analog switches ASW0 to ASW63, respectively. The decoder 181 turns on one of the analog switches ASW0 to ASW63 according to the value of the digital data. As a result, the voltage supplied to the analog switch that is turned on is output as the output voltage Out through the buffer amplifier 183.

  Hereinafter, the configuration of the drive circuit 191 and the voltage dividing circuit 192 when the technique disclosed in Japanese Patent Laid-Open No. 5-273520 is applied to an 8-bit digital driver will be described with reference to FIGS.

  FIG. 21A shows the configuration of the voltage dividing circuit 192. The voltage dividing circuit 192 divides the nine gradation voltages V0, V32, V64, V96, V128, V160, V192, V224, and V256 given from the outside by using a resistor, so that the adjacent gradation voltages are divided. Each of the 31 interpolation voltages is generated. As a result, a total of 256 voltages V0 to V255 of 8 gradation voltages and 248 interpolation voltages are supplied to the drive circuit 191.

  FIG. 21B shows a resistor array between the gradation voltage V0 and the gradation voltage V32 shown in FIG. 32 resistors R connected in series are provided between the gradation voltage V0 and the gradation voltage V32. The same applies to the resistance arrangement between the other gradation voltages.

  FIG. 22 shows the configuration of the drive circuit 191. The drive circuit 191 is a circuit corresponding to one output in the 8-bit digital driver.

  FIG. 23 shows the configuration of the output circuit 203 (FIG. 22). The output circuit 203 includes an 8-to-256 decoder 211 and 256 analog switches ASW0 to ASW256. The analog switches ASW0 to ASW256 receive 256 voltages V0 to V255 supplied from the voltage dividing circuit 192, respectively. The decoder 211 turns on one of the analog switches ASW0 to ASW255 according to the value of the digital data. As a result, the voltage supplied to the analog switch that is turned on is output as the output voltage Out through the buffer amplifier 213.

  According to the conventional method, the 6-bit digital driver requires 64 resistors for the voltage dividing circuit 162. This is because eight resistors are required between adjacent gradation voltages. In contrast, an 8-bit digital driver requires 256 resistors for the voltage divider circuit 192. This is because 32 resistors are required between adjacent gradation voltages.

  Thus, an 8-bit digital driver requires four times as many resistors as a 6-bit digital driver. This increases the area required for the voltage divider circuit.

  In the 6-bit digital driver, 64 voltages V0 to V63 are supplied from the voltage dividing circuit 162 to the driving circuit 161, whereas in the 8-bit digital driver, 256 voltages V0 to V255 are supplied from the voltage dividing circuit 192. It is supplied to the drive circuit 191.

  The voltage output from the voltage dividing circuit is supplied to the drive circuit via the voltage supply line. Therefore, the 8-bit digital driver requires four times as many voltage supply lines as the 6-bit digital driver. This quadruples the area occupied by the voltage supply line, resulting in an increase in chip area.

  Further, the output circuit 203 of the 8-bit digital driver is many times larger than the output circuit 173 of the 6-bit digital driver. The 8-to-256 decoder 211 included in the output circuit 203 of the 8-bit digital driver requires a much larger number of logic gates than the 6-to-64 decoder 181 included in the output circuit 173 of the 6-bit digital driver. Because. Also, the output circuit 203 of the 8-bit digital driver requires four times as many analog switches as the output circuit 173 of the 6-bit digital driver.

  Note that the decoder is not necessarily realized by a combination of logic gates. For example, the decoder can be realized by a read-only memory (ROM). In this case as well, the 8-to-256 decoder 211 remains substantially larger than the 6-to-64 decoder 181.

  One driver has the same number of output circuits as drive terminals. Therefore, an increase in the size of the output circuit causes a significant increase in the size of the LSI constituting the driver.

  For example, assume that the driver has 240 drive terminals. In this case, when the size of one output circuit corresponds to 50 gates, the size of the entire driver corresponds to 12000 (= 50 × 240) gates. On the other hand, when the size of one output circuit corresponds to 100 gates, the size of the entire driver corresponds to 24000 (= 100 × 240) gates.

  Thus, even if the number of gates is only 100 gates in one drive circuit, the number of gates in the entire driver is increased by 12,000.

  For the reasons described above, according to the conventional method, the 8-bit digital driver becomes significantly larger than the 6-bit digital driver. This makes the realization of an 8-bit digital driver virtually impossible.

  The present invention has been made in view of such problems, and an object thereof is to provide a drive circuit that realizes a practical 8-bit digital driver without increasing the circuit scale.

The present invention is a drive circuit for a display device that displays a plurality of gradations according to digital data including a first bit portion and a second bit portion, and divides a plurality of gradation voltages applied from the outside. A first voltage dividing circuit for generating a plurality of first interpolation voltages between the plurality of gradation voltages, and the plurality of gradation voltages and the plurality of gradations according to the first bit portion of the digital data. A first selection circuit that selects a first voltage and a second voltage that is different from the first voltage from among the first interpolation voltage, and the first voltage and the second voltage are divided by dividing the first voltage. A second voltage dividing circuit for generating a plurality of second interpolation voltages between the voltage and the second voltage, and at least one of the first voltage and the second voltage in accordance with the second bit portion of the digital data. A second selection circuit that selects one of the plurality of second interpolation voltages and the first voltage; A first impedance converter for receiving comprises a second impedance converter for receiving the second voltage, and
The second voltage dividing circuit divides the output of the first impedance converter and the output of the second impedance converter, thereby providing an output of the first impedance converter and an output of the second impedance converter. The plurality of second interpolation voltages are generated during the period, and the first impedance converter and the second impedance converter allow the voltage value of the output load of the second selection circuit to reach a steady state within one output period. It is a drive circuit characterized by having.

  The present invention also provides a driving circuit for a display device that displays a plurality of gradations according to digital data including a first bit portion and a second bit portion, and divides a plurality of gradation voltages applied from the outside. A first voltage dividing circuit that generates a plurality of first interpolation voltages between the plurality of gradation voltages, and the plurality of gradation voltages and the plurality of gradation voltages according to the first bit portion of the digital data. A first selection circuit that selects a first voltage and a second voltage different from the first voltage among a plurality of first interpolation voltages; and dividing the first voltage and the second voltage, A second voltage dividing circuit for generating a plurality of second interpolation voltages between the first voltage and the second voltage; and the first voltage and the second voltage in accordance with the second bit portion of the digital data. And a second selection circuit for selecting one of the plurality of second interpolation voltages. And a resistance value for selecting the first voltage and the second voltage of the first selection circuit is included in the resistance value for generating the second interpolation voltage of the second voltage dividing circuit. This is a drive circuit characterized by that.

In the present invention, the second voltage dividing circuit includes a plurality of resistors connected in series, and the resistance value when the first selection circuit and the second voltage of the first selection circuit are selected. Even if rON + r ′ = r, the relationship between rON, the resistance value r ′ of the two resistors at both ends of the series-connected resistors of the second voltage dividing circuit, and the resistance value r of the other resistors is rON + r ′ = r Good.
In the present invention, the drive circuit further includes a third impedance converter connected to the output of the second selection circuit. The operation will be described below.

  Digital data including the first bit portion and the second bit portion is supplied to the driving circuit. The first voltage dividing circuit divides a plurality of gradation voltages given from the outside to generate a plurality of first interpolation voltages between the plurality of gradation voltages. A plurality of gradation voltages supplied from the outside and a plurality of first interpolation voltages generated by the first voltage dividing circuit are supplied to the first selection circuit. The first selection circuit selects a first voltage and a second voltage from among the plurality of gradation voltages and the plurality of first interpolation voltages according to the first bit portion of the digital data. Here, the first voltage and the second voltage are different from each other. The first voltage and the second voltage are supplied to the second voltage dividing circuit. The second voltage dividing circuit generates a plurality of second interpolation voltages between the first voltage and the second voltage by dividing the first voltage and the second voltage. The first voltage, the second voltage, and the plurality of second interpolation voltages generated by the second voltage dividing circuit are supplied to the second selection circuit. The second selection circuit selects at least one of the first voltage, the second voltage, and the plurality of second interpolation voltages according to the second bit portion of the digital data. The voltage selected by the second selection circuit corresponds to one of a plurality of gradations displayed on the display device, and is output to the data line of the display device. In this way, the gradation corresponding to the value of the digital data is displayed on the display device.

  When the drive circuit further includes an impedance converter connected to the output of the second selection circuit, the magnitude of the current branched from the second voltage divider circuit to the impedance converter is the resistance in the second voltage divider circuit. Is negligibly small compared to the current flowing through Thereby, accurate voltage division by the second voltage dividing circuit is realized.

  According to the present invention, it is possible to realize a high-gradation driver such as an 8-bit digital driver. Needless to say, the present invention can also be applied to digital drivers other than 8-bit, for example, 6-bit digital drivers. In this case, for example, it is conceivable to load the upper 3 bits of the digital data to the voltage dividing circuit 10 and to load the lower 8 bits to the voltage dividing circuit 42 in each output circuit 33. Of course, it goes without saying that various modifications can be made including the case of 8 bits.

  Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1)
FIG. 1 shows the configuration of an 8-bit digital driver 1 according to the present invention. The driver 1 includes a voltage dividing circuit 10 and n drive circuits 20-1 to 20-n. Here, n is a positive integer.

  The voltage dividing circuit 10 generates 24 interpolation voltages by dividing the 9 gradation voltages V0, V32, V64,..., V224, V256 given from the outside. The voltage dividing circuit 10 outputs a total of 33 voltages V0, V8, V16,..., V248, V256 including the gradation voltage and the interpolation voltage. Hereinafter, in this specification, nine gradation voltages are represented as V32i (i = 0, 1, 2,..., 8), and 33 voltages output from the voltage dividing circuit 10 are represented as V8i (i. = 0, 1, 2, ..., 32).

  In the example shown in FIG. 1, the voltage dividing circuit 10 is provided in common to the n drive circuits 20-1 to 20-n. Such a configuration is preferable in that the circuit scale is reduced by sharing the circuit. However, the present invention is not limited to such a configuration. A separate voltage dividing circuit may be provided for each of the n drive circuits 20-1 to 20-n.

  Each of the drive circuits 20-1 to 20-n is based on the voltage V8i (i = 0, 1, 2,..., 32) supplied from the voltage dividing circuit 10 and outputs an output voltage Out corresponding to the digital data. Is output to a data line (not shown). For example, when the digital data consists of 8 bits, 2 8 (= 256) types of output voltages Out are output. During one output period defined by the output pulse OP, the data line is connected to a picture element (not shown), and the picture element is charged based on the output voltage Out. In this way, display of 2 8 (= 256) gradations is realized.

  FIG. 2A shows a configuration of the voltage dividing circuit 10 shown in FIG. Nine gradation voltages V32i (i = 0, 2,..., 8) are input to the voltage dividing circuit 10. The voltage dividing circuit 10 has four resistors R between two adjacent gradation voltages among the gradation voltages V32i (i = 0, 2,..., 8). The voltage dividing circuit 10 divides the gradation voltage V32i (i = 0, 2,..., 8) by these resistors R, thereby generating 24 interpolation voltages. In this way, the voltage dividing circuit 10 outputs a total of 33 voltages V8i (i = 0, 1, 2,..., 32) including the gradation voltage and the interpolation voltage. The total number of voltages including the gradation voltage and the interpolation voltage is designed to be smaller than ½ of the number of output voltages determined by the number of bits of digital data handled by the driver.

  FIG. 2B shows a resistor array between the gradation voltage V0 and the gradation voltage V32 shown in FIG. The same applies to the resistance arrangement between the other gradation voltages.

  FIG. 3A shows another configuration of the voltage dividing circuit 10. In the example shown in FIG. 3A, an impedance converter 11 is provided corresponding to each output from the voltage dividing circuit 10. The impedance converter 11 converts a high input impedance into a low output impedance. According to the impedance converter 11, the input voltage becomes the output voltage as it is, but almost no current flows into the input side, and a large current can be taken out from the output side. As the impedance converter 11, for example, a voltage follower is used.

  By providing the impedance converter 11, the voltage dividing circuit 10 can drive a large load. Therefore, when the voltage dividing circuit 10 is connected to the plurality of drive circuits 20-1 to 20-n, the voltage dividing circuit 10 preferably includes an impedance converter 11 corresponding to each output.

  FIG. 3B shows a resistor array between the gradation voltage V0 and the gradation voltage V32 shown in FIG. The same applies to the resistance arrangement between the other gradation voltages.

  FIG. 4 shows the configuration of the drive circuit 20-1 shown in FIG. The drive circuit 20-1 is a circuit corresponding to one output in the 8-bit digital driver.

  The drive circuit 20-1 includes a sampling storage unit 31, a holding storage unit 32, and an output circuit 33. In response to the rising edge of the sampling pulse Tsmp, 8-bit digital data D0 to D7 are stored in the sampling storage unit 31. In response to the rising edge of the output pulse OP, the digital data stored in the sampling storage unit 31 is transferred to the holding storage unit 32 where it is held. Based on the voltage V8i (i = 0, 1, 2,..., 32) supplied from the voltage dividing circuit 10, the output circuit 33 outputs corresponding to the value of the digital data held in the holding storage unit 32. The voltage Out is output.

  The configuration of the drive circuits 20-2 to 20-n shown in FIG. 1 is the same as the configuration of the drive circuit 20-1. Therefore, the description is omitted here.

  FIG. 5 shows the configuration of the output circuit 33 shown in FIG. The output circuit 33 includes a logic circuit 41, a voltage dividing circuit 42, a logic circuit 43, and an impedance converter 44.

  The logic circuit 41 receives the upper 5 bits of the 8-bit digital data and, based on the value of the upper 5 bits, any one of 32 control signals S0, S8, S16,. And any one of 32 control signals S8 ′, S16 ′, S24 ′,..., S256 ′ is made active.

  The control signals S0, S8, S16,..., S248 are supplied to analog switches (analog gates) ASW0, ASW8, ASW16,. The control signals S8 ', S16', S24 ', ..., S256' are supplied to analog switches (analog gates) ASW8 ', ASW16', ASW24 ', ..., ASW256', respectively. Each of these analog switches is configured to be turned on when an input control signal is active.

  The analog switches ASW0, ASW8, ASW16,..., ASW248 are supplied with voltages V0, V8, V16,. The analog switches ASW8 ', ASW16', ASW24 ', ..., ASW256' are supplied with voltages V8, V16, V24, ..., V256 from the voltage dividing circuit 10, respectively. Each of these analog switches is configured to output the input voltage as it is in the ON state.

  The voltage dividing circuit 42 includes eight resistors r connected in series. Each of the eight resistors r has an equivalent resistance value. The voltages output from the analog switches ASW0, ASW8, ASW16,..., ASW248 are applied to one end of eight resistors r connected in series. The voltages output from the analog switches ASW8 ', ASW16', ASW24 ', ..., ASW256' are applied to the other ends of the eight resistors r connected in series. The voltage dividing circuit 42 divides the voltages applied to both ends of the eight resistors r connected in series, thereby generating eight different voltages at the connection points P0, P1, P2,. generate. The voltage at the connection point P0 is equal to the voltage output from the analog switches ASW0, ASW8, ASW16,. The voltage at the connection points P1, P2,..., P7 is equal to the voltage divided according to the number of resistors r.

  The logic circuit 43 receives the lower 3 bits of the 8-bit digital data, and activates any one of the eight control signals t0 to t7 based on the value of the lower 3 bits.

  The control signals t0 to t7 are supplied to analog switches (analog gates) ASWt0 to ASWt7, respectively. Each of these analog switches is configured to be turned on when an input control signal is active.

  The eight voltages obtained by the voltage dividing circuit 42 are supplied to the analog switches ASWt0 to ASWt7, respectively. Each of these analog switches is configured to output the input voltage as it is in the ON state.

  In this way, according to the value of the lower 3 bits of the digital data, any one of the eight voltages obtained in the voltage dividing circuit 42 is selected by the logic circuit 43, and the selected voltage is subjected to impedance conversion. Is output to the device 44. The function and operation of the impedance converter 44 are the same as the function and operation of the impedance converter 11 described above. Therefore, the description is omitted here.

  The voltage at the connection points P1, P2,..., P7 of the voltage dividing circuit 42 is input to the impedance converter 44 having a very large input impedance via the analog switches ASWt0 to ASWt7. As a result, the magnitude of the current branched from the connection points P1, P2,..., P7 of the voltage dividing circuit 42 to the impedance converter 44 is larger than the magnitude of the current flowing through the resistor r in the voltage dividing circuit 42. Small enough to be ignored. Thereby, an accurate partial pressure is realized.

  If the load to be driven is small, the impedance converter 44 may be omitted.

  Table 1 shows the relationship between the values of the upper bits D7 to D3 of the digital data input to the logic circuit 41 and the values of the control signals S0, S8, S16, ..., S248 output from the logic circuit 42. It is a logical table that prescribes.

  Table 2 shows the relationship between the values of the upper bits D7 to D3 of the digital data input to the logic circuit 41 and the values of the control signals S8 ′, S16 ′, S24 ′..., S256 ′ output from the logic circuit 42. It is a logical table that prescribes the relationship.

論理回路４２は、表１および表２によって規定される論理に従って動作する。表１および表２において、空欄は制御信号の値が”０”であることを示す。制御信号の値が”０”（非能動）である場合にはアナログスイッチはオフ状態となり、制御信号の値が”１”（能動）である場合にはアナログスイッチはオン状態となる。

The logic circuit 42 operates according to the logic defined by Table 1 and Table 2. In Tables 1 and 2, a blank column indicates that the value of the control signal is “0”. When the value of the control signal is “0” (inactive), the analog switch is turned off, and when the value of the control signal is “1” (active), the analog switch is turned on.

  Table 3 is a logic table that defines the relationship between the values of the lower bits D2 to D0 of the digital data input to the logic circuit 43 and the values of the control signals t0 to t7 output from the logic circuit 43.

論理回路４３は、表３によって規定される論理に従って動作する。表３において、空欄は制御信号の値が”０”であることを示す。制御信号の値が”０”（非能動）である場合にはアナログスイッチはオフ状態となり、制御信号の値が”１”（能動）である場合にはアナログスイッチはオン状態となる。

The logic circuit 43 operates according to the logic defined by Table 3. In Table 3, a blank indicates that the value of the control signal is “0”. When the value of the control signal is “0” (inactive), the analog switch is turned off, and when the value of the control signal is “1” (active), the analog switch is turned on.

  The operation of the output circuit 33 when digital data D7 to D0 having a value 4 in decimal notation is input will be described below. In this case, (D7, D6, D5, D4, D3, D2, D1, D0) = (0, 0, 0, 0, 0, 1, 0, 0).

  The logic circuit 41 activates the control signal S0 according to the logic table shown in Table 1. This is because the values of the upper 5 bits D7 to D3 of the digital data are all "0". As a result, the voltage V0 is applied to one end of the voltage dividing circuit 42 via the analog switch ASW0.

  The logic circuit 41 activates the control signal S8 'according to the logic table shown in Table 2. This is because the values of the upper 5 bits D7 to D3 of the digital data are all "0". As a result, the voltage V8 is applied to the other end of the voltage dividing circuit 42 via the analog switch ASW8 '.

  The logic circuit 42 activates the control signal t4 according to the logic table shown in Table 3. This is because the values of the lower 3 bits D2 to D0 of the digital data are “1”, “0”, and “0”, respectively. As a result, the voltage at the connection point P4 of the voltage dividing circuit 42 is output to the impedance converter 44 via the analog switch ASWt4.

  The voltage at the connection point P4 of the voltage dividing circuit 42 is equal to (4V0 + 4V8) / 8 (= (V0 + V8) / 2). There are four resistors r connected in series between one end point of the voltage dividing circuit 42 to which the voltage V0 is applied and the connection point P4, and the other of the voltage dividing circuit 42 to which the voltage V8 is applied. This is because there are four resistors r connected in series between the end point and the connection point P4.

  In this way, the output circuit 33 outputs voltage (4V0 + 4V8) / 8 (= (V0 + V8) / 2) for digital data having a value of 4 in decimal notation.

  The logic circuit 41 may have any structure as long as it realizes the operations defined in Tables 1 and 2. For example, the logic circuit 41 may be realized by a combination of logic elements such as a logical product and a logical sum, or may be realized by a read only memory (ROM). The same applies to the logic circuit 42.

  Hereinafter, matters to be considered when the present invention is applied to an actual driver will be described.

  The first matter to be considered when the present invention is applied to an actual driver is the relationship between the value of the on-resistance rON of the analog switch and the value of the resistance r in the voltage dividing circuit 42 in the output circuit 33.

  FIG. 6 shows an equivalent circuit of the voltage dividing circuit 42 when the analog switches ASW0 and ASW8 'are in the ON state. A voltage V 0 is applied to one end of the voltage dividing circuit 42, and a voltage V 8 is applied to the other end of the voltage dividing circuit 42.

  In FIG. 6, rON represents the on-resistance of the analog switch. As described above, the ON resistance rON is further added to both ends of the eight resistances r included in the voltage dividing circuit 42. As a result, the voltage at the connection points P0 to P7 of the voltage dividing circuit 42 is not equal to the voltage obtained by dividing the voltage applied across the voltage dividing circuit 42 into eight equal parts.

  In order to make such a deviation as small as possible, it is preferable to make the on-resistance rON as small as possible compared to the resistance r. However, making the on-resistance rON much smaller than the resistance r (for example, 1/10 or less) causes a disadvantage of increasing the chip size.

  FIG. 7 shows a configuration of an output circuit 33 ′ including the voltage dividing circuit 52 improved from such a viewpoint.

  The voltage dividing circuit 52 includes eight resistors connected in series. Of the eight resistors, the value of two resistors r 'at both ends is r', which is different from the values r of the other resistors r. The value r 'is designed to satisfy the equation rON + r' = r.

  FIG. 8 shows an equivalent circuit of the voltage dividing circuit 52 when the analog switches ASW0 and ASW8 'are in the ON state. Since rON + r '= r, the voltage at the connection points P0 to P7 of the voltage dividing circuit 52 is equal to the voltage obtained by dividing the voltage applied to both ends of the voltage dividing circuit 52 into eight equal parts.

  In this case, the voltage at the connection point P0 of the voltage dividing circuit 52 is not used. This is because the voltage V0 applied to one end point of the voltage dividing circuit 52 and the voltage at the connection point P0 are not equal due to a voltage drop (or voltage rise) due to the on-resistance rON. For example, when rON = r ′, the voltage at the connection point P0 is (15V0 + V8) / 16.

  When the values of the lower 3 bits of the digital data are all “0”, the logic circuit 51 outputs the control signals S8 ′, S16 ′, S24 ′,..., S256 ′ regardless of the values of the upper 5 bits. All are inactive. As a result, the analog switches ASW8 ', ASW16', ASW24 ', ..., ASW256' are all turned off. As a result, the current loop from the logic circuit 51 to the logic circuit 51 via the analog switch ASW8i, the voltage dividing circuit 52, and the analog switch ASW8i '(or a current loop in the opposite direction) is cut off.

  The values of the control signals S8 ′, S16 ′, S24 ′,..., S256 ′ output from the logic circuit 51 are as shown in Table 2 except when the lower 3 bits of the digital data are all “0”. It is shown.

  The values of the control signals S0, S8, S16,..., S248 output from the logic circuit 51 are shown in Table 1 regardless of whether or not all the lower 3 bits of the digital data are “0”. It is as follows.

  Such control of the logic circuit 51 can be realized by adding logic when the values of the lower 3 bits of the digital data are all “0” to the logic tables shown in Tables 1 and 2.

  The logic circuit 53 activates any one of the control signals t1 to t7 when the values of the lower 3 bits of the digital data are all "0". The control signal that becomes active when the values of the lower 3 bits of the digital data are all “0” may be any of the control signals t1 to t7. This is because the voltages at the connection points P 1 to P 7 of the voltage dividing circuit 52 are all equal to the voltage applied to one end point of the voltage dividing circuit 52.

  When the values of the lower 3 bits of the digital data are all “0”, the current loop from the logic circuit 51 through the voltage dividing circuit 52 to the logic circuit 51 is interrupted as described above. Since no current flows through the on-resistance rON, the resistance r ', and the resistance r, no voltage drop (or voltage increase) occurs due to these resistances. Accordingly, the voltages at the connection points P 1 to P 7 of the voltage dividing circuit 52 are all equal to the voltage applied to one end point of the voltage dividing circuit 52.

  Table 4 is a logic table that defines the relationship between the values of the lower bits D2 to D0 of the digital data input to the logic circuit 53 and the values of the control signals t1 to t7 output from the logic circuit 53.

論理回路５３は、表４によって規定される論理に従って動作する。表４において、空欄は制御信号の値が”０”であることを示す。制御信号の値が”０”（非能動）である場合にはアナログスイッチはオフ状態となり、制御信号の値が”１”（能動）である場合にはアナログスイッチはオン状態となる。表４に示す例では、論理回路５３は、デジタルデータの下位３ビットの値がすべて”０”である場合には制御信号ｔ1を能動にする。

The logic circuit 53 operates according to the logic defined by Table 4. In Table 4, a blank indicates that the value of the control signal is “0”. When the value of the control signal is “0” (inactive), the analog switch is turned off, and when the value of the control signal is “1” (active), the analog switch is turned on. In the example shown in Table 4, the logic circuit 53 activates the control signal t1 when the values of the lower 3 bits of the digital data are all “0”.

  Thus, in the output circuit 33 ′ including the improved voltage dividing circuit 52, the analog switch ASW 0 becomes unnecessary. Therefore, the output circuit 33 'has an advantage that the number of analog switches can be reduced as compared with the output circuit 33 shown in FIG. Further, there is an advantage that the voltage fluctuation can be made zero when the values of the lower 3 bits of the digital data are all “0”. On the other hand, the output circuit 33 'is disadvantageous in that the number of logic gates is increased because the logic circuit 51 is slightly more complicated than the output circuit 33 shown in FIG. These advantages and disadvantages may be compared and determined to determine whether or not to use the output circuit 33 ′ instead of the output circuit 33.

  The second matter to be considered when the present invention is applied to an actual driver is the magnitude of the current that branches from the connection points P1, P2,..., P7 of the voltage dividing circuit 42 to the impedance converter 44. is there.

  In a transient state immediately after any one of the analog switches ASWt0 to ASWt7 is turned on, a current branched from the connection points P1, P2,..., P7 of the voltage dividing circuit 42 to the impedance converter 44 is present. It flows slightly. This is because charges for charging the input capacitance of the analog switch and the input capacitance of the impedance converter 44 are supplied.

  However, after reaching the steady state, depending on the structure of the analog switch, a leakage current generated inside the analog switch and a current based on the input impedance and the leakage current of the impedance converter 44 only flow. . These currents are generally orders of magnitude smaller than the current flowing through the resistor r in the voltage dividing circuit 42.

  Therefore, the value of the resistance r in the voltage dividing circuit 42 is preferably determined so that the above-described leakage current can be substantially ignored. For example, the value of such a resistance r is 1.25 Mohm. However, the value of the resistance r is not essential to the present invention. The value of resistance r is not limited to 1.25M ohms. Semiconductor design and manufacturing technology is making rapid progress. Therefore, it is meaningless to limit the value of the resistance r on the assumption of the current technology.

  Generally, when a current flows through a circuit in which a resistor exists, a voltage drop (or voltage rise) occurs. Therefore, in actually designing the driver, it is necessary to clearly distinguish between a circuit through which a current flows and a circuit through which no current flows. Furthermore, for a circuit through which a current flows, it is necessary to consider the influence of a voltage drop (or voltage rise) as necessary.

  A third matter to be considered when the present invention is applied to an actual driver is the ratio between the value of the resistor R in the dividing circuit 10 and the value of the resistor r in the output circuit 33.

  FIG. 9 shows an equivalent circuit of the driver 1 when all of the drive circuits 20-1 to 20-n output a voltage obtained by further dividing the voltage V0 and the voltage V8 output from the voltage dividing circuit 10. Indicates.

  In FIG. 9, R is the resistance in the voltage dividing circuit 10, r is the resistance in the voltage dividing circuit 42, r1 is the resistance of the line from the voltage dividing circuit 10 to the voltage dividing circuit 42 included in the drive circuit 20-1, and Δr is the drive. The resistance of the line between each voltage dividing circuit 42 included in the circuits 20-1 to 20-n is shown. Here, the value of the resistor r1 and the value of the resistor Δr are much smaller than the value of the resistor r and the value of the resistor R. Therefore, when considering the current branched from the connection point PV8 of the voltage dividing circuit 10, the value of the resistor r1 and the value of the resistor Δr may be ignored. When voltage V0> voltage V8, current flows into the connection point PV8 of the voltage dividing circuit 10, and when voltage V0 <voltage V8, current flows out of the voltage dividing circuit connection point PV8.

  When the value of the resistor r1 and the value of the resistor Δr are ignored, the equivalent circuit shown in FIG. 9 is transformed into the circuit shown in FIG. This is because n resistor arrays are connected in parallel. Each of the n resistor arrays includes eight resistors r connected in series.

  In addition, by providing the driver 1 with a plurality of voltage dividing circuits, it is possible to reduce the number of driving circuits corresponding to one output that one voltage dividing circuit bears. In this case, N may be used instead of n. Here, N is the number of driving circuits to which the voltage divided by the voltage dividing circuit 10 is supplied, and N ≦ n. In the following description, it is assumed that n = N.

  From the circuit shown in FIG. 10, the values of the resistance R and the resistance r are set so that R >> 8r / n, that is, nR / 8r >> 1 (ratio nR / 8r is sufficiently larger than 1). , It can be seen that the voltage fluctuation due to the current branched from each connection point of the voltage dividing circuit 10 can be substantially ignored. As the ratio nR / 8r approaches 1, the deviation generated in the voltage divided by the voltage dividing circuit 10 increases. Here, the condition that “all of the drive circuits 20-1 to 20-n output a voltage obtained by further dividing the voltage V0 and the voltage V8 output from the voltage dividing circuit 10” is a voltage dividing circuit. Note that this is the condition where the current branching from each of the 10 connection points is maximized.

  Assume r = 1.25 M ohms and n = 100. In this case, if R = 1K ohms, the ratio nR / 8r = 100, and the ratio nR / 8r >> 1 is established. Therefore, the voltage fluctuation due to the current branched from each connection point of the voltage dividing circuit 10 can be ignored. In practice, the ratio nR / 8r is rarely required to be 100. However, the ratio nR / 8r is preferably greater than about 10.

  A fourth matter to be considered when the present invention is applied to an actual driver is the influence of line resistance from the voltage dividing circuit 10 to each of the driving circuits 20-1 to 20-n.

  Assume that r = 1.25 Mohm, | V0−V8 | is 0.1 V, and n = 100. In this case, the maximum current flowing through the line is 0.1 / (10 M / 100) = 10 −6 A. When it is desired to keep the output deviation based on the resistance of the line within 0.01V, the resistance of the line is determined not to exceed 0.01/10@-6 = 10 @ 4 .OMEGA. Note that the maximum current described above actually flows only in the line portion (the resistance portion r1 in FIG. 9) from the voltage dividing circuit 10 to the drive circuit 20-1, and the subsequent lines are connected to each drive circuit. It gradually decreases by the amount of current that branches. Therefore, the actual resistance condition of the line may be slightly looser than the above-described condition. However, calculating the line resistance under the above-described conditions is very effective in estimating the line resistance.

(Embodiment 2)
FIG. 11 shows another configuration of the output circuit 33. In FIG. 11, the same components as those shown in FIG. 5 are denoted by the same reference numerals, and the description thereof is omitted.

  In the example shown in FIG. 11, the voltage selected according to the value of the upper 5 bits of the digital data is input to the voltage dividing circuit 42 via the impedance converters 61 and 62. The input impedances of the impedance converters 61 and 62 are sufficiently large, and the output impedance is small enough to allow a current determined by the voltage difference in the open state of the selected voltage and the resistance r in the voltage dividing circuit 42 to flow sufficiently.

  For example, it is assumed that the value of the resistance r is 1.25 KΩ and the potential difference between the selected voltages is 0.1V. In this case, the current flowing through the resistor r connected in series in the voltage dividing circuit 42 is 0.1 / (1.25 × 8) = 0.01 mA. The output impedances of the impedance converters 61 and 62 are sufficiently small so that even if a current of 0.01 mA is output, voltage fluctuation does not substantially occur. For example, if the output impedance is 100Ω, the voltage fluctuation is 1 mV or less. The voltage variation of 1 mV or less is generally within a sufficiently negligible range.

  The output impedances of the impedance converters 61 and 62 are defined for both positive and negative currents. That is, the output sides of the impedance converters 61 and 62 are configured so that, in this example, a current of 0.01 mA can be flowed in or out with a voltage fluctuation of 1 mV or less. The magnitude of the input impedance of the impedance converters 61 and 62 is such that the current flowing into the impedance converter is sufficiently small, and the total amount of current flowing into the corresponding impedance converter of all the output circuits is the voltage drop (or voltage rise) and the amount applied to the line. The influence of the branch current on the connection point of the voltage circuit 10 is sufficiently large to be a negligible value. Note that the discussion of the value is omitted because it can be performed essentially in the same way as the discussion described in the previous example.

  When the voltage at the output terminal of the impedance conversion circuit 61 is larger than the voltage at the output terminal of the impedance conversion circuit 62, a current of 0.01 mA flows out from the impedance conversion circuit 61 and passes through the voltage dividing circuit 42 to the impedance conversion circuit 62. Flows in. The voltage difference between the impedance conversion circuit 61 and the impedance conversion circuit 62 is divided by the voltage dividing circuit 42. A voltage selected by the logic circuit 43 among the voltages at the points P 0 to P 7 in the voltage dividing circuit 42 is output via the impedance converter 44.

  The current flowing through the voltage dividing circuit 42 flows from the higher voltage to the lower voltage of the impedance conversion circuits 61 and 62. If the equivalent function described above can be realized as a result, the impedance conversion circuit 61 and 62 may be any form of active device. The advantage of the second embodiment is that the value of the resistance r in the voltage dividing circuit 42 can be determined relatively freely.

  Variation in the value of the resistance r in the voltage dividing circuit 42 generates a deviation of the divided voltage. Accordingly, there is a correlation between the accuracy and the resistance value depending on equipment such as a process for mass-producing the driver. If this value is forcibly designed to be large, variation in the value of the resistance r in the voltage dividing circuit 42 becomes large depending on mass production equipment. In the second embodiment, the driver can be designed without being relatively restricted by such a thing.

  However, providing the impedance conversion circuits 61 and 62 is not always advantageous as compared to not providing the impedance conversion circuits 61 and 62. This is because the provision of the impedance conversion circuits 61 and 62 may cause an additional burden on design or mass production. Whether or not to provide the impedance converters 61 and 62 may be determined in accordance with the specifications of the driver, the factory equipment to be mass-produced, the characteristic measuring equipment, and the like.

(Embodiment 3)
FIG. 12 shows another configuration of the output circuit 33. In FIG. 12, the same components as those shown in FIG. 11 are denoted by the same reference numerals, and the description thereof is omitted.

  The output circuit 33 shown in FIG. 12 is different from the output circuit 33 shown in FIG. 11 in that the impedance converter 44 is omitted. Further, as the output characteristics of the impedance converters 71 and 72, the output current capacity is large enough to charge (discharge) the data line of the display body which is a load. However, the output impedance itself of the impedance converters 71 and 72 does not change from the condition described in the second embodiment. That is, it is not necessary to make the output impedance unnecessarily small.

  FIG. 13 shows an equivalent circuit of data lines. When a voltage is applied to a load represented by such an equivalent circuit, no current flows from the driver after a sufficient time has elapsed. This is because the system is brought into a steady state by sufficiently charging the load capacity.

  For example, consider the case in FIG. 12 where the control signal t2 output from the logic circuit 43 is active and the corresponding analog switch ASWt2 is in the ON state. In this case, when the voltage at the connection point Pt2 in the voltage dividing circuit 42 becomes equal to the voltage at the point P in FIG. 13, the system is in a steady state, and the current branched from the connection point Pt2 in the voltage dividing circuit 42 to the output side is no longer substantial. Therefore, it becomes 0. Therefore, the voltage at the connection point Pt2 in the voltage dividing circuit 42 (that is, the voltage of the load) is a voltage accurately divided by the voltage dividing circuit 42.

  The impedance converters 71 and 72 are required to have an ability to supply a charge sufficient to sufficiently charge the load within a predetermined period. The predetermined period is, for example, one output period (generally, a period in which the driver outputs a value for one data).

  In the transient state, the impedance converters 71 and 72 may cause voltage fluctuation. What is important is that the impedance converters 71 and 72 have a charge supply capability (absorption capability) sufficient to reach the steady state within a predetermined period, and when the system reaches the steady state. The same condition as described in the second embodiment is satisfied, and the fluctuation of the output voltage is minimized.

(Embodiment 4)
FIG. 14 shows another configuration of the output circuit 33. In FIG. 14, the same components as those shown in FIG. 5 are denoted by the same reference numerals, and the description thereof is omitted.

  In the example shown in FIG. 14, the voltage dividing circuit 82 includes a capacitor c connected in series instead of the resistor r connected in series. After the charge of each capacitor c of the voltage dividing circuit 82 becomes stable according to the voltage applied to both ends of the voltage dividing circuit 82, no current flows through the voltage dividing circuit 82 except for leakage current. As a result, unlike the case where the voltage dividing circuit 82 includes the resistor r connected in series, voltage fluctuation due to current flow does not occur. However, the capacitance of each part, such as the input capacitance component of the analog switch, disperses the charge and causes voltage fluctuations, so care must be taken in designing.

  Further, instead of configuring the voltage dividing circuit 10 by the resistor R connected in series, the voltage dividing circuit 10 may be configured by a capacitor C connected in series. Note that the relationship between the capacitance values when a capacitor is used for the voltage dividing circuit 10 can be determined by the same consideration as in the case where the resistor is used.

  An advantage of using a capacitor in the voltage dividing circuit is that no through current flows when a resistor is used in the voltage dividing circuit. However, when the waveform of the gradation voltage is rectangular, the capacity is charged / discharged.

  Therefore, whether it is more advantageous to use a capacitor or a resistor is evaluated by subtraction between an increase in power consumption for charging / discharging and a reduction in power consumption due to no through current flowing.

  In the above description, the description has been made on the assumption that the active matrix type liquid crystal display device is driven. However, the present invention itself is not necessarily limited to the driving circuit of the active matrix type liquid crystal display device. It goes without saying that the present invention is effective for all display devices that perform gradation display by changing the voltage applied to the pixel in accordance with the data.

It is a figure which shows the structure of the 8-bit digital driver 1 by this invention. (A) is a figure which shows the structure of the voltage dividing circuit 10 shown by FIG. 1, (b) is a figure which shows a part of structure of the voltage dividing circuit 10. FIG. (A) is a figure which shows the other structure of the voltage dividing circuit 10 shown by FIG. 1, (b) is a figure which shows a part of other structure of the voltage dividing circuit 10. FIG. It is a figure which shows the structure of the drive circuit 20-1 shown by FIG. FIG. 5 is a diagram showing a configuration of an output circuit 33 shown in FIG. 4. 3 is a diagram showing an equivalent circuit of a voltage dividing circuit 42. FIG. FIG. 6 is a diagram showing a configuration of an output circuit 33 ′ including an improved voltage dividing circuit 52. 3 is a diagram showing an equivalent circuit of a voltage dividing circuit 52. FIG. FIG. 3 is a diagram showing an equivalent circuit of the driver 1. It is a figure which shows the circuit which deform | transformed the equivalent circuit shown by FIG. 6 is a diagram illustrating another configuration of the output circuit 33. FIG. 6 is a diagram illustrating another configuration of the output circuit 33. FIG. It is a figure which shows the equivalent circuit as a load of the data line of a display body. 6 is a diagram illustrating another configuration of the output circuit 33. FIG. It is a figure which shows the structure of the drive circuit in the conventional 3 bit digital driver. It is a figure which shows the structure of the conventional output circuit 133. FIG. It is a figure which shows the structure of the drive circuit and voltage dividing circuit in the conventional 4-bit digital driver. (A) is a figure which shows the structure of the voltage dividing circuit in a 6-bit digital driver, (b) is a figure which shows a part of structure of a voltage dividing circuit. It is a figure which shows the structure of the drive circuit in a 6-bit digital driver. FIG. 20 is a diagram showing a configuration of an output circuit shown in FIG. 19. (A) is a figure which shows the structure of the voltage dividing circuit in an 8-bit digital driver, (b) is a figure which shows a part of structure of a voltage dividing circuit. It is a figure which shows the structure of the drive circuit in an 8-bit digital driver. FIG. 23 is a diagram showing a configuration of an output circuit shown in FIG. 22.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Driver 10 Voltage divider circuit 11 Impedance converter 20-1-20-n Drive circuit 31 Sampling memory | storage part 32 Holding | maintenance memory | storage part 33 Output circuit 41 Logic circuit 42 Voltage divider circuit 43 Logic circuit 44 Impedance converter 51 Logic circuit 52 Voltage divider circuit 53 Logic circuit 54 Impedance converter 61, 62 Impedance converter 71, 72 Impedance converter 82 Voltage divider circuit

Claims (4)

A driving circuit for a display device that displays a plurality of gradations according to digital data including a first bit portion and a second bit portion,
A first voltage dividing circuit that generates a plurality of first interpolation voltages between the plurality of gradation voltages by dividing a plurality of gradation voltages applied from the outside;
A first voltage for selecting a first voltage and a second voltage different from the first voltage from the plurality of gradation voltages and the plurality of first interpolation voltages according to the first bit portion of the digital data. A selection circuit;
A second voltage dividing circuit that generates a plurality of second interpolation voltages between the first voltage and the second voltage by dividing the first voltage and the second voltage;
A second selection circuit for selecting at least one of the first voltage, the second voltage, and the plurality of second interpolation voltages according to the second bit portion of the digital data;
A first impedance converter for receiving the first voltage;
A second impedance converter for receiving the second voltage,
The second voltage dividing circuit divides the output of the first impedance converter and the output of the second impedance converter, thereby providing an output of the first impedance converter and an output of the second impedance converter. The plurality of second interpolation voltages are generated during the period, and the first impedance converter and the second impedance converter allow the voltage value of the output load of the second selection circuit to reach a steady state within one output period. A drive circuit comprising: A driving circuit for a display device that displays a plurality of gradations according to digital data including a first bit portion and a second bit portion,
A first voltage dividing circuit that generates a plurality of first interpolation voltages between the plurality of gradation voltages by dividing a plurality of gradation voltages applied from the outside;
A first voltage for selecting a first voltage and a second voltage different from the first voltage from the plurality of gradation voltages and the plurality of first interpolation voltages according to the first bit portion of the digital data. A selection circuit;
A second voltage dividing circuit that generates a plurality of second interpolation voltages between the first voltage and the second voltage by dividing the first voltage and the second voltage;
A second selection circuit that selects at least one of the first voltage, the second voltage, and the plurality of second interpolation voltages in accordance with the second bit portion of the digital data. And
The resistance value when the first selection circuit selects the first voltage and the second voltage is included in the resistance value for generating the second interpolation voltage of the second voltage dividing circuit. Drive circuit. The second voltage dividing circuit includes a plurality of resistors connected in series,
A resistance value rON for selecting the first voltage and the second voltage of the first selection circuit, and a resistance value r ′ of two resistances at both ends of the series connection resistance of the second voltage dividing circuit The drive circuit according to claim 2, wherein the relationship between the resistance value r and the resistance value r of other resistors is rON + r ′ = r. The drive circuit according to claim 1, wherein the drive circuit further includes a third impedance converter connected to an output of the second selection circuit.

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