JP2001188615A - Voltage supply device, and semiconductor device using the voltage supply device, electro-optical device and electronic equipment lising the semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a voltage supply device capable of highly accurately and quickly obtaining necessary charging voltage without requiring any offset cancel circuit. SOLUTION: The voltage supply device supplies voltage to a load capacitor to charge the load capacitor with prescribed voltage within a prescribed charging period. The voltage supply device is provided with a DAC 70, a voltage follower circuit 72 for converting voltage from the DAC 70 into impedance and outputting the impedance to a 1st switching element Q1 connected between the circuit 72 and the load capacitor, a by-pass line 205 for supplying the voltage from the DAC 70 directly to the load capacitor without passing the circuit 72 and the element Q1, and a 2nd switching element Q2 connected to the way of the by-pass line 205. In the first half period of the charging period, voltage output is switched to an output only from the circuit 72 by turning on the element Q1 and turning of the element Q2, and in the latter half period, the voltage output is switched to an output only from the DAC 70 by turning off the element Q1 and turning on the element Q2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device using a voltage supply device, and an electro-optical device and an electronic apparatus using the same.

[0002]

2. Description of the Related Art At present, devices requiring a high-precision supply voltage include, for example, liquid crystal display devices.

In an active matrix type liquid crystal display device or a simple matrix type liquid crystal display device, a liquid crystal panel has a multi-gradation (multi-color) and an applied voltage with higher precision.

In order to increase the number of gradations of a liquid crystal panel, for example, an active matrix type liquid crystal display device such as a TFT (T
In a thin film transistor (LCD) liquid crystal device, each data of RGB (red, green, and blue) data signals is, for example, 6-bit data (64 gradation display, approximately 260,000 colors) or 8-bit data (256 gradation display). , About 167
70,000 colors).

[0005] Further, with the increase in the number of gray scales described above, a multi-step voltage level is required in proportion to the gray scale. Therefore, a technique for setting each voltage level with higher accuracy is required.

According to the characteristics of the applied voltage-panel transmittance in the liquid crystal panel, at an intermediate level where the transmittance is close to 50%, the change in the panel transmittance with respect to the applied voltage is large, and the panel transmittance becomes 100% or 0%. As the distance approaches, the change in panel transmittance with respect to the applied voltage decreases. Therefore, when the panel transmittance is at an intermediate level, a gradation change due to a slight deviation of the applied voltage is particularly remarkable. In order to suppress the shift of the panel transmittance, it is required to supply a liquid crystal application voltage with higher accuracy.

The allowable value of the variation in the applied voltage of the liquid crystal is, for example, ± 5 mV for 256 gradation display, 256
In the case of gradation display, the voltage is ± 1 to 2 mV. As the display becomes multi-gradation, more accurate liquid crystal application voltage is required. Threshold voltage V in general IC chip
In contrast to the variation of TH having an allowable range of several tens mV to several hundred mV, the allowable range must be set more strictly in a liquid crystal display device that performs multi-tone display. Also,
It is expected that a method for adjusting the voltage applied to the liquid crystal with higher precision will be required even in the future with further increase in the number of gradations.

In view of such circumstances, conventionally, for example, a method of generating a plurality of gradation generation voltages in a driving circuit of a liquid crystal panel has been based on a voltage selection method, a time division method, a digital-analog conversion method, or the like. Voltage generation methods are known.

FIG. 4 shows a conventional voltage supply apparatus of the type using a digital-to-analog converter (hereinafter referred to as a DAC type).
Shown in

The voltage follower circuit 72 to which the output from the DAC 70 is input functions as an impedance converter. In the case of the ideal voltage follower circuit 72, the voltage of the node 201 input to the non-inverting input terminal is equal to the inverting input voltage. It becomes equal to the voltage of the node 202 input to the terminal. However, conventionally, in the operation of the voltage follower circuit 72 which has not been corrected by the offset cancel circuit, an offset occurs between the input and the output mainly due to a variation in the performance of each transistor. Will be different.

FIG. 4 shows a voltage supply device for solving the above-mentioned problem. The output from the DAC 70 is supplied to the non-inverting input terminal 201 of the voltage follower circuit 72, and the voltage follower circuit 72 is supplied to the inverting input terminal 202.
Is fed back. A switching element Q10, a capacitor C10, and a switching element Q12 are connected in series along a line connecting the output line of the voltage follower circuit 72 and the non-inverting input terminal 201. Inverting input terminal 202
In the middle of the negative feedback line connected to the switching element Q1
Only exists. The switching element Q10 is connected in parallel to the capacitor C10 and the switching element Q11.

In the first period, the switching element Q11 turns off, and the switching element Q10 and the switching element Q
12 is turned on, the voltage follower circuit 7
The offset voltage between the input and output of No. 2 is charged in the capacitor C10. During the second period, the switching element Q11 is turned on, and the switching element Q10 and the switching element Q1 are turned on.
When 2 is turned off, the charge of the offset cancellation charged in the capacitor C10 is superimposed on the inverting input terminal 202 of the voltage follower circuit 72 and fed back.

As described above, the voltage follower circuit 72
In the middle of the wiring connecting the output line and the non-inverting input terminal 201,
A method has been adopted in which a capacitor C10 for offset cancellation is provided and a reverse voltage for the offset is applied to offset the offset.

[0014]

In the data driver of the conventional DAC system shown in FIG. 4, it is necessary to incorporate the capacitor C10 into the chip as an offset canceling circuit. However, a large area is required because a capacitance C10 that is sufficiently larger than the input capacitance of the voltage follower circuit 72 is required. If the offset cancel capacitance is too small, the input capacitance in the voltage follower circuit 72 is regarded as noise, and the noise is superimposed on the output voltage.

In order to charge the offset voltage to the offset canceling capacitor C10, it usually takes 3 to 5 μs.
It takes some time.

In this type of active matrix type liquid crystal device, if the number of pixels in one line is increased to perform high-definition display, one horizontal scanning period (selection period) must be set short. For example, in the SXGA high-definition display, the selection period is as short as 8 to 12 μs.

In this case, if the period for charging the offset canceling capacitor C10 is occupied during the selection period, it becomes difficult to secure a time for offset canceling.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to obtain a required charging voltage with high accuracy and speed without the need for an offset canceling circuit. An object of the present invention is to provide a voltage supply device and a semiconductor device, an electro-optical device, and an electronic device using the same.

[0019]

A voltage supply device according to one aspect of the present invention supplies a voltage to a load capacitance and charges the load capacitance with a predetermined voltage within a predetermined charging period. The voltage supply device includes a voltage supply source, an impedance conversion circuit that converts a voltage from the voltage supply source into impedance and outputs the voltage, and a first switching element connected between the impedance conversion circuit and the load capacitance. A bypass line that supplies a voltage from the voltage supply source to the load capacitance without passing through the impedance conversion circuit and the first switching element; and a second switching element connected in the middle of the bypass line. And Then, the first switching element is turned on and the second switching element is turned off in the first half period of the charging period, and the first switching element is turned off in the second half period of the charging time, and the second switching element is turned on. Is turned on.

According to the present invention, the output voltage from the impedance conversion circuit is supplied to the load capacitance via the first switching element during the first half of the charging period. At this time, if there is an offset between the input voltage and the output voltage of the impedance conversion circuit, the predetermined voltage is not charged to the load capacitance even if the output voltage from the impedance conversion circuit is continuously supplied to the load capacitance. .

Therefore, in the latter half of the charging period, the voltage supply path is switched to the bypass path, and the voltage from the voltage output source is directly supplied to the load capacitance without passing through the impedance conversion circuit. For this reason, the voltage that was insufficient for the offset is supplied to the load capacity and supplied, and charging can be performed to a predetermined voltage. Note that the amount of charge per unit time supplied from the voltage output source to the load capacitance is reduced because the impedance is not converted.
However, if the load capacity is charged to a sufficient voltage by the output voltage from the impedance conversion circuit, it becomes possible to charge the load capacity to a predetermined voltage within the charging period.

Further, according to the present invention, since the offset canceling capacity used in the prior art is not required,
That area is not required, and the time for charging the offset canceling capacitor with the offset voltage is not required.

In the present invention, it is preferable that a period in which the first switching element and the second switching element are both turned off is set. In this case,
The voltage from the voltage output source via the bypass line can be prevented from being positively fed back to the impedance conversion circuit.

In the present invention, it is preferable to further provide a third switching element connected to a power supply line for supplying a power supply voltage to the impedance conversion circuit. This third
Are turned off in synchronization with the off operation of the first switching element. With this configuration, when the output of the impedance conversion circuit is unnecessary, power supply to the output can be cut off, and power consumption can be reduced.

The impedance conversion circuit used in the present invention can be constituted by a voltage follower circuit. The power supply potential supplied to this voltage follower circuit is set to VDD, and the ground potential is set to VEE. When an input voltage close to the power supply potential VDD or a voltage close to the ground potential VEE is input, this type of voltage follower circuit sets the input voltage to On the other hand, there is a type in which the output voltage does not show a linear characteristic and has a characteristic in which the output voltage is saturated. In this case, in the saturation region of the output voltage of the voltage follower circuit, the first switching element is turned off, the second switching element is turned on, and the voltage of the voltage output source is supplied to the load capacitance via the bypass line. Is preferred. With this configuration, in the voltage follower circuit, in a saturation region where the output voltage is saturated with respect to a low input voltage or a high input voltage, a linear output voltage can be supplied by directly outputting the voltage from the voltage output source. Will be.

In order to generate a linear output voltage while using the voltage follower circuit as described above, it is preferable to have a comparator for comparing the output voltage of the voltage output source with the output voltage of the voltage follower circuit. Based on the comparison result of the comparator, the states of the first and second switching elements can be controlled, and the voltage of the voltage output source can be output instead of the saturation voltage.

Another embodiment of the present invention defines a semiconductor device having the above-described voltage supply device. Since this semiconductor device does not require a capacitor for offset cancellation,
Either the chip size can be reduced by the area, or high integration can be achieved by integrating other elements in the area.

Still another aspect of the present invention is an electro-optical device having a semiconductor device on which the above-described voltage supply device is mounted, and a display unit using an electro-optical element. Are used as drive ICs for driving.
By supplying the voltage output from the voltage supply device to the electro-optical element via the signal line of the display unit, an accurate drive voltage can be supplied to the electro-optical element.

In this case, the electro-optical element may be driven in gray scale based on a stepwise voltage from a voltage supply device. At this time, the voltage output source can be configured by a DA converter that converts a digital gray scale signal into an analog voltage. In such a case, a voltage within a voltage range corresponding to (LSB) / 2 with respect to a desired gradation voltage value to be supplied to the electro-optical element, and a desired gradation voltage value of 9
It is preferable that the first half of the charging period be ended after the voltage of 0% or more has been charged to the load capacity. If the above-described sufficient voltage is supplied to the electro-optical element in the first half period, the voltage applied to the electro-optical element can be controlled even if the voltage from the DA converter is directly supplied to the load capacitor in the second half period. , And it is also possible to prevent the gradation in the electro-optical element from being different.

According to still another aspect of the present invention, an electronic apparatus having the above-described electro-optical device is defined. If this electro-optical device is used as a display unit of an electronic apparatus, image quality can be improved.

[0031]

Embodiments of the present invention will be described below with reference to the drawings.

<First Embodiment> (Explanation of Liquid Crystal Device) FIG. 1 shows an overall configuration diagram including a liquid crystal panel device and its peripheral circuits.

In FIG. 1, the liquid crystal panel 20 is, for example, a TFT type liquid crystal panel.

As circuits for driving the liquid crystal panel 20, a gate driver IC 40 (scanning line driver IC) connected to an address line (scanning line) and a data driver IC 30 (signal line) connected to a data line (signal line) are provided. Driver IC). The gate driver IC 40 and the data driver IC 30 include a power supply circuit 46.
And a signal control circuit 4
The data line 21 and the gate line 22 are driven based on the signal supplied from the second line 2. Actually, both the data driver IC 30 and the gate driver IC 40 have a plurality of ICs.
It consists of. Further, the gradation voltage circuit section 44 supplies a reference voltage required for gradation driving in the data driver IC 30. The liquid crystal capacitance 25 is formed by sealing liquid crystal between the pixel electrode 24 and the common electrode 23. The common electrode drive circuit 48 supplies a common voltage to the common electrode 23.

The present invention is not limited to the one applied to the TFT type liquid crystal panel, but can be applied to other display panels using an electro-optical element containing a liquid crystal.

(Description of Data Line Driving Circuit) FIG. 2 shows a data driver IC 3 for driving the liquid crystal panel 20 of FIG.
FIG. 3 shows a configuration diagram of the liquid crystal panel 20 of FIG.
An example of a driving waveform for driving the middle data line 21 is shown.

FIG. 2 shows that the data line output 21 is, for example, 3
FIG. 2 shows an internal block diagram of a data driver IC 30 for three colors and 64 gradations having 00 output lines.

The data driver IC 30 shown in FIG. 2 sequentially converts the 6-bit display data of the RGB signals supplied from the signal control circuit 42 based on the timing of the clock signal φ1 similarly supplied from the signal control circuit 42. , Are latched by the input latch circuit 50. Display data of the clock signal φ1 for 100 clocks (RGB × 6 bits × 10
The signal for 0 clock) is taken into the line latch circuit 52 via the shift register 51 of 100 bits. Further, the display data is taken into the latch circuit 53 at the timing of the latch pulse LP. Then, the display data of the latch circuit 53 is converted into an analog signal by the 6-bit DAC 54, impedance-converted by the voltage follower circuit 55, and supplied to the data line 21 of the liquid crystal panel 20.

Here, as shown in FIG. 3, a 6-bit D
The AC 54 generates a 64-level grayscale voltage, and for example, 10-level voltages V1 to V10 are supplied from the outside. The reference voltages V1 to V10 are supplied to the gradation voltage circuit section 44.
Supplied from In the DAC 54, for example, each of RGB 6
The upper 3 bits of the bit display data, 1
One of the voltage ranges divided by the 0-level reference voltages V1 to V10 is selected. For example, the reference voltage V4
And V5. Next, a range of a certain voltage specified by the upper three-bit data, for example, a V34 level which is one of eight voltage levels between V4 and V5 levels is selected based on the lower three-bit data.

(Regarding Voltage Supply Apparatus) FIG.
FIG. 7 is a circuit diagram of a voltage supply device 58 that outputs an output from the TFT 70 to a data line of a TFT type liquid crystal panel via a voltage follower circuit 72.

The DAC 70 shown in FIG. 5 is connected to one data line 21, and the DA converter 54 shown in FIG. Voltage follower circuit 72 and voltage follower circuit 55
The relationship is the same.

In the circuit of FIG. 5, the output from the DAC 70 is supplied to the non-inverting input terminal 201 of the voltage follower circuit 72, and the output of the voltage follower circuit 72 is supplied to the inverting input terminal 202 by feedback. The voltage follower circuit 72 and the load capacitance (the wiring capacitance of the data line 21,
A first switching element Q1 is provided on the output line between the first switching element Q1 and the liquid crystal capacitor 25). The voltage from the DAC 70 is supplied to the voltage follower circuit 72 and the first
The second switching element Q2 is connected to the bypass line 205 that supplies the load capacitance without passing through the switching element Q1.

A control signal is supplied to the second switching element Q2 from the first control signal generation circuit 74, and the second switching element Q2 is on / off controlled. The inverter INV1 is connected to the first switching element Q1, and the output from the first control signal generation circuit 74 is inverted and supplied, so that the first switching element Q1 is on / off controlled. This control signal is, for example, as shown in FIG.
As shown in (b), the signal CNT1 is output based on the timing synchronized with the data latch pulse LP.

FIG. 6A shows a waveform diagram of a latch pulse LP used for voltage supply by the conventional DAC system, supply voltages VX1 and VX2 to the gate line, and an output voltage to the data line. In one frame period, the gate line 22
The voltage waveform charged to the liquid crystal capacitor 25 via the data line 21 during the selection period is as shown by the output VY1.

As for the voltage applied to the data line 21, a more accurate voltage is required as the number of gradations and the number of colors of the liquid crystal panel are increased. However, as shown in FIG. 6A, the voltage output via the voltage follower circuit is affected by the variation of the input / output voltage due to the offset.
Since the required gradation potential is not reached, it is often difficult to set a high-precision gradation potential.

That is, as shown in FIG. 6A, the liquid crystal capacitor 25 is charged with a potential which does not reach the gradation potential during the selection period t and is insufficient by δ potential. Although the input / output change due to the offset can be corrected by providing the offset canceling circuit as shown in FIG. 4, there is a problem in that the area of the capacitor C10 for that purpose is enlarged, and the speed at which the required gradation potential is reached is obtained. Was.

Therefore, in the present embodiment, attention is paid to the limit of the output capability of the voltage follower circuit, and when the gradation potential output is maintained to some extent, the output from the DAC 70 is replaced with the liquid crystal output instead of the output of the voltage follower circuit. Capacity 2
5 has been switched.

Referring to FIG. 6B, the operation of the data driver of the TFT type liquid crystal panel device according to the present embodiment will be described with reference to FIG.

The output of the voltage follower circuit 72 of the TFT type liquid crystal device using the DAC system is amplified to more than 99% of a required voltage value, although it is not constant in the specification, but it takes almost half of the selection period. Is required. For example,
In a liquid crystal driver requiring 12 V, an electric charge of Q = 12 × C (C is a load capacitance) must be charged by the output of the voltage follower circuit 72. Assuming that the difference between the input voltage and the output voltage is up to 10 mV by the end of the first half of the selection period, the load capacitance (charge amount) that must be charged in the second half of the selection period
Is Q = 0.01 × C. As a result, when the output is switched to the output of the DAC 70, the required charge amount Q is 1/1200
By supplying the charge amount (about 0.1%), a necessary gradation can be obtained. The selection period t varies depending on the panel, but a high-definition SXGA display usually takes 8 to 12 μs.
It is about.

During the selection period t between the latch pulses LP, one gate line 2 is
1 is applied with the voltage VX1, and the transistor is turned on.
As a result, the liquid crystal capacity 25 in the liquid crystal panel 20 can be charged. In the data driver IC 30, the control signal CN output in synchronization with the latch pulse LP
By T1, the first switching element Q1 is turned on,
The second switching element Q2 turns off. Therefore, the voltage VY is applied from the voltage follower circuit 72 to the data line 21.
2 is output. This voltage VY2 is charged to the liquid crystal capacitance 25 via the data line 21, and the change over time of the charge to the liquid crystal capacitance 25 reaches, for example, a point A exceeding 99% of the required voltage in the first period t1. ing.

In the second period t2, the first switching element Q1 is turned off, the second switching element Q2 is turned on, and the output of the voltage follower circuit 72 is cut off. The liquid crystal capacitance 25 is charged via the line 21. At this time, DAC7
At 0, the amount of charge that can be supplied per unit time is small,
The active load affecting the output voltage is small, and the liquid crystal capacitor 2
5 is almost completely completed, so that a sufficient voltage can be charged to the liquid crystal capacitor 25 within the selection period t.

Here, when, for example, 10 mV is generated as an offset between the input and output of the voltage follower circuit 72, it is necessary to switch the voltage 10 mV before the necessary gradation voltage. Depending on the design of the ratio of the current drive capability of the voltage follower circuit 72 and the DAC 70, the ratio is 1/10
If it is 0, it is appropriate to set the switching timing when the point A in FIG. 6B reaches 99% of the required voltage.

As described above, in the first half period t1 of the selection period t, a large amount of charge per unit time is supplied by the output of the voltage follower circuit 72 to charge the liquid crystal capacitor 25 to a certain voltage. The latter half period t2 of the selection period t
Thus, by directly supplying the output of the DAC 70 to the liquid crystal capacitor 25, a high-precision output voltage can be quickly obtained without requiring an offset canceling circuit.

The timing at which the output of the voltage follower circuit 72 and the output of the DAC 70 are switched is described below.
A voltage of 90% or more of the necessary gradation voltage is charged in the liquid crystal capacitor 25, and a voltage difference from the necessary voltage is Ｌ LSB (Lea).
The operation when the voltage is set within the range of the voltage width of (st Significant Bit) will be described with reference to FIG.

FIG. 7 is an enlarged view between the reference voltages V3 and V4 of the waveform diagram of the liquid crystal applied voltage shown in FIG.

It is assumed that, for example, a liquid crystal application voltage of only the voltage VA is required to obtain a required liquid crystal display. In the present embodiment, the voltage follower circuit 72 has a range of the width of the voltage VLSB corresponding to Ｌ LSB with respect to the required voltage VA (the range of the voltage VLSB to VA), and 90% or more of the voltage VA. Voltage
It needs to be obtained as a liquid crystal applied voltage. FIG. 7 shows that the voltage VLSB which satisfies the voltage in VAD which is 90% of the required voltage VA and which is within the voltage width of (LSB) / 2 with respect to the voltage VA is charged in the first half period t1 and in the second half period t2 Shows an example in which the voltage is charged up to the voltage VA.

This ensures the necessary liquid crystal display,
The insufficient voltage is compensated for by the output of the DAC 70, and a highly accurate output voltage can be obtained within the selection period t.

The output of the voltage follower 72 and
Regarding the switching timing at which the output of the voltage output source 70 is switched, for example, it is conceivable that a point at which the gradation is guaranteed to some extent is set as the switching timing.

<Second Embodiment> FIG. 8 shows a modification of the voltage supply device having the configuration shown in FIG.

As shown in FIG. 8, a first control signal generating circuit 74 for controlling the first switching element Q1 is provided.
And a second control signal generating circuit 75 for controlling the second switching element Q2, so that the first switching element Q1 and the second switching element Q2 are controlled independently.

FIG. 9 shows a waveform chart according to the embodiment of FIG.

In FIG. 9, the control signal CNT1 output from the data driver IC 30 in synchronization with the latch pulse LP turns on the first switching element Q1. The second switching element Q2 is turned off by the control signal CNT2. At this time, the first switching element Q1 and the second switching element Q2 include:
The control signal CNT2 is controlled so that the period θ during which the switch is simultaneously turned off is set.

The output of the voltage follower 72 is switched to the output of the DAC 70 by the control signals CNT1 and CNT2, and the waveform of the liquid crystal applied voltage such as the output VY2 is shown.

According to the configuration shown in FIG. 8, it is possible to prevent the first switching element Q1 and the second switching element Q2 from being turned on at the same time. As a result, the output of the voltage follower circuit 72 is
The switching element Q2 returns to the non-inverting input terminal 201 of the voltage follower circuit 72 to prevent the oscillation phenomenon.

<Third Embodiment> In the circuit of FIG. 10, in addition to the circuit of FIG.
The third switching element Q3 is provided between the power supply terminals of. The third switching element Q3 is configured to receive control of a control signal CNT1 synchronized with the first switching element Q1. The operations of the DAC 70 and the voltage follower circuit 72 are the same as those of the circuit of FIG.

Here, by switching from the output of the voltage follower circuit 72 to the output of the DAC 70, the output of the voltage follower circuit 72 is cut off by turning off the first switching element Q1. Therefore,
The third switching element Q3 is turned off in synchronization with the timing at which the first switching element Q1 is turned off, and the power supply to the voltage follower circuit 72 is cut off.

Thus, the voltage follower circuit 72
In a period in which the output of the power supply is not used, power consumption can be reduced by cutting off the power supply.

<Fourth Embodiment> As a circuit configuration of the voltage follower circuit 72, for example, a circuit as shown in FIG. 12 can be mentioned. The circuit shown in FIG. 12 is a circuit diagram of a voltage follower circuit 72 for performing class AB operation amplification, and mainly includes a differential amplifier 91, an output amplifier 92, and an input unit 93. FIG. 12 includes N-type MOS transistors QN1 to QN31 and P-type MOS transistors QP1 to QP31. DAC
70 is equal to the input voltage VI of the input unit 93.
N. The output amplifier 92 amplifies the final stage and supplies the output voltage VOUT to the load capacitance.

Input voltage V of voltage follower circuit 72
FIG. 11 shows input / output characteristics of the output voltage VOUT with respect to IN.

VDD in the figure is a voltage follower circuit 7
2, and VEE indicates a ground potential.

In FIG. 11, the input voltage VIN falls within the range of 0 to VTHN due to the operation of the N-type MOS transistor QN31 having the threshold voltage VTHN in the output amplification stage 92 of FIG. The output characteristic 227 is not obtained, and the saturation output characteristic 225 is shown. Similarly,
Due to the operation of the P-type MOS transistor QP31 of the threshold voltage VTHP (negative voltage) in the output amplifying stage 92, the input voltage VIN changes from (VDD + VTHP) to VDD.
Within the range, the linear input / output characteristic 223 cannot be obtained, and the saturated output characteristic 221 is shown.

This is because, in FIG. 12, the input voltage VIN
Changes in the range of 0 V to the threshold voltage VTHN, the N-type MOS transistor Q
At the node 212 connected to the gate of N31 and serving as the drain of the P-type MOS transistor QP21, the potential of the node 212 is lower than the potential of the node 213 corresponding to the source. As a result, when the threshold voltage is lower than VTHN, the N-type MOS transistor QN31 operates in a direction in which it is turned off, so that current cannot flow. For this reason,
The output voltage VOUT is saturated.

When the input voltage VIN is (VDD + VTH)
When the potential changes from P) to the power supply potential VDD, the N-type MOS transistor QN1 connected to the gate of the P-type MOS transistor QP31 in the output amplifier 92.
The potential of the node 212 becomes higher than the potential of the node 211 corresponding to the source. As a result, when the voltage is equal to or higher than the threshold voltage (VDD + VTHP), the P-type MOS transistor QP31 operates in a direction in which the transistor turns off, so that current cannot flow. For this reason,
The output voltage VOUT is saturated.

FIG. 13 shows a circuit having an improved input / output characteristic in which the output voltage is saturated due to the threshold voltages VTHN and VTHP.

The threshold voltages VTHN, VTH
P changes under the influence of the constant current circuit in the voltage follower circuit 72 in addition to the threshold voltage inherent to the MOS transistor element. N-type MOS transistor Q
N11, QN12, P-type MOS transistor QP11,
Due to the QP12, the voltage corresponding to the offset is superimposed because the constant current is flowing. Therefore, in the present embodiment, threshold voltages VTHN and VTHP are assumed in consideration of the voltage corresponding to the offset.

In the circuit shown in FIG. 13, the input voltage at the node 203 of the voltage follower
A comparator 76 for comparing with the output voltage at 4 is added. Based on the comparison result of the comparator 76, a control signal is supplied to the gates of the first switching element Q1 and the second switching element Q2 via the first control signal generation circuit 74.

The comparator 76 determines that the output voltage VOUT at the node 204 is equal to the input voltage (V
IN ± ΔV) (ΔV: any error set value) is compared. A control signal is transmitted via the first control signal generation circuit 74. As a result, the first switching element Q1 is turned off, the second switching element Q2 is turned on, and the output of the DAC 70 becomes the output voltage VOUT. Note that the output voltage VOUT may overshoot or undershoot with respect to the input voltage VIN, and may exceed or fall below the allowable range of the error set value ± ΔV. In this case, the control signal is set by setting an allowable range (VIN ± ΔV) taking this into consideration or increasing the gain of the output voltage VOUT and counting the number of times the output voltage VOUT crosses a certain voltage. The transmission timing can be set.

As a modification of this embodiment, FIG.
A detection method such as 4 is conceivable.

FIG. 14 includes a first comparator 77, a second comparator 78, and an OR circuit 79. The input voltage VIN of the voltage follower circuit 72 is
A comparison signal between the voltage at 3 and the reference voltages set by the first comparator 77 and the second comparator 78 is supplied to the OR circuit 79. The OR circuit 79 includes at least the first comparator 77
Alternatively, when one high-level signal of the second comparator 78 is received, a control signal is supplied to the first switching element Q1 and the second switching element Q2 via the first control signal generation circuit 74. .

Here, for example, as the reference voltage of the first comparator 77, in the input / output characteristics of the voltage follower circuit 72 in FIG.
A boundary point where N is the threshold voltage (VDD + VTHP) is set. When a voltage equal to or higher than the threshold voltage (VDD + VTHP) is input, a high-level signal is output from the first comparator 77 and supplied to the OR circuit 79. Second
Outputs a low level signal from the comparator 78 of
The signal is supplied to a circuit 79. A high level signal is output from the OR circuit 79 and the first control signal generation circuit 7
The control signal is transmitted via the control signal 4. The first switching element Q1 is off, the second switching element Q2
Is turned on, and the output of the DAC 70 becomes the output voltage VOUT. Similarly, as the reference voltage of the second comparator 78, the input voltage VIN at the node 203 in the input / output characteristics of the voltage follower circuit 72 in FIG. 11 is set at the boundary point where the threshold voltage VTHN is reached. When a voltage equal to or lower than the threshold voltage VTHN is input, the second comparator 78
Outputs a high-level signal, and the first comparator 77 outputs a low-level signal. A high-level signal is output from the OR circuit 79, and a control signal is transmitted via the first control signal generation circuit 74. The first switching element Q1 is turned off, the second switching element Q2 is turned on, and the output of the DAC 70 becomes the output voltage VOUT.

By these operations, the input voltage is changed from 0 to V
When the output of the comparator 76 is changed within the range of THN or within the range of (VDD + VTHP) to VDD, the output of the voltage follower circuit 72 is cut off at this timing, and the output is switched to the output of the DAC 70. Is replaced by a linear output characteristic 223 instead of the output characteristic 221 at which
Alternatively, the output characteristic 227 can be secured in place of the output characteristic 225.

When this voltage supply device 58 is used in a TFT liquid crystal device having a DAC system, a highly accurate output voltage can be obtained without requiring an offset cancel circuit. Further, the input voltage is changed from 0V to the power supply voltage VDD.
Can be obtained as an output voltage without saturation, and voltage utilization in a wider range can be achieved.

<Fifth Embodiment> FIG. 15 shows a circuit including a third switching element for turning on and off the power supply voltage of the voltage follower circuit 72 in the voltage supply device having the configuration shown in FIG. I have.

As shown in FIG. 15, the power supply of the voltage follower circuit 72 itself can be turned off while the output of the DAC 70 is supplied as the output voltage. Thus, low power consumption can be achieved.

The present invention can be applied to various electronic devices such as a mobile phone, a game device, an electronic organizer, a personal computer, a word processor, a television, and a car navigation device.

[Brief description of the drawings]

FIG. 1 is a schematic explanatory view showing a liquid crystal device to which the present invention is applied.

FIG. 2 is a block diagram of a conventional data driver IC.

FIG. 3 is a conventional data driver IC shown in FIG. 2;
3 is an output characteristic diagram of FIG.

FIG. 4 is a diagram illustrating a configuration example of a voltage supply device using the conventional voltage follower circuit illustrated in FIG. 2;

FIG. 5 is a diagram showing a voltage supply device according to the first embodiment of the present invention.

6A is an operation waveform diagram of the voltage supply device shown in FIG. 4, and FIG. 6B is an operation waveform diagram of the voltage supply device shown in FIG.

FIG. 7 is a diagram illustrating a relationship between a first half and a second half of a selection period and a voltage charged to a liquid crystal capacitor;

FIG. 8 is a diagram illustrating a voltage supply device according to a second embodiment of the present invention.

FIG. 9 is an operation waveform diagram of the voltage supply device shown in FIG. 8;

FIG. 10 is a diagram illustrating a voltage supply device according to a third embodiment of the present invention.

FIG. 11 is a diagram showing input / output characteristics of a voltage follower used in a fourth embodiment of the present invention.

FIG. 12 is a circuit diagram of a voltage follower having the characteristics shown in FIG.

FIG. 13 is a diagram showing a voltage supply device according to a fourth embodiment of the present invention including the voltage follower shown in FIG.

FIG. 14 is a diagram illustrating a modification of the voltage supply device illustrated in FIG. 13;

FIG. 15 is a diagram illustrating a voltage supply device according to a fifth embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 10 display device 20 liquid crystal panel 21 data line 22 gate line 23 common electrode 24 liquid crystal electrode 25 liquid crystal capacitance 30 data driver IC 40 gate driver IC 42 signal control circuit 44 gradation voltage circuit 46 power supply circuit 48 common electrode drive circuit 50 input latch circuit Reference Signs List 51 shift register 52 line latch circuit 53 latch circuit 54 DA converter 55 voltage follower circuit 58 voltage supply device 70 DA converter 72 voltage follower circuit 73 control signal generation circuit 74 first control signal generation circuit 75 second control signal generation circuit 76 Comparator 77 First comparator 78 Second comparator

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[Procedure amendment]

[Submission date] October 19, 2000 (2000.10.
19)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H093 NA16 NA53 NC03 NC05 NC25 NC34 NC49 NC58 ND39 ND43 ND49 ND54 5C006 AA16 AC11 AC21 AF43 AF82 BB16 BC12 BF03 BF04 FA41 5C080 AA10 BB05 DD22 EE29 FF11 JJ02 JJ04 JJ05 JJ05 JJ05 JJ05 JJ05 JJ05 JJ05 DD04 EA11 EA12 EA37 EB16 EB37 FF03 FF25 GG07

Claims (10)

[Claims] 1. A voltage supply device for supplying a voltage to a load capacitance and charging the load capacitance with a predetermined voltage within a predetermined charging period, comprising: a voltage supply source; and impedance converting the voltage from the voltage supply source. And a first switching element connected between the impedance conversion circuit and the load capacitance; and a voltage from the voltage supply source, the impedance conversion circuit and the first switching. A bypass line for supplying the load capacitance without passing through an element; and a second switching element connected in the middle of the bypass line, wherein the first switching element is turned on during a first half of the charging period. Turning off the second switching element and turning off the first switching element during the latter half of the charging time; A voltage supply device for turning on a switching element. 2. The voltage supply device according to claim 1, wherein both the first switching element and the second switching element are set in an off state. 3. The switching device according to claim 1, further comprising a third switching element connected to a power supply line that supplies a power supply voltage to the impedance conversion circuit, wherein the third switching element is configured to perform the first switching operation. A voltage supply device which is turned off in synchronization with an off operation of an element. 4. The impedance conversion circuit according to claim 1, wherein the impedance conversion circuit is constituted by a voltage follower circuit, wherein a power supply potential of a power supply voltage supplied to the voltage follower circuit is VDD, and a ground potential is VEE. When an input voltage close to the power supply potential VDD is input, the voltage follower circuit has a characteristic that the output voltage does not show a linear characteristic with respect to the input voltage, and the output voltage saturates; In the saturation region of the output voltage of the follower circuit, the first switching element is turned off, the second switching element is turned on, and the voltage of the voltage output source is supplied to the load capacitance via the bypass line. A voltage supply device. 5. The voltage conversion circuit according to claim 1, wherein the impedance conversion circuit is configured by a voltage follower circuit, wherein a power supply potential of the power supply voltage supplied to the voltage follower circuit is VDD, and a ground potential is VEE. When an input voltage close to the ground potential VEE is input, the voltage follower circuit has a characteristic that the output voltage does not exhibit a linear characteristic with respect to the input voltage, and the output voltage is saturated. In the saturation region of the output voltage of the voltage follower circuit, the first switching element is turned off and the second switching element is turned on during the charging period, and the voltage output is output via the bypass line. A voltage supply device for supplying a source voltage to the load capacitance. 6. The device according to claim 4, further comprising: a comparator that compares an output voltage of the voltage output source with an output voltage of the voltage follower circuit, based on a comparison result of the comparator. A voltage supply device for controlling a state of the second switching element. 7. A semiconductor device comprising the voltage supply device according to claim 1. 8. A display unit using an electro-optical element, and a drive IC for driving a signal line of the display unit, wherein the drive IC supplies a voltage to a load capacitance and supplies a voltage to a load capacitor within a predetermined charging period. A voltage supply device for charging the load capacitance with a predetermined voltage, the voltage supply device includes: a voltage supply source; an impedance conversion circuit that converts a voltage from the voltage supply source into an impedance and outputs the converted voltage; A first switching element connected between a conversion circuit and the load capacitance; and a voltage from the voltage supply source supplied to the load capacitance without passing through the impedance conversion circuit and the first switching element. And a second switching element connected in the middle of the bypass line, wherein the first switching element is turned on and turned on during the first half of the charging period. Turns off the second switching element, wherein the latter period of the charging time first off the switching element, an electro-optical device, characterized in that turning on the second switching element. 9. The DA according to claim 8, wherein the electro-optical element is driven for gradation based on a stepwise voltage from the voltage supply device, and the voltage output source converts a digital gradation signal to an analog voltage. A voltage within a voltage range corresponding to (LSB) / 2 with respect to a desired gradation voltage value to be supplied to the electro-optical element, and the desired gradation voltage The electro-optical device according to claim 1, wherein the first half period is terminated after a voltage of 90% or more of the value is charged to the load capacitance. 10. An electronic apparatus comprising the electro-optical device according to claim 8.