JP2005251898A - Wafer level package structure and its manufacturing method, and element divided from its wafer level package structure - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wafer level package structure which can minimize each individual package and which can laminate a substrate at a comparatively low temperature, and to provide a method of manufacturing the same. <P>SOLUTION: The wafer level package structure includes a first substrate 1 having a plurality of functional elements 2 each having input and output electrodes, and a second substrate 11 in which the respective functional elements are laminated to be sealed. The second substrate has through holes 11a, 11B opposed to input and output electrodes 4a, 4b, and through conductors 21a, 22a filled in the through holes, respectively. The input and output terminals 21, 22 of the respective functional elements are constituted to include the through holes and the first conductors. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a wafer level package structure in which elements such as a semiconductor element, a MEMS (Micro Electro Mechanical Systems) sensor, a high frequency circuit, and a MMIC (Monolithic Microwave Integrated Circuit) are packaged at a wafer level.

  The package structure required to make a semiconductor element and a MEMS element into one module is an important technology that not only affects the performance of the element but also greatly affects the product size and product price. Conventionally, it has been common to cut out elements from a wafer and then package them individually. Recently, in order to reduce manufacturing costs, packaging technology at the wafer level has been actively researched and developed. In addition, since MEMS elements have movable parts and dislike moisture in the air, it is difficult to handle after separation, such as filling with inert gas or vacuum sealing, so A wafer level package is advantageous.

  One of the problems in packaging at the wafer level is how to take out signal terminals from the element. This signal extraction structure is an element that determines the size of the module or sensor, and is directly related to the product price. In high frequency applications, as the operating frequency increases, the high frequency characteristics are affected by the take-out structure, and the transceiver module needs to be downsized as the wavelength of the radio wave to be handled becomes shorter.

  As such a wafer level package structure, Patent Document 1 discloses a wafer bonded using a frit glass. The frit glass disclosed in this patent is a low-melting glass that melts at a temperature of about 400 ° C.

  9A and 9B show a simplified structure based on the disclosure of Japanese Patent No. 3303146. In this structure, the functional element 52 and its extraction electrode 53a are formed on the substrate 51. The substrate 54 has a recess 54a, and the substrate 51 and the substrate 54 are bonded together by a frit glass 55 so that the functional element 52 and the recess 54a face each other. The semiconductor element 52 is filled with an inert gas or vacuum-sealed by the substrate 54. Further, the signal is taken out by the wiring 53 and connected to another signal processing circuit or the like by wire bonding from the electrode pad 53a. Such a signal terminal extraction method is referred to as feed-through wiring.

  In this conventional example, since the sealing pattern 55 of frit glass is usually produced by a screen printing method, the pattern width is generally as wide as about 500 μm to 1 mm, and the sealing portion occupies a large area. Become. Furthermore, the necessity of the electrode pad 53b outside the crossing of the sealing pattern is also a factor for taking up an area.

In addition, in an integrated high-frequency module in which active elements such as MMIC are flip-chip mounted on a passive circuit built on a silicon substrate using MEMS technology, etc., processing is performed at 300 ° C. or lower in order to avoid adverse effects on the flip-chip element. A possible packaging technology is desired. For packages such as sensors, an efficient method of taking out signal terminals is desired for the purpose of downsizing.
Patent No. 3303146

  However, in the wafer level package using the feedthrough wiring of the conventional example, the sealing area is increased due to the method of forming the frit glass, or the necessity of forming the input / output terminals on the same plane as the functional element, etc. As a result, there was a limit to miniaturization of modules or sensors. Further, frit glass bonding has a problem that a high temperature process of 400 ° C. or higher is required.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a wafer level package structure and a method for manufacturing the wafer level package structure in which each individual package portion can be made small and substrates can be bonded at a relatively low temperature.

  In order to achieve the above object, a wafer level package structure according to the present invention is bonded to a first substrate provided with a plurality of functional elements each having an input / output electrode and to seal each functional element. A wafer level package structure including a second substrate combined, the second substrate having a through hole facing each of the input / output electrodes, and a first conductor filled in the through hole. The input / output terminal of each functional element includes the through hole and the first conductor.

The wafer level package structure according to the present invention does not need to form the input / output terminals on the same plane as the functional element, and thus can be miniaturized.
In addition, the first conductor and the input / output electrode are joined by a second conductor having a melting point lower than that of the first conductor, and the first sealing base metal film surrounding each of the functional elements, and the first sealing thereof. The first substrate and the second substrate are joined at a relatively low temperature by joining the second sealing base metal film facing the stop base metal film with a third conductor having a melting point lower than that of the first conductor. It becomes possible.

Embodiments according to the present invention will be described below with reference to the drawings.
Embodiment 1 FIG.
The wafer level package structure according to the first embodiment of the present invention is obtained by bonding a second substrate 11 to a first substrate (wafer) 1 on which a plurality of elements 2 are formed using semiconductor manufacturing technology. A wafer level package structure in which each element 2 is individually sealed in a wafer state before being separated into elements, and input / output terminals 21 and 22 of each element are formed on the second substrate 11 in the individual package portion. It is characterized by using the through-hole made.
The structure according to the present invention is referred to as a wafer level package structure because a typical example is a semiconductor wafer such as silicon. The wafer level package structure according to the present invention uses a semiconductor wafer. The structure using other substrates, such as glass, is not restricted to a thing.

  More specifically, in the wafer level package structure of the first embodiment, on one surface of the first substrate 1, the element 2, the extraction electrodes 3a and 3b connected to the element 2, the extraction electrode 3a, The connection electrodes 4a and 4b connected to one end of 3b are formed, and the sealing base metal film 5 is formed so as to surround the element 2, the extraction electrodes 3a and 3b, and the connection electrodes 4a and 4b. (FIGS. 1A and 1B). The connection electrodes 4a and 4b are made of a conductive material having good wettability with a second conductor formed in through-holes 11a and 11b, which will be described later. Is configured. Further, as the material of the sealing base metal film 5, a material having good solder wettability with respect to a third conductor described later is selected.

  In FIG. 1A and FIG. 1B, one element 2 and one individual package portion including the lead electrodes 3a and 3b, the connection electrodes 4a and 4b, and the sealing base metal film 5 of the one element 2 are formed. Although only the corresponding portions are shown, several tens to several hundreds of elements 2 are formed on the first substrate 1, and lead-out electrodes 3a and 3b, connection electrodes 4a, 4b and a base metal film 5 for sealing are formed.

  Further, in the first embodiment, the second substrate 11 is made of, for example, a silicon wafer or the like, and is formed so as to face the recess 11c for forming a space for hermetically sealing the element 2 and the connection electrodes 4a and 4b. The through-holes 11a and 11b thus formed, the input / output terminals 21 and 22 respectively configured using the through-holes, and the sealing base metal film 14 formed to face the sealing base metal film 5, It is provided so as to correspond to each element 2 (FIGS. 2A and 2A).

Here, the input / output terminal 21 is composed of a through-hole 11a and a first conductor 21a filled therein with an insulating film 12a and a conductor film 13a, and is one input / output electrode of the element 2 for connection. A second conductor 21b is formed in a bump shape so as to face the electrode 4a. In the first embodiment, as the material of the conductor film 13a, a material having good solder wettability with respect to the first conductor 21a filled in the through hole 11a is selected, and the airtightness and reliability of the input / output terminal 21 are selected. Is secured.
The input / output terminal 22 is also constituted by a through hole 11b and a first conductor 22a filled therein with an insulating film 12b and a conductor film 13b, and a connection electrode 4b which is the other input / output electrode of the element 2; A second conductor 22b is formed in a bump shape so as to face each other. As a material of the conductor film 13b, in order to ensure airtightness and reliability, the first conductor 22a filled in the through hole 11b is wetted with solder. A material with good properties is selected.
Further, a material having good solder wettability with respect to the third conductor 23 is selected as the material of the sealing base metal film 14, and the third conductor 23 serving as a sealing material is formed on the sealing base metal film 14. Is formed.

In the first embodiment, it is preferable that the melting points of the second conductor and the third conductor are selected to be equal to or lower than the melting point of the first conductor. For example, when gold-tin eutectic solder (Au—Sn, melting point 280 ° C.) is selected as the first conductor, tin-copper eutectic solder (Sn—Cu, melting point 226 ° C.) is selected as the second and third conductors. . Such a combination may be another conductor as long as the above-described melting point relationship is established. As described above, when the material of the second conductor and the third conductor is selected to be equal to or lower than the melting point of the first conductor, in the joining process of the first substrate 1 and the second substrate 11, The first substrate 1 and the second substrate 11 can be joined without deteriorating the airtightness.
Moreover, it may replace with the 3rd conductor used as a sealing material, and may use the thermosetting resin hardened | cured at the temperature below melting | fusing point of a 1st conductor. Examples of the thermosetting resin include BCB (benzocyclobutene) that is cured at 200 ° C. to 250 ° C.

The first substrate 1 and the second substrate 11 configured as described above are such that the connection electrodes 4a and 4b and the input / output terminals 21 and 22 face each other, and the sealing base metal film 5 and the sealing base metal The wafer level package structure of the first embodiment is configured by bonding so that the films 14 face each other.
Here, the element 2 includes a functional element such as a MEMS (Micro Electro Mechanical Systems) element manufactured by micromachining in addition to a functional element made of a semiconductor on which a normal semiconductor circuit is formed. Include an inertial force sensor, a high-frequency control circuit (RF / MEMS element), an infrared sensor, and the like.

  In each individual package portion of the wafer level package structure according to the first embodiment configured as described above, the electrical signal input to the input / output terminal 21 is the first conductor 21a, the second conductor 21b, and the connection electrode 4a. The signal is input to the element 2 through the extraction electrode 3a, for example, after being processed there, and then output from the input / output terminal 22 through the extraction electrode 3b, the connection electrode 4b, the second conductor 22b, and the first conductor 22a The For example, the element 2 which is a semiconductor element is hermetically sealed by the third conductor 23.

  Hereinafter, a method for manufacturing the wafer level package structure according to the first embodiment will be described with reference to FIGS. 3A to 3H. In the following example, a description will be given using an example in which a silicon substrate is used as the first substrate 1 and the second substrate 11.

First step.
In the first step, a mask 31 for forming the recess 11c is formed on the silicon substrate 11 as the second substrate by photolithography (FIG. 3A).
Second step.
In the second step, the recess 11c is formed by alkali etching or the like (FIG. 3B).

Third step.
In the third step, the mask 31 is removed to form a mask 32 for forming the through holes 11a and 11b, and the through holes 11a and 11b are formed by inductively coupled plasma (ICP) etching or the like. (FIG. 3C).
Fourth step.
In the fourth step, the mask 32 is removed, and then the insulating films 12a and 12b are formed by thermal oxidation and photolithography (FIG. 3D).

5th process.
In the fifth step, the conductor films 13a and 13b and the sealing base metal film 14 having good wettability with the first conductor and the third conductor are formed by sputtering film formation and photolithography. The conductor films 13a and 13b and the sealing base metal film 14 can be formed of a common conductor, and the conductor film can be formed of, for example, chromium / nickel / gold (Cr / Ni / Au) ( FIG. 3E). If a material with good wettability with the first conductor is selected as the conductor films 13a and 13b, and a material with good wettability with the third conductor is selected as the base metal film for sealing 14, the conductor films 13a and 13b The material of the sealing base metal film 14 may be different.

Sixth step.
In the sixth step, the first conductors 21a and 22a are embedded in the through holes 11a and 11b by the solder chute method. For example, Au—Sn having a melting point of 280 ° C. can be selected as the first conductor. The solder chute method is a method in which a low melting point conductor such as solder (here, the first conductor) is made into fine particles (fine droplets) with a diameter of several tens of μm and ejected from the nozzle head 33 using an ink jet method. (FIG. 3F). At the time of this embedding, in the first embodiment, in the fifth step, the conductor films 13a and 13b having good solder wettability and the first conductor are formed in the through holes 11a and 11b, respectively. 22a can be densely embedded in the through holes 11a and 11b, and good airtightness can be obtained in the through holes 11a and 11b.

Seventh step.
In the seventh step, the second conductors 21b and 22b are formed in a bump shape by the solder chute method on the first conductors 21a and 22a embedded in the sixth step. For example, Sn—Cu having a melting point of 226 ° C. can be selected as the second conductor (FIG. 3G).
Eighth step.
In the eighth step, the third conductor 23 is formed in a bump shape by the solder chute method on the sealing base metal film 14 which is the sealing region. As the third conductor, for example, the same Sn—Cu as that of the second conductor can be selected. Further, the bump-shaped third conductors are formed on the sealing base metal film 14 by arranging as many as necessary to join the sealing base metal film 5 and the sealing base metal film 14 without gaps. (FIG. 3H).

Ninth step.
In the ninth step, on the substrate 1 on which the element 2, the extraction electrodes 3a and 3b, the connection electrodes 4a and 4b for improving the solder wettability to the second conductors 21b and 22b, and the sealing conductor film 5 are formed. The silicon substrate 11 after the eighth step is disposed face down so that the concave portion 11c faces the element 2, and the second conductors 21b and 22b and the third conductor 23 made of solder bumps are respectively formed using an alignment device. Are adjusted so as to face the connection electrodes 4a and 4b and the sealing base metal film 5, respectively, and installed in the wafer bonding apparatus (FIG. 2A).

Tenth step.
In the tenth step, pressure and temperature are applied to the two substrates in the vacuum bonding state or the nitrogen atmosphere state in the wafer bonding apparatus with the first substrate 1 and the second substrate 11 stacked in alignment. The temperature is in the vicinity of the melting points of the second conductor and the third conductor and is equal to or lower than the melting points of the first conductors 21a and 22a. Thereby, the second conductors 21b and 22b are reflowed on the connection electrodes 4a and 4b to be electrically connected to the extraction electrodes 3a and 3b without deteriorating the airtightness of the input / output terminals 21 and 22 parts, Similarly, the third conductor 23 is reflowed and bonded on the conductor film 5, and the inside surrounded by the third conductor 23 is hermetically sealed (FIG. 2B).

  When the above-described photosensitive BCB resin is used as the sealing material instead of the third conductor 23, a BCB sealing pattern is formed by photolithography instead of the solder chute method in the eighth step. What is necessary is just to perform a process and a 10th process. In this case, the sealing base metal film 14 and the sealing base metal film 5 are unnecessary.

  In the wafer level package structure according to the first embodiment configured as described above, each input / output terminal is configured using the through-hole formed in the second substrate. Since no input / output terminals are formed, each individual package portion can be reduced in size.

  In addition, since the first conductor and the input / output electrode are joined by the second conductor having a melting point lower than that of the first conductor, the first conductor and the input / output electrode can be connected without deteriorating the airtightness of the input / output terminal portion. It is possible to join.

  Furthermore, in the wafer level package structure according to the first embodiment, the first substrate has a lower melting point than the first conductor in the sealing base metal film 5 and the sealing base metal film 14 surrounding each functional element. Since it is joined by the third conductor, the first substrate and the second substrate can be joined without deteriorating the airtightness of the input / output terminal portion.

  Moreover, in this Embodiment 1, since a 2nd conductor and a 3rd conductor consist of the same material, a process can be simplified.

  Moreover, in this Embodiment 1, a 1st board | substrate and a 2nd board | substrate can also be joined by sealing resin, and in that case, this sealing resin is used for the 1st conductor by a 2nd conductor, and an input-output electrode. By using a resin capable of sealing the functional element at the bonding temperature, the process can be simplified without deteriorating the airtightness of the input / output terminal portion.

Embodiment 2. FIG.
As shown in FIG. 4, in the wafer level package structure according to the second embodiment of the present invention, the second conductors 21b and 22b are formed on the connection electrodes 4a and 4b formed on the substrate 1, respectively. Except that the conductor 23 is formed on the sealing base metal film 5 formed on the substrate 1 and the first substrate 1 and the second substrate 11 are joined, the configuration is the same as in the first embodiment.
Even with the above, a wafer level package structure similar to that of the first embodiment shown in FIG. 2B can be obtained, and the same effects as those of the first embodiment can be obtained.

Embodiment 3 FIG.
As shown in FIG. 5, the wafer level package structure according to the third embodiment of the present invention is configured separately from the first substrate 1 in place of the element 2 configured integrally on the first substrate 1. The configuration is the same as that of the wafer level package of the first embodiment except that the chip element 6 which is a functional element is flip-chip bonded onto the extraction electrodes 3a and 3b of the first substrate 1. In the third embodiment, the chip-like semiconductor chip element 6 is flip-chip mounted on the substrate 1 with Au bumps 7. In the third embodiment, the first substrate 1 is silicon and the semiconductor chip element 6 is a monolithic microwave integrated circuit (MMIC) configured using a gallium arsenide substrate, or a microwave configured using a substrate such as alumina. This is particularly effective in the case of an integrated circuit.

  In the third embodiment, as shown in FIG. 6, instead of the recess 11c of the second substrate 11, a recess 1c is formed in the first substrate 1, and the semiconductor chip element 6 is flip-chip bonded to the recess 1c. You may make it do.

Embodiment 4
As shown in FIGS. 7A and 7B, the wafer level package structure according to the fourth embodiment of the present invention includes a semiconductor chip element 6 connected to each element 2 and includes the element 2 and the semiconductor chip element 6. The configuration is the same as that of the first embodiment except that the functional element is configured and the functional circuits are collectively sealed.
Specifically, as shown in FIGS. 7A and 7B, one lead electrode 3b of the element 2 is separated into two, and the semiconductor chip element 6 is flip-chip bonded between them. In FIG. 7A, the part connected to the element 2 is displayed as the extraction electrode 3d.
An airtight space is formed between the first substrate 1 and the second substrate 11 by the recess 11 c formed so as to form a space in which the element 2 and the semiconductor chip element 6 can be accommodated.
In this way, the wafer level package structure of the fourth embodiment having the semiconductor chip element 6 flip-chip mounted with the element 2 on the same plane of the silicon substrate 1 and sealing them together is configured. The

  In the individual package part of the wafer level package structure according to the fourth embodiment configured as described above, the electrical signal input to the input / output terminal 21 is the first conductor 21a, the second conductor 21b, the connection electrode 4a, The signal is input to the element 2 through the extraction electrode 3a, for example, is subjected to signal processing there, and then input to the semiconductor chip element 6 that is flip-chip mounted via the extraction electrode 3d and the conductor bump 7, where further signal processing or the like Then, the signal is output from the input / output terminal 22 through the extraction electrode 3b, the connection electrode 4b, the second conductor 22b, and the first conductor 22a.

Embodiment 5 FIG.
As shown in FIGS. 8A and 8B, the wafer level package structure according to the fifth embodiment of the present invention has a plurality of elements by attaching a third substrate 41 to the first substrate 1 and the second substrate 11. Are packaged at a wafer level, and the element 2 and the chip element 6 constituting the functional element are formed or mounted on different substrates.

Specifically, the first substrate 1 sandwiched between the second substrate 11 and the third substrate 41 includes the element 2, lead electrodes 3 a and 3 b connected to the element 2, and through wiring connected to the lead wiring 3 b. 24, a through wiring 25 for connecting the second substrate 11 and the third substrate 41 is formed.
Further, on the upper surface of the first substrate 1, a sealing base metal film 5a that includes the element 2, the extraction electrodes 3a and 3b, the through wiring 24, and the through wiring 25 and defines an individual package portion is formed. On the lower surface of one substrate 1, a sealing base metal film 5b is formed so as to face the sealing base metal film 5a.

A connection electrode 4a is formed at one end of the extraction electrode 3a connected to the element 2, and the input / output terminal 21 of the second substrate 11 is connected to the connection electrode 4a.
The through wiring 24 includes a through hole 1b and a first conductor 24a filled therein with an insulating film 12c and a conductor film 13c.
The through wiring 25 is formed outside the connection electrode 4a, and includes a through hole 1c and a first conductor 25a filled therein with an insulating film 12d and a conductor film 13d.
Further, on the through wiring 25, a connection electrode 4b that is electrically separated from the connection electrode 4a is formed.

  In the fifth embodiment, the second substrate 11 is formed with a recess 11c, input / output terminals 21 and 22, and a sealing base metal film 14 configured in the same manner as in the first embodiment. In the fifth embodiment, the input / output terminals 21 and 22 are arranged on one side of the recess 11c. A third conductor 23 is formed on the sealing base metal film 14.

  The third substrate 41 has a recess 41a, and lead electrodes 42a and 42b separated on the bottom surface of the recess 41a and a sealing base metal film 44 are formed around them. For example, the semiconductor chip element 6 is flip-chip mounted on the bottom surface of the concave portion 41a where the extraction electrodes 42a and 42b are separated. Also, second conductors 25b and 24b are formed at one end of the lead electrodes 42a and 42b via connection electrodes 43a and 43b, respectively, and a third conductor 26 is formed on the sealing base metal film 44. Has been.

In the fifth embodiment, under the first substrate 1, the sealing base metal film 44 and the sealing base metal film 5 b are opposed to the third substrate 41, and the connection electrodes 43 a and 43 b are respectively connected to the through wiring 25, 24, the second substrate 11 is placed on the first substrate 1, the sealing base metal film 5 a and the sealing base metal film 14 face each other, and the through wiring 25 and the input / output terminal 22 Are arranged so that the connection electrode 4a and the input / output terminal 21 face each other, and are joined to each other as shown in FIG. 8B.
As described above, the uppermost second substrate 11 has the input / output terminals 21 and 22, the element 2 is integrally formed on the first substrate 1 positioned in the middle, and the lowermost third substrate 41 ( The wafer level package structure according to the fifth embodiment in which the flip chip mounting element is disposed in the recess 41a) is configured.

  In the wafer level package structure according to the fifth embodiment configured as described above, for example, the element 2 is a passive circuit built in a silicon substrate, and the chip element 6 to be flip-chip mounted is gallium arsenide or alumina. For example, suitable for a high-frequency signal control circuit.

  In the wafer level package structure of the fifth embodiment, the electrical signal input to the input / output terminal 21 of the second substrate 11 is transmitted via the first conductor 21a, the second conductor 21b, the connection electrode 4a, and the lead electrode 3a. After being input to the element 2 of the first substrate 1 and subjected to signal processing there, the flip chip mounting chip element is connected via the extraction electrode 3b, the first conductor 24a constituting the through wiring 24, the second conductor 24b, and the extraction electrode 42b. 6, the signal is processed there, and then output from the input / output terminal 22 through the extraction electrode 42 a, the second conductor 25 b constituting the through wiring 25, and the first conductor 25 a.

  The wafer level package structure of the fifth embodiment described above has the same effects as those of the first embodiment and the like, and can be further miniaturized because the modules can be further stacked.

As described above in detail, according to the first to fifth embodiments of the present invention, since the input / output terminals of the functional element can be taken out in the vertical direction of the substrate using the through wiring technique, the package can be reduced in size and the module. Stacking can be achieved. Further, since the bonding of the substrate (wafer) and the terminal connection of the through wiring (including the input / output terminals) are performed using a solder metal or a resin material, the process temperature related to these can be reduced to 300 ° C. or less, and the flip chip mounting element Even if a wafer having a built-in structure is bonded, there is an advantage that the airtightness and the flip chip bump are not adversely affected.
Furthermore, the conductor constituting the through wiring is composed of two types of solders having different melting points, and the solder having the lower melting point is used for connecting the through wiring and joining between the substrates. The higher solder does not reflow and melt, and the semiconductor element in the substrate can be filled with an inert gas or vacuum sealed.

It is a top view of the 1st board | substrate in the wafer level package structure of Embodiment 1 which concerns on this invention. It is sectional drawing about the A-A 'line | wire of FIG. FIG. 4 is a cross-sectional view of the wafer level package structure according to the first embodiment before bonding the first substrate and the second substrate. FIG. 3 is a cross-sectional view (after bonding) of the wafer level package structure of the first embodiment. FIG. 6 is a cross-sectional view (1) for illustrating a manufacturing process of the second substrate in the first embodiment. FIG. 6 is a cross-sectional view (2) for illustrating the manufacturing process for the second substrate in the first embodiment. FIG. 10 is a cross-sectional view (3) for illustrating the manufacturing process for the second substrate according to the first embodiment. FIG. 6 is a cross-sectional view (4) for illustrating the process for manufacturing the second substrate in the first embodiment. FIG. 10 is a cross-sectional view (5) for illustrating the manufacturing process for the second substrate in the first embodiment. FIG. 10 is a cross-sectional view (6) for illustrating a process for manufacturing the second substrate in the first embodiment. FIG. 10 is a cross-sectional view (7) for illustrating the manufacturing process for the second substrate according to the first embodiment. FIG. 10 is a cross-sectional view (8) for illustrating the manufacturing process for the second substrate in the first embodiment. It is sectional drawing of the wafer level package structure of Embodiment 2 which concerns on this invention. It is sectional drawing of the wafer level package structure of Embodiment 3 which concerns on this invention. It is sectional drawing of the wafer level package structure of the modification of Embodiment 3 which concerns on this invention. FIG. 10 is a cross-sectional view of the wafer level package structure according to the fourth embodiment before bonding the first substrate and the second substrate. It is sectional drawing (after joining) of the wafer level package structure of Embodiment 4. It is sectional drawing before joining the 1st board | substrate in the wafer level package structure of Embodiment 5, a 2nd board | substrate, and a 3rd board | substrate. It is sectional drawing (after joining) of the wafer level package structure of Embodiment 5. It is a top view of the wafer level package of a prior art example. It is sectional drawing about the B-B 'line | wire of FIG. 9A.

Explanation of symbols

1 First substrate,
2 elements,
3a, 3b, 3d, 42a, 42b Lead electrodes,
4a, 4b, 43a, 43b connection electrodes,
5, 14, 44 Base metal film for sealing,
6 chip elements,
7 Au bump,
11 Second substrate,
11a, 11b through-holes,
1c, 11c, 41a recess,
12a, 12b, 12c, 12d insulating film,
13a, 13b, 13c, 13d conductor film,
21, 22 I / O terminals,
21a, 22a, 24a, 25a first conductor,
21b, 22b, 25b, 24b second conductor,
23, 26 Third conductor,
31, 32 masks,
41 Third substrate,
24, 25 Through wiring,
1b, 1c through hole,

Claims (15)

A wafer level package structure comprising a first substrate provided with a plurality of functional elements each having an input / output electrode, and a second substrate bonded to seal each functional element,
The second substrate includes a through hole facing the input / output electrode and a first conductor filled in the through hole, and the input / output terminal of each functional element is connected to the through hole and the first electrode. A wafer level package structure comprising a conductor.   The wafer level package structure according to claim 1, wherein the first conductor and the input / output electrode are joined by a second conductor having a melting point lower than that of the first conductor. The first substrate has a first sealing base metal film surrounding each of the functional elements, and the second substrate is a second sealing base facing the first sealing base metal film. Has a metal film,
3. The wafer level package structure according to claim 1, wherein the functional elements are hermetically sealed by joining the first sealing base metal film and the second sealing base metal film with a third conductor. body.   The third conductor may bond the first sealing base metal film and the second sealing base metal film at a bonding temperature between the first conductor and the input / output electrode by the second conductor. 4. The wafer level package structure according to claim 3, comprising a conductor that can be formed.   The wafer level package structure according to claim 4, wherein the second conductor and the third conductor are made of the same material.   The first substrate and the second substrate are joined by a sealing resin provided so as to surround each of the functional elements, and the sealing resin is formed by the second conductor. 3. The wafer level package structure according to claim 2, wherein the wafer level package structure is made of a resin capable of sealing each element at a junction temperature between one conductor and the input / output electrode.   The wafer level package structure according to any one of claims 1 to 6, wherein each of the functional elements is sealed with an inert gas or vacuum-sealed.   The wafer level package structure according to claim 1, wherein the second substrate has a second recess in a region facing each functional element.   The wafer level package structure according to claim 1, wherein each functional element includes a chip element that is flip-chip mounted on the first substrate.   The wafer level package according to claim 1, wherein the first substrate includes a first recess, and each functional element includes a chip element flip-chip mounted on a bottom surface of the first recess. Structure.   Each of the functional elements includes a first element integrally formed with the first substrate and a second element that is flip-chip mounted. Wafer level package structure.   The second substrate of the first substrate further includes a third substrate on which an element constituting a part of the functional element is formed, and the third substrate seals the element formed on the third substrate. The wafer level package structure according to any one of claims 1 to 11, which is bonded to a surface opposite to the substrate.   An element formed by dividing the wafer level package structure according to any one of claims 1 to 12. A method for producing a wafer level package structure, comprising: a first substrate provided with a plurality of functional elements each having input / output electrodes; and a second substrate bonded to seal each of the functional elements. And
Forming through holes at positions facing the input / output electrodes in the second substrate,
Filling each through hole with a first conductor;
Forming the first bonding electrode in the first substrate so as to include the functional element and the input / output electrode, respectively;
Forming a second bonding electrode at a position facing the first bonding electrode in the second substrate;
A method for producing a wafer level package structure, comprising: joining the first joining electrode and the second joining electrode; and joining the first conductor and the input / output electrode with a metal having a melting point lower than that of the first conductor. . The step of filling the through holes with the first conductors,
Forming an insulating film in the through hole;
On the insulating film, forming a conductor film capable of getting wet with the dissolved first conductor;
15. The method of manufacturing a wafer level package structure according to claim 14, further comprising: dropping particles obtained by melting the material of the first conductor into a through hole in which the conductor film is formed.

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