JP2005223364A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a resin seal of a surface-mounted plastic seal package from warping, using a LOC. <P>SOLUTION: In a manufacturing process of semiconductor device 42 composed of a surface-mounted plastic seal package using a LOC, a molding step of a plastic seal 40 connects a plurality of anti-warp leads 20 for preventing the plastic seal 40 from warping, which are respectively placed on both side portions of a chip 24 in the plastic seal 40, to both of outer frame 13 of a lead frame 12 and section frame 14 respectively. After molding the plastic seal 40, the connections between the anti-warp leads 20 and the outer frame 13 and the section frame 14 are cut. The anti-warp lead 20 is formed integrally with an inner lead 17. Since the volumes of the side portions of the chip of the plastic seal 40 are divided up and down, at the portions, a warp which enlarges upper side and shrinks lower side can be prevented from occurring. Since the anti-warp leads are stabilized during poring resin, resin balancing can be improved. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a technique for preventing warpage in a resin encapsulant, and for example, a semiconductor integrated circuit device (hereinafter referred to as LOC) including a leadless on-chip package (hereinafter referred to as LOC). , IC), and a technique effective for use in the manufacturing method.

As a package for a dynamic random access memory (DRAM), an LOC is widely used as an internal structure, and a surface mount type resin-sealed package is widely used as an external structure.
The LOC is a package in which a plurality of inner leads are stuck on a semiconductor chip (hereinafter referred to as a chip) via an insulating layer, and each inner lead is electrically connected to the chip by a wire.
The surface-mount type resin-sealed package has an outer lead group aligned and protruded from the side surface of a resin-sealed body molded into a flat plate shape using an insulating resin. It is a package bent into a surface mountable shape such as a lead shape.

Note that there is Non-Patent Document 1 as an example describing an IC having a LOC.
“Practical Course VLSI Packaging Technology (below)”, Nikkei BP, May 31, 1993, p. 158

Generally, in a resin-sealed package, if the ratio of the resin thickness above the chip to the resin thickness below the chip in the resin-sealed body (hereinafter referred to as the top-to-bottom ratio) approaches “1”, the resin-sealed body It is known that warpage does not occur, but warpage occurs in the resin sealing body when it is away from “1”.
In the surface-mount type resin-sealed package, when the resin-sealed body is warped, the outer lead is peeled off from the land of the printed wiring board during surface mounting.
Therefore, in the conventional general surface mount resin-sealed package, the so-called tab lowering is performed to bring the resin thickness up-down ratio closer to “1”.

  However, in the LOC surface-mount type resin-sealed package, it is possible to warp the resin-sealed body just by making the resin thickness above the chip equal to the resin thickness below the chip. Revealed by the inventor.

  An object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing the occurrence of warpage in a resin-sealed body even if it is a LOC surface-mount type resin-sealed package.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  An outline of typical inventions among inventions disclosed in the present application will be described as follows.

A semiconductor chip and a semiconductor device manufacturing method in which a plurality of inner leads electrically connected to the semiconductor chip are resin-sealed by a rectangular resin sealing body,
In the molding step of the resin sealing body, the warp prevention leads that are laid on both sides of the semiconductor chip of the resin sealing body and prevent the resin sealing body from warping are rectangular frames of the lead frame. A method for manufacturing a semiconductor device, wherein the semiconductor device is connected to a body in both a vertical direction and a horizontal direction.

According to the above-described means, since the warp preventing leads are disposed on both sides of the semiconductor chip, the portions on both sides of the semiconductor chip in the resin sealing body are divided in volume up and down. In the portion of the resin sealing body, it is possible to prevent the occurrence of warping in which the upper side expands and the lower side contracts.
Also, in the resin sealing body molding process, the warp prevention lead is connected to the rectangular frame of the lead frame in both the vertical direction and the horizontal direction, so that the warp prevention lead can be used when injecting the resin. The resin balance can be improved.

1A and 1B show a semiconductor device according to an embodiment of the present invention. FIG. 1A is a partially cut plan view, and FIG. 1B is a partially omitted side sectional view taken along line bb in FIG. is there.
FIG. 2 and subsequent figures are diagrams for explaining a semiconductor device manufacturing method and operation according to an embodiment of the present invention.

In this embodiment, the semiconductor device according to the present invention is shown in FIGS. 1A and 1B as a DRAM having a LOC in the internal structure and a surface-mount type resin-sealed package in the external structure. It is configured to be.
The LOC of a DRAM (hereinafter referred to as a semiconductor device), which is an example of a semiconductor integrated circuit device (IC), is an insulating tape as an insulating layer on a semiconductor chip (hereinafter referred to as a chip) 24 in which a DRAM circuit is built. A plurality of inner leads 17 are attached via 27, and each inner lead 17 is electrically connected to the chip 24 by a wire 28.
The surface mount resin-sealed package is configured as a resin-sealed TSOP (Thin Small Outline Package, hereinafter referred to as TSOP).

In the TSOP, a chip 24, an insulating tape 27, and a resin sealing body 40 for resin-sealing the group of inner leads 17 are formed in a flat plate shape having a rectangular plan view, and the outer leads 18 connected to the inner leads 17 respectively. Are protruded from the pair of side surfaces on the long side and bent into a gull wing shape.
A plurality of warp prevention leads 20 for preventing warping of the resin sealing body 40 are laid in parallel with the chip 24 on both side portions of the resin sealing body 40 on the short side of the chip 24. The side portion of the chip 24 of the sealing body 40 is substantially divided into two equal parts in the thickness direction by the warp prevention leads 20 group.
Each warpage prevention lead 20 has a bent portion 20a formed by bending an intermediate portion into a crank shape.
Further, the warpage prevention leads 20 group are distributed on both the left and right sides with respect to the resin flow line of the resin sealing body 40, and the gap 21 between the tips of the warpage prevention leads 20, 20 facing each other forms a maze. Are laid like so.

  A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described below. The details of the above-described configuration of the semiconductor device will be clarified by this description.

The semiconductor device manufacturing method uses the multiple lead frame 11 shown in FIGS. 2 and 3A, 3B, and 3C. The multiple lead frame 11 is a multiple lead frame. Manufactured in the molding process.
3A is a side cross-sectional view taken along line aa in FIG. 2, FIG. 3B is a front cross-sectional view taken along line bb in FIG. 2, and FIG. 3C is cc in FIG. It is front sectional drawing which follows a line.
The multiple lead frame 11 is made of a thin plate made of a spring material having a relatively large mechanical strength, such as an iron-nickel alloy or phosphor bronze, and is integrally formed by punching press processing or etching processing.
A plating film (not shown) using silver (Ag) or the like is partially or wholly applied to the surface of the multiple lead frame 11 so that wire bonding described later is properly performed.
In the multiple lead frame 11, a plurality of unit lead frames 12 are arranged in a row in the horizontal direction. However, only one unit is shown for convenience.

The unit lead frame 12 includes a pair of outer frames 13 each having a positioning hole 13a. Both outer frames 13 and 13 are arranged in parallel at a predetermined interval and extend in series.
Between adjacent unit lead frames 12 and 12, a pair of section frames 14 and 14 are arranged between the outer frames 13 and 13 so as to be parallel to each other. A unit lead frame 12 is formed in a rectangular frame (frame) formed by the frames 14 and 14.
A chip placement portion 15 for placing a chip is set at a central portion of the unit lead frame 12 so that a planar view corresponding to a chip to be described later is rectangular.

A pair of dam members 16, 16 are installed between the outer frames 13, 13 in parallel inside the section frames 14, 14.
A plurality of inner leads 17 are provided on the inner end sides of both dam members 16, 16 so as to be integrally projected in the longitudinal direction so as to be orthogonal to the dam member 16. Each of the 17 groups is arranged in parallel to the long side of the chip placement portion 15, and the inner end portion is aligned right above the chip placement portion 15.
As shown in FIGS. 3A, 3 </ b> B, and 3 </ b> C, the inner end portion of each inner lead 17 that is disposed directly above the chip placement portion 15 is oriented in the direction of the chip placement portion 15 (hereinafter referred to as “chip placement portion 15”). The tip lowering portion 17a corresponding to a so-called tab lowering portion is formed at each end portion.

On the other hand, the same number of outer leads 18 as the inner leads 17 are arranged on the outer side edge of the dam member 16 so as to face the inner leads 17 and project integrally with the inner leads 17. ing. The outer end of each outer lead 18 is connected to the section frame 14.
A portion between the adjacent outer leads 18, 18 in the dam member 16 substantially constitutes a dam 16 a that blocks the flow of the resin when a resin sealing body is formed as described later.

A plurality of suspension leads 19 are provided in the central portion of the inner end sides of the outer frames 13 and 13 respectively in a perpendicular direction (hereinafter referred to as the front-rear direction) and face each other on the outer frame 13 side. Three warp prevention leads 20 are laid in the middle part of the pair of suspension leads 19 and 19 so as to face each other, and project in a right angle direction (hereinafter, referred to as a left-right direction).
Appropriate gaps 21 are formed between the tips of the left and right warping prevention leads 20, 20 facing each other, and these three gaps 21, 21, 21 arranged in the front-rear direction constitute a maze. Arranged in a staggered pattern.
Further, as shown in FIGS. 3A, 3B, and 3C, the tip portion of each warpage preventing lead 20 is formed by bending the descending portion 20a downward into a crank shape. Therefore, the height of the descending portion 20a is set to be approximately equal to the height of the chip in the chip placement portion 15.

  The distal end portion of each suspension lead 19 is disposed in the vicinity of the short side of the chip placement portion 15, thereby forming the outer inner lead portion 22. Each suspension lead 19 is connected to an inner lead 17 positioned on the outermost side in the front-rear direction by a connecting portion 23. Accordingly, the outer inner lead portions 22 are electrically connected to the inner leads 17 respectively.

In the multiple lead frame 11 having the above-described configuration, the chip 24 shown in FIGS. 4A, 4B, and 4C is formed in the chip bonding process as shown in FIGS. b) Chip bonding as shown in (c), followed by wire bonding in a wire bonding process.
The chip bonding operation and the wire bonding operation are sequentially performed for each unit lead frame by pitch-feeding the multiple lead frames in the horizontal direction.

A chip 24 shown in FIGS. 4A, 4B, and 4C is a semiconductor integrated circuit structure in which an integrated circuit including a DRAM element is formed in a so-called pre-process in a semiconductor device manufacturing process. As shown in FIG. 4A, it is formed in a rectangular flat plate shape.
As shown in FIGS. 4B and 4C, a protective film 25 is deposited on the main surface (hereinafter referred to as the upper surface) of the chip 24 on the active area side. A large number of bonding pads (hereinafter referred to as pads) 26 electrically connected to the active area, and each inner lead along a center line parallel to the long side as shown in FIG. 17 are arranged and exposed so as to face each other.
On both sides of the pad 26 group row on the upper surface of the protective film 25, a plurality of insulating tapes 27 as insulating layers are arranged and attached so as to correspond to the group row of chip lowering portions 17 a of the inner leads 17. .
The insulating tape 27 may be attached to the inner lead 17 side.

The chip 24 configured as described above is arranged in the chip arrangement part 15 of the unit lead frame 12 as shown in FIG. 5, and is shown on the lower surface of the chip lowering part 17 a of the inner lead 17 by the insulating tape 27. 6 Bonded as shown in (a), (b), (c). Since the chip 24 is bonded to the lower surface of the chip lowering portion 17a, the upper surface of the chip 24 is in a state of being lowered from the inner lead 17, that is, the lower surface of the unit lead frame 12.
Further, the lowered portion 20 a of each warpage preventing lead 20 is substantially equal to the height of the chip 24.

Subsequently, in the wire bonding step, a bonding wire 28 is provided between each pad 26 of each chip 24 and each inner lead 17 and outer inner lead portion 22, and a wire bonding apparatus (such as an ultrasonic thermocompression type wire bonding apparatus). (Not shown) is used, and both ends thereof are bonded and bridged.
As a result, the integrated circuit built in the chip 24 is electrically drawn out via the pad 26, the bonding wire 28, the inner lead 17 and the outer lead 18.

  The resin-sealed body is shown in FIGS. 7A, 7B, and 7C in the assembly 29 shown in FIGS. 5 and 6 that has been chip-bonded and wire-bonded as described above. The transfer molding apparatus 30 is used to mold the unit lead frames 12 at the same time.

The transfer molding apparatus 30 shown in FIGS. 7A, 7B, and 7C includes a pair of upper mold 31 and lower mold 32 that are clamped together by a cylinder apparatus or the like (not shown). The upper mold cavity recess 33a and the lower mold cavity recess 33b cooperate with each other to form a rectangular flat plate-shaped cavity 33 on the mating surface of the upper mold 31 and the lower mold 32. Each of them is buried in multiple sets. That is, the upper mold cavity recess 33a and the lower mold cavity recess 33b are formed in a shallow hole shape having a substantially rectangular bottom when viewed from the top.
In the present embodiment, the total height of the cavity 33 is set to 1 mm or less in order to correspond to TSOP.

A pot 34 is opened on the mating surface of the upper mold 31, and a plunger 35 that is advanced and retracted by a cylinder device (not shown) feeds resin (hereinafter referred to as resin) as a molding material to the pot 34. Has been inserted so that it can.
On the mating surface of the lower mold 32, a cull 36 is disposed at a position opposite to the pot 34 and is submerged, and a plurality of runners 37 are arranged radially and submerged so as to be connected to the cull 36, respectively. ing.
The other end of each runner 37 is connected to one short side of the lower cavity recess 33 b, and a gate 38 is formed at the connection so that the resin can be injected into the cavity 33. .

  At the time of transfer molding, the assembly 29 according to the above configuration is arranged and set so that the chip 24 in each unit lead frame 12 is accommodated in each cavity 33.

Subsequently, the upper mold 31 and the lower mold 32 are clamped as shown in FIG. 7, and the resin 39 is fed from the pot 34 by the plunger 35 to the respective cavities 33 through the runner 37 and the gate 38 and press-fitted. Is done.
As shown in FIG. 7A, the resin 39 that has flowed into the cavity 33 from the gate 38 moves up and down the cavity 33 by the rectifying plate action of the group of warping prevention leads 20 located near the gate 38. Since they are distributed, they circulate evenly in the upper space and the lower space of the cavity 33.

At this time, if the three gaps 21 formed by the left and right warp prevention leads 20 and 20 are aligned on a straight line, the three resins 39 that have reached the group of warp prevention leads 20 are aligned on the straight line. Therefore, the current plate action of the warp preventing lead group 20 is not effectively implemented.
However, in the present embodiment, since the three gaps 21 are arranged in a staggered manner so as to form a maze, as shown in FIG. 7C, the lead 20 group for warpage prevention has been reached. The resin 39 is in a state where it flows through the maze without passing in a straight line, and the rectifying plate action of the group of warping preventing leads 20 is effectively implemented.

After the injection, when the resin is thermoset and the resin sealing body 40 is molded, the upper mold 31 and the lower mold 32 are opened, and the resin sealing body 40 group is formed by ejector pins (not shown). Mold is released.
In this way, as shown in FIGS. 8 and 9, the molded product 41 in which the resin sealing body 40 group is molded is detached from the transfer molding device 30.
Then, the inner lead 17, the warp prevention lead 20, the chip 24, the insulating tape 27, and the bonding wire 28 are resin-sealed inside the resin-sealed body 40 that is resin-molded in this way.
In the present embodiment, the warpage preventing lead 20 has a lowered portion 20 a inside the resin sealing body 40 and substantially coincides with the upper surface of the chip 24.
FIG. 8 is a partially cut-away plan view of the molded product 41 after resin sealing, with partial omission. FIG. 9A is a side sectional view taken along the line aa in FIG. FIG. 9B is a front sectional view taken along the line bb in FIG. 8, and FIG. 9C is a front sectional view taken along the line cc in FIG.

By the way, since the resin sealing body 40 shrinks toward the center when it is thermoset, the resin sealing body 40 is caused by the difference in the upper / lower ratio of the resin thickness or the difference in the vertical structure inside the resin sealing body 40. Causes warping.
As shown in FIG. 10A, when the warp preventing lead is not disposed on the side portion of the chip 24, even if the chip 24 is disposed at the upper and lower central portions. Since a large volume portion is formed in the side portion of the chip 24 in the resin sealing body 40, a large contraction force is generated as shown by the broken line arrow in FIG. A warp in which the upper side expands and the lower side contracts in that portion of the stationary body 40 occurs as indicated by an imaginary line.

However, in this embodiment, the group 20 of warp preventing leads is disposed on the side portion of the chip 24, so that the side portion of the chip 24 in the resin sealing body 40 is shown in FIG. Since the volume is divided up and down as shown in FIG. 10B, the contraction force is dispersed as shown by broken line arrows in FIG. The occurrence of warping that expands and shrinks the lower side is prevented.
In addition, since the warpage prevention lead 20 is formed so that the lowered portion 20a is substantially flush with the upper surface of the chip 24, the side portion of the chip 24 in the resin sealing body 40 is divided into two equal parts. Therefore, the occurrence of a warp in which the upper side is enlarged and the lower side is contracted in the portion of the resin sealing body 40 is more reliably prevented.
In other words, warpage due to resin shrinkage in the portion is reduced, and the occurrence of warpage is completely prevented.

  In the present embodiment, since the chip lowering portion 17 a is formed on the inner lead 17, the chip 24 is disposed at the central portion of the height of the resin sealing body 40. Even in the central portion where the chip 24 is located, the occurrence of warpage is prevented. Therefore, the resin sealing body 40 maintains a flat state with no warpage throughout.

A molded product 41 as a semi-finished product obtained by molding the resin sealing body 40 without warping as described above is provided with the outer frame 13 and the dam 16a for each unit lead frame in a lead cutting molding process (not shown). While being cut off, each outer lead 18 is bent into a gull wing shape.
As a result, the semiconductor device 42 shown in FIG. 1 is manufactured.

According to the embodiment described above, the following effects can be obtained.
1) Since a warp prevention lead is laid on both sides of the chip inside the LOC resin sealing body, the resin sealing body can be prevented from warping. It is possible to prevent the occurrence of poor performance such as poor appearance and moisture resistance due to warpage.

2) By preventing the resin sealing body from warping, it is possible to prevent peeling of the outer lead from the land when the TSOP is printed circuit board.

3) Since the warpage preventing lead for preventing the resin sealing body from warping can be formed integrally with the lead frame, an increase in manufacturing cost can be avoided.

4) By preventing warping of the resin sealing body, it is possible to reduce product transportation troubles after the resin sealing body molding process. The productivity of the semiconductor device can be increased.

  Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor.

  For example, the warp prevention leads are not limited to three, but may be one, two, or four or more.

  The external structure is not limited to TSOP, but it is a surface mount type resin seal such as normal SOP, SOJ (Small Outline J Lead Package), TSOJ, SOI (Small Outline I Lead Package), TSOI, etc. You may comprise a package and also an insertion type resin sealing package.

  In the above description, the case where the invention made by the present inventor is mainly applied to the DRAM, which is the field of use behind it, has been mainly described. However, the present invention is not limited thereto, and other ICs, transistor arrays, etc. It can be applied to all semiconductor devices.

BRIEF DESCRIPTION OF THE DRAWINGS The semiconductor device which concerns on one embodiment of this invention is shown, (a) is a partially cutaway plan view, (b) is a partially abbreviated side sectional view along the bb line of (a). 1 is a partially omitted plan view showing a lead frame used in a semiconductor device manufacturing method according to an embodiment of the present invention; 2A is a side sectional view taken along line aa in FIG. 2, FIG. 2B is a front sectional view taken along line bb in FIG. 2, and FIG. 2C is a front sectional view taken along line cc in FIG. It is. The chip | tip is shown similarly, (a) is a top view, (b) is front sectional drawing which follows the bb line of (a), (c) is side sectional drawing which follows the cc line of (a). is there. It is a partially-omission plan view showing a chip and a wire bonding step in the method for manufacturing a semiconductor device according to an embodiment of the present invention. 5A is a side sectional view taken along line aa in FIG. 5, FIG. 5B is a front sectional view taken along line bb in FIG. 5, and FIG. 5C is a front sectional view taken along line cc in FIG. It is. The molding process of the resin sealing body is also shown, (a) is a partially omitted side cross-sectional view, (b) is a cross-sectional view taken along line bb of (a), and (c) is c of (a). It is a partial plane sectional view which meets a -c line. It is a partially-omitted partially cut plan view showing a molded product after resin sealing body molding. 8A is a side sectional view taken along line aa in FIG. 8, FIG. 8B is a front sectional view taken along line bb in FIG. 8, and FIG. 8C is a front sectional view taken along line cc in FIG. It is. It is side surface sectional drawing for demonstrating the curvature of the resin sealing body, (a) has shown the case of the comparative example, (b) has shown the case of embodiment, respectively.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Multiple lead frame, 12 ... Unit lead frame, 13 ... Outer frame, 14 ... Section frame, 15 ... Chip placement part, 16 ... Dam member, 16a ... Dam, 17 ... Inner lead, 17a ... Chip lowering part, 18 DESCRIPTION OF SYMBOLS ... Outer lead, 19 ... Suspension lead, 20 ... Warp prevention lead, 20a ... Lower part, 21 ... Gap, 22 ... Outer inner lead part, 23 ... Connection part, 24 ... Chip, 25 ... Protective film, 26 ... Bonding pad, 27 ... Insulating tape (insulating layer), 28 ... Bonding wire, 29 ... Assembly, 30 ... Transfer molding device, 31 ... Upper mold, 32 ... Lower mold, 33 ... Cavity, 33a ... Upper mold cavity recess, 33b ... Lower mold cavity recess, 34 ... pot, 35 ... plunger, 36 ... cal, 37 ... runner, 38 ... gate, 39 ... resin, 40 ... resin sealing body, 1 ... moldings, 42 ... semiconductor device.

Claims (3)

A semiconductor chip and a semiconductor device manufacturing method in which a plurality of inner leads electrically connected to the semiconductor chip are resin-sealed by a rectangular resin sealing body,
In the molding step of the resin sealing body, the warp prevention leads that are laid on both sides of the semiconductor chip of the resin sealing body and prevent the resin sealing body from warping are rectangular frames of the lead frame. A method for manufacturing a semiconductor device, wherein the semiconductor device is connected to a body in both a vertical direction and a horizontal direction.   The method of manufacturing a semiconductor device according to claim 1, wherein a connecting portion between the warpage preventing lead and the frame body is cut after the molding of the resin sealing body.   The method of manufacturing a semiconductor device according to claim 1, wherein the warpage preventing lead is formed integrally with the inner lead.

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