JP2005222198A - Data transferring device and data transferring method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data transferring device and a data transferring method for reducing a load at interrupting processing. <P>SOLUTION: This data transferring device 100 is provided with a CPU 102 connected to a bus 120 which controls each device, a memory 104 which temporarily stores data to be transferred with an external device 150, and stores data transfer control information, a device controller 106 which controls data transfer with the external device 150, an input part 108 which inputs a signal from the outside through an interface other than the device controller 106, an output part 110 which outputs the signal through the interface to the outside other than the device controller 106 and a processing part 112 which performs interrupting processing instead of the CPU 102. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a data transfer apparatus that performs data transfer with a device outside the apparatus, and a data transfer method in the data transfer apparatus.

  Conventionally, a data transfer device has been proposed for reducing the load on devices and buses inside the device during data transfer (for example, Patent Document 1). This conventional data transfer apparatus is configured as shown in FIG. In FIG. 5, a data transfer apparatus 500 performs data transfer with a device (external device) 550 outside the apparatus, and includes a CPU (Central Processing Unit) 502, a memory 504, and a device controller 506 connected to a bus 520. , An input unit 508 and an output unit 510.

  When transferring data to or from the external device 550, the CPU 502 accesses a register in the device controller 506 and writes data transfer control information, which is information relating to data transfer, to the memory 504. The device controller 506 reads the data transfer control information written in the memory 504, and performs data transfer with the external device 550 according to the data transfer control information. Thereby, for example, data input by the input unit 508 is transferred to the external device 550, and data from the external device 550 is output to the output unit 510.

  In such a data transfer procedure, when data transfer is completed or fails, the device controller 506 sends an interrupt signal to the CPU 502. When receiving an interrupt signal, the CPU 502 issues various instructions to the device controller 506 in accordance with an interrupt status indicating the priority of the interrupt signal.

Alternatively, if devices can directly transfer data without going through the CPU, the load on the CPU and the bus to which the CPU is connected can be reduced, and safe and efficient data transfer can be performed ( For example, see Patent Documents 2 to 4.)
JP 11-345192 A Japanese Patent Laid-Open No. 10-312633 JP 2000-122969 A JP 2000-242603 A

  However, in various conventionally proposed data transfer apparatuses, no consideration is given to reducing the load on the CPU when interrupt processing occurs. That is, in the conventional data transfer apparatus as described above (see FIG. 5), the data transfer control by the CPU is necessary at the time of interrupt processing, which hinders the reduction of the load.

  The present invention has been made to solve the conventional problems, and an object of the present invention is to provide a data transfer apparatus and a data transfer method that reduce the load during interrupt processing.

  The data transfer apparatus of the present invention controls the data transfer between the internal device control means for controlling the devices inside the apparatus and the devices outside the apparatus, and sends an interrupt signal to the inside of the apparatus when the need for interrupt processing occurs. An external device control means for sending, and an interrupt processing means for performing an interrupt process corresponding to the interrupt signal in place of the internal device control means when an interrupt signal is sent by the external device control means; Become.

  With this configuration, when an interrupt signal is sent by an external device control unit that controls data transfer with a device outside the apparatus, the interrupt processing unit generates an interrupt corresponding to the interrupt signal instead of the internal device control unit. Processing is performed.

  In the data transfer apparatus according to the present invention, the internal device control unit notifies the interrupt processing unit of an interrupt processing procedure corresponding to the interrupt signal, and the interrupt processing unit receives the interrupt processing unit from the internal device control unit. According to the interrupt processing procedure corresponding to the interrupt signal, the interrupt processing corresponding to the interrupt signal can be performed.

  With this configuration, the interrupt processing means can easily recognize the interrupt processing procedure corresponding to the interrupt signal, and can perform appropriate interrupt processing.

  In the data transfer apparatus of the present invention, the interrupt processing unit performs access to the register in the external device control unit and updates information related to data transfer control stored in the storage unit in the apparatus. be able to.

  With this configuration, the interrupt processing unit can appropriately perform the interrupt processing originally performed by the internal device control unit instead of the internal device control unit.

  In the data transfer apparatus of the present invention, the transmission path to which the internal device control means is connected and the transmission path to which the external device control means and the interrupt processing means are connected can be different.

  With this configuration, signals exchanged between the interrupt processing unit and the external device control unit during interrupt processing can be prevented from being transmitted through the transmission path to which the internal device control unit is connected. It is possible to reduce the load on the transmission line to which the means is connected.

  Further, the data transfer method of the present invention includes an internal device control means for controlling devices inside the apparatus, an external device control means for controlling data transfer between devices outside the apparatus, an interrupt processing means for performing interrupt processing, In the data transfer method in the data transfer apparatus having an interrupt signal, the external device control means sends an interrupt signal to the inside of the apparatus when an interrupt process is required in the data transfer with the device outside the apparatus And an interrupt processing step for performing interrupt processing corresponding to the interrupt signal instead of the internal device control means when the interrupt processing means is sent by the external device control means. Become.

  Further, the data transfer method of the present invention has a processing procedure notification step in which the internal device control means notifies the interrupt processing means of an interrupt processing procedure corresponding to the interrupt signal. The interrupt processing unit may perform an interrupt process corresponding to the interrupt signal in accordance with an interrupt process procedure corresponding to the interrupt signal from the internal device control unit.

  In the present invention, when an interrupt signal is sent by an external device control unit that controls data transfer with a device outside the apparatus, the interrupt processing unit performs processing corresponding to the interrupt signal instead of the internal device control unit. It is possible to reduce the load on the internal device control means such as the CPU.

Hereinafter, a data transfer apparatus according to an embodiment of the present invention will be described with reference to the drawings.
First, a first embodiment of the present invention will be described. FIG. 1 shows a block diagram of a data transfer apparatus according to the first embodiment of the present invention. In FIG. 1, a data transfer apparatus 100 performs data transfer with a device (external device) 150 outside the apparatus, and includes a CPU 102, a memory 104, a device controller 106, an input unit 108, an output unit 110, and interrupt processing. Part 112.

  The CPU 102, the memory 104, the device controller 106, the input unit 108, the output unit 110, and the interrupt processing unit 112 are connected to the bus 120. The bus 120 transmits control information and data exchanged between the connected devices.

  The CPU 102 controls each device in the data transfer apparatus 100. The memory 104 temporarily stores data exchanged between the data transfer apparatus 100 and the external device 150, and stores data transfer control information referred to when the device controller 106 performs data transfer. The device controller 106 is connected to the external device 150 and controls data transfer with the external device 150. The input unit 108 inputs continuous signal data such as a video signal and an audio signal through an interface other than the device controller 106. The output unit 110 is a monitor, for example, and outputs a signal to the outside through an interface other than the device controller 106. The interrupt processing unit 112 performs interrupt processing in place of the CPU 102.

  In the present embodiment, a PCI (Peripheral Component Interconnect) bus is assumed as the bus 120. Also, a USB (Universal Serial Bus) widely used for connecting external devices is assumed as the device controller 106, and an external device having a USB interface is assumed as the external device 150.

  In the present embodiment, it is assumed that all data transfer between each device in the data transfer apparatus 100 and the external device 150 is performed via the memory 104. That is, for example, when data transfer from the input unit 108 to the external device 150 is performed, data transfer from the input unit 108 to the memory 104 and data transfer from the memory 104 to the external device 150 are performed. When data transfer from the external device 150 to the output unit 110 is performed, data transfer from the external device 150 to the memory 104 and data transfer from the memory 104 to the output unit 110 are performed.

  The operation of the data transfer apparatus 100 configured as described above will be described with reference to FIG. Note that FIG. 2 illustrates a case where data transfer from the input unit 108 to the external device 150 is performed.

  First, prior to data transfer, the CPU 102 notifies the interrupt processing unit 112 of an interrupt processing procedure (S10). The interrupt processing unit 112 receives and holds this interrupt processing procedure. This interrupt processing procedure shows a procedure of interrupt processing that is performed when the interrupt processing unit 112 receives an interrupt signal.

  Thereafter, the CPU 102 issues a data transfer command to the input unit 108. The input unit 108 transfers data to the memory 104 in accordance with this command (S11). The memory 104 temporarily holds the transferred data.

  Next, the CPU 102 accesses the register of the device controller 106 in order to transfer the data temporarily stored in the memory 104 to the external device 150 (S12), and writes the data transfer control information in the memory 104 (S13). The data transfer control information includes information related to data transfer control, such as a transfer destination of data to be transferred by the device controller 106.

  Next, the CPU 102 issues a data transfer command to the device controller 106. Upon receiving this instruction, the device controller 106 acquires the control right of the bus 120 from the CPU 102. Furthermore, the device controller 106 reads data from the memory 104 and data transfer control information corresponding to the data, and performs processing necessary for transferring data to the external device 150 according to the data transfer control information ( S14).

  Thereafter, the device controller 106 determines whether interrupt processing is necessary (S15). Specifically, the device controller 106 monitors the status of data transfer to the external device 150, and determines that interrupt processing is necessary when the data transfer is completed or failed. If the device controller 106 determines that interrupt processing is necessary, it sends an interrupt signal to the bus 120 (S16). The interrupt signal sent to the bus 120 can reach each device connected to the bus 120.

  When receiving the interrupt signal, the interrupt processing unit 112 performs interrupt processing according to the interrupt processing procedure notified from the CPU 102 in S10. Here, the interrupt process performed by the interrupt processing unit 112 is essentially the same as the interrupt process performed when the CPU 102 receives an interrupt signal from the device controller 106. Specifically, the interrupt processing unit 112 acquires the control right of the bus 120 from the CPU 102, accesses the register of the device controller 106 (S17), and updates the data transfer control information in the memory 104 (S18). ).

  After the interrupt process by the interrupt processing unit 112, the CPU 102 determines whether or not there is a next data transfer process (S19). When there is a next data transfer process, the operation after the access (S12) to the register of the device controller 106 by the CPU 102 is repeated. On the other hand, when there is no next data transfer process, a series of operations are completed.

  When data transfer from the external device 150 to the output unit 110 is performed, the following processing is performed instead of the processing of S11 to S14 described above. That is, the CPU 102 accesses a register of the device controller 106 and writes data transfer control information in the memory 104 in order to temporarily store data from the external device 150 in the memory 102. Further, the CPU 102 issues a data transfer command to the device controller 106. The device controller 106 performs processing necessary for reading data from the external device 150 in accordance with the data transfer control information read from the memory 104 according to this command, and writes the read data to the memory 104. Thereafter, the CPU 102 issues a data transfer command to the output unit 110, and the output unit 110 reads and outputs data from the memory 104 according to this command.

  As described above, according to the first embodiment of the present invention, when the device controller 106 sends an interrupt signal to the bus 120 in data transfer with the external device 150, the interrupt processing unit 112 Interrupt processing is performed in place of the CPU 102. For this reason, the CPU 102 does not need to perform interrupt processing, and the load on the CPU 102 can be reduced.

  In particular, when a load close to the upper limit of the processing capacity of the CPU 102 is generated, the interrupt processing unit 112 performs the interrupt process instead of the CPU in this way, so that the load of the CPU 102 becomes the upper limit of the processing capacity. Can be prevented. Conventionally, depending on the interrupt status corresponding to the interrupt signal, the CPU 102 may continue other processing and may not perform the interrupt processing until the processing is completed. Since only interrupt processing is performed in place of the CPU 102, quick interrupt processing is possible.

  Further, according to the first embodiment of the present invention, the interrupt processing unit 112 receives an interrupt processing procedure notified from the CPU 102, and accesses the register of the device controller 106 and the memory 104 in accordance with the interrupt processing procedure. The data transfer control information is updated, and the interrupt processing unit 112 easily recognizes the interrupt processing procedure corresponding to the interrupt signal, and appropriately performs the interrupt processing originally performed by the CPU 102 on behalf of the CPU 102. Can do.

  Next, a second embodiment of the present invention will be described. FIG. 3 shows a block diagram of a data transfer apparatus according to the second embodiment of the present invention. In FIG. 3, a data transfer apparatus 200 performs data transfer with a device (recording device) 400 outside the apparatus, and includes a CPU 210, a CPU control device 211, a spool buffer memory 212, a memory 213, a device controller 220, A data transfer control unit 230, an input unit 240, and an output unit 250 are included.

  Among these, the CPU 210, the CPU device control unit 211, and the data transfer control unit 230 are connected to the bus 300. The bus 300 transmits control information and data exchanged among the connected CPU 210, CPU device control unit 211, and data transfer control unit 230. The device controller 220 and the data transfer control unit 230 are connected to a bus 301, and the bus 301 transmits control information and data exchanged between the device controller 220 and the data transfer control unit 230. As described above, the CPU 210 and the CPU device control unit 211 are connected to the data transfer control unit 230 via the bus 300, the device controller 220 is connected to the data transfer control unit 230 via the bus 301, the spool buffer memory 212, and the memory 213. The input unit 240 and the output unit 250 are connected.

  The CPU 210 controls the CPU control device 211 and the data transfer control unit 230 connected to the bus 300. The spool buffer memory 212 temporarily stores data exchanged between the data transfer apparatus 200 and the external device 400. The memory 213 stores data transfer control information that is referred to when the device controller 220 performs data transfer. The device controller 220 is connected to the external device 400 and controls data transfer with the external device 400. The input unit 240 inputs continuous signal data such as a video signal and an audio signal from an external interface through an interface other than the device controller 220. The output unit 250 is a monitor, for example, and outputs a signal to the outside through an interface other than the device controller 220.

  The data transfer control unit 230 controls data transfer between each device in the data transfer apparatus 200 and the external device 400. The data transfer control unit 230 includes a CPU interface (I / F) unit 231 connected to the CPU 210 via the bus 300, a memory interface (I / F) unit 232 connected to the memory 213, and the bus 301. Device controller interface (I / F) unit 233 connected to device controller 220, spool buffer memory interface unit (I / F) unit 234 connected to spool buffer memory 212, and input connected to input unit 240 Interface (I / F) unit 235, output interface (I / F) unit 236 connected to output unit 250, CPU I / F unit 231, memory I / F unit 232, device controller I / F unit 233, input I / F unit 235, output I / F unit 236, and spool buffer memory Arbitrates the data transfer between the 12, and a arbiter 237 having a function that enables data transfer at a defined rate.

  Among these, the CPU I / F unit 231, the device controller I / F unit 233, the spool buffer I / F unit 234, the input I / F unit 235 and the output I / F unit 236 are connected to the control bus 310 and the data bus 320. Has been. The arbiter unit 237 is configured on the control bus 310. Further, the CPU I / F unit 231 and the memory I / F unit 232 are connected to the control bus 311 and the data bus 321, and the memory I / F unit 232 and the device controller I / F unit 233 are connected to the control bus 312 and the data bus 322. It is connected to the.

  In the present embodiment, PCI buses are assumed as the buses 300 and 301 as in the first embodiment. In addition, a USB widely used for connecting external devices is assumed as the device controller 220, and an external device having a USB interface is assumed as the external device 400.

  Further, in this embodiment, it is assumed that data transfer between each device in the data transfer apparatus 200 and the external device 400 is all performed via the spool buffer memory 212. That is, for example, when data transfer from the input unit 240 to the external device 400 is performed, data transfer from the input unit 240 to the spool buffer memory 212 and data transfer from the spool buffer memory 212 to the external device 400 are performed. Done. When data transfer from the external device 400 to the output unit 250 is performed, data transfer from the external device 400 to the spool buffer memory 212 and data transfer from the spool buffer memory 212 to the output unit 250 are performed. .

  The operation of the data transfer apparatus 200 configured as described above will be described with reference to FIG. FIG. 4 illustrates a case where data transfer from the input unit 240 to the external device 400 is performed.

  First, prior to data transfer, the CPU 210 notifies the device controller I / F unit 233 of an interrupt processing procedure via the CPU I / F unit 213 in the data transfer control unit 230 (S20). The device controller I / F unit 233 in the data transfer control unit 230 receives and holds this interrupt processing procedure.

  Thereafter, the CPU 210 issues a data transfer command to the input unit 240 via the CPU I / F unit 213 and the input I / F unit 235 in the data transfer control unit 230. In accordance with this instruction, the input unit 240 transfers data to the spool buffer memory 212 via the input I / F unit 235 and the spool buffer I / F unit 234 in the data transfer control unit 230 (S21). The spool buffer memory 212 temporarily holds the transferred data.

  Next, the CPU 210 acquires the control right of the bus 301 from the device controller 220 (S22), and transfers the data temporarily stored in the spool buffer memory 212 to the external device 400 in order to transfer the CPUI in the data transfer control unit 230. The register of the device controller 220 is accessed via the / F unit 231 and the device controller I / F unit 233 (S23). After this access is completed, the CPU 210 releases the control right of the bus 301 (S24). Further, the CPU 210 writes the data transfer control information to the memory 213 via the CPU I / F unit 231 and the memory I / F unit 232 in the data transfer control unit 230 (S25).

  Next, the CPU 210 issues a data transfer command to the device controller 220 via the CPU I / F unit 231 and the device controller I / F unit 233 in the data transfer control unit 230. Upon receiving this command, the device controller 220 reads data from the spool buffer memory 212 via the device controller I / F unit 233 and the spool buffer I / F unit 234 in the data transfer control unit 230, and at the same time, reads the device controller I / F. Data transfer control information corresponding to the data read from the spool buffer memory 212 is read from the memory 213 via the F unit 233 and the memory I / F unit 232. Further, the device controller 220 performs processing necessary for transferring the data read from the spool buffer memory 212 to the external device 400 in accordance with the data transfer control information read from the memory 213 (S26).

  Thereafter, the device controller 220 determines whether or not an interrupt process is necessary (S27). Specifically, as in the first embodiment described above, the device controller 220 monitors the status of data transfer to the external device 400, and when the data transfer is completed or fails, interrupt processing is performed. Is determined to be necessary. If the device controller 220 determines that interrupt processing is necessary, it sends an interrupt signal to the bus 301 (S28). The interrupt signal sent to the bus 301 can reach the data transfer control unit 230 connected to the bus 301.

  When the data transfer control unit 230 receives an interrupt signal from the device controller I / F unit 233, the data transfer control unit 230 performs interrupt processing according to the interrupt processing procedure notified from the CPU 210 in S20. Here, the interrupt processing performed by the data transfer control unit 230 is essentially the same as the interrupt processing performed when the CPU 210 receives an interrupt signal from the device controller 220. Specifically, the data transfer control unit 230 obtains the control right of the bus 301 from the device controller 220, accesses the register of the device controller 220 (S30), and grants the bus control right after the access is completed. The data transfer control information in the memory 213 is updated (S32).

  After the interrupt process by the data transfer control unit 230, the CPU 210 determines whether or not there is a next data transfer process (S33). When there is a next data transfer process, the operation after the acquisition of the control right of the bus 301 by the CPU 210 (S22) is repeated. On the other hand, when there is no next data transfer process, a series of operations are completed.

  When data transfer from the external device 400 to the output unit 250 is performed, the following processing is performed instead of the processing of S21 to S26 described above. That is, the CPU 210 accesses a register of the device controller 220 and writes data transfer control information in the memory 213 in order to temporarily store data from the external device 400 in the spool buffer memory 212. Further, the CPU 210 issues a data transfer command to the device controller 220. In accordance with this command, the device controller 220 performs processing necessary for reading data from the external device 400 according to the data transfer control information read from the memory 213, and writes the read data to the spool buffer memory 212. Thereafter, the CPU 210 issues a data transfer command to the output unit 250, and the output unit 250 reads and outputs data from the spool buffer memory 212 in accordance with this command.

  As described above, according to the second embodiment of the present invention, when the device controller 220 sends an interrupt signal to the bus 301 in data transfer with the external device 400, the data transfer control unit 230 In place of the CPU 210, interrupt processing is performed. For this reason, as in the first embodiment, the CPU 210 does not need to perform interrupt processing, thereby reducing the load on the CPU 210 and enabling quick interrupt processing.

  Further, the data transfer control unit 230 receives the interrupt processing procedure notified from the CPU 210, and accesses the register of the device controller 220 and updates the data transfer control information in the memory 213 according to the interrupt processing procedure. As in the first embodiment, the interrupt processing procedure corresponding to the interrupt signal can be easily recognized, and the interrupt processing originally performed by the CPU 210 can be appropriately performed in place of the CPU 210.

  Further, according to the second embodiment of the present invention, a signal exchanged between the data transfer control unit 230 and the device controller 220 during interrupt processing is transmitted only through the bus 301 and is connected to the CPU 210. Since the data is not transmitted to 300, the load on the bus 300 can be reduced.

  In the first and second embodiments described above, a PCI bus is assumed as the buses 120, 300, and 301. However, any bus that can transmit control information and data may be used. Further, a plurality of input units 108 and 240 and output units 110 and 250 may be configured.

  As described above, the data transfer apparatus and the data transfer method according to the present invention have an effect that the load on the internal device control means such as a CPU can be reduced, and data between devices outside the apparatus is obtained. The present invention is useful as a data transfer apparatus and a data transfer method for performing transfer.

The block diagram of the data transfer apparatus in the 1st Embodiment of this invention Flowchart of the operation of the data transfer apparatus in the first embodiment of the present invention The block diagram of the data transfer apparatus in the 2nd Embodiment of this invention Flowchart of the operation of the data transfer apparatus in the second embodiment of the present invention Block diagram of a conventional data transfer device

Explanation of symbols

100, 200 Data transfer device 102, 210 CPU
104, 213 Memory 106, 220 Device controller 108, 240 Input unit 110, 250 Output unit 112 Interrupt processing unit 120, 300, 301 Bus 150, 400 External device 211 CPU control device 212 Spool buffer memory 230 Data transfer control unit 231 CPU I / F part 232 Memory I / F part 233 Device controller I / F part 234 Spool buffer I / F part 235 Input I / F part 236 Output I / F part 237 Arbiter part 310, 311, 312 Control bus 320, 321, 322 Data bus

Claims (6)

Internal device control means for controlling devices inside the apparatus;
External device control means for controlling data transfer with a device external to the device and sending an interrupt signal to the inside of the device when interrupt processing is necessary;
A data transfer apparatus comprising: interrupt processing means for performing interrupt processing corresponding to the interrupt signal in place of the internal device control means when an interrupt signal is transmitted by the external device control means. The internal device control means notifies the interrupt processing means of an interrupt processing procedure corresponding to the interrupt signal,
2. The data transfer apparatus according to claim 1, wherein the interrupt processing means performs interrupt processing corresponding to the interrupt signal in accordance with an interrupt processing procedure corresponding to the interrupt signal from the internal device control means. 3. The data according to claim 1, wherein the interrupt processing unit performs access to a register in the external device control unit and updates information related to data transfer control stored in a storage unit inside the apparatus. Transfer device. 4. The data transfer according to claim 1, wherein a transmission path to which the internal device control means is connected is different from a transmission path to which the external device control means and the interrupt processing means are connected. apparatus. In a data transfer method in a data transfer apparatus having internal device control means for controlling devices inside the apparatus, external device control means for controlling data transfer between devices outside the apparatus, and interrupt processing means for performing interrupt processing ,
An interrupt signal sending step for sending an interrupt signal to the inside of the device when the external device control means needs to perform interrupt processing in data transfer with the device outside the device;
An interrupt processing step for performing interrupt processing corresponding to the interrupt signal instead of the internal device control means when the interrupt processing means is sent out by the external device control means. Data transfer method. The internal device control means has a processing procedure notification step of notifying the interrupt processing means of an interrupt processing procedure corresponding to the interrupt signal;
6. The data transfer according to claim 5, wherein in the interrupt processing step, the interrupt processing means performs interrupt processing corresponding to the interrupt signal in accordance with an interrupt processing procedure corresponding to the interrupt signal from the internal device control means. Method.

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