JP2005217221A - Semiconductor package and method for manufacturing the same - Google Patents

Semiconductor package and method for manufacturing the same Download PDF

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JP2005217221A
JP2005217221A JP2004022557A JP2004022557A JP2005217221A JP 2005217221 A JP2005217221 A JP 2005217221A JP 2004022557 A JP2004022557 A JP 2004022557A JP 2004022557 A JP2004022557 A JP 2004022557A JP 2005217221 A JP2005217221 A JP 2005217221A
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semiconductor package
electromagnetic wave
sealing resin
resin layer
wave absorbing
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Norifumi Iwashita
典文 岩下
Kimihiro Tsuruzono
公博 鶴園
Hitoshi Shibue
人志 渋江
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Sony Corp
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Sony Corp
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor package for suppressing the deterioration of a yield due to a short defect, and for reducing manufacturing costs, and to provide a method for manufacturing the semiconductor package. <P>SOLUTION: This method for manufacturing a semiconductor package comprises a process for coating a semiconductor chip 2 with an electromagnetic wave absorbing mold resin layer 12 having an electromagnetic wave absorbing function, and a process for coating an electromagnetic wave absorbing mold resin with an epoxy resin layer 13. The electromagnetic wave absorbing mold resin layer is formed by a potting method, and an epoxy resin layer is formed by a transfer mold method. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は半導体パッケージ及びその製造方法に関する。詳しくは、電磁波吸収機能を有し、半導体素子を被覆する第1の封止樹脂層をポッティング法により形成することによって、ボンディングワイヤーと半導体素子とのショートやボンディングワイヤー同士のショートを抑制すると共にコスト低減を図ろうとした半導体パッケージ及びその製造方法に係るものである。   The present invention relates to a semiconductor package and a manufacturing method thereof. Specifically, the first sealing resin layer that has an electromagnetic wave absorption function and covers the semiconductor element is formed by a potting method, thereby suppressing a short circuit between the bonding wire and the semiconductor element and a short circuit between the bonding wires and a cost. The present invention relates to a semiconductor package to be reduced and a manufacturing method thereof.

近年、デジタルカメラやデジタルカムコーダー等の様々な商品でデジタル化が進み、それらの商品に使用される半導体部品もデジタルICの割合が多くなってきているが、これらデジタルICは高周波で動作するためにノイズ発生源となり、他の部品に誤動作を生じさせる等の悪影響を及ぼす。   In recent years, digitization has progressed in various products such as digital cameras and digital camcorders, and the proportion of digital ICs has also increased in the semiconductor components used in those products. However, these digital ICs operate at high frequencies. It becomes a source of noise and adversely affects other components.

そこでノイズ対策として、従来の半導体パッケージでは防磁シート等をノイズ発生源やノイズの影響を受けやすい部品に貼り付ける等の対策が施されていた(例えば、特許文献1参照。)。   Therefore, as countermeasures against noise, countermeasures such as attaching a magnetic shielding sheet or the like to a noise generation source or a component susceptible to noise have been taken in conventional semiconductor packages (for example, see Patent Document 1).

ところが、防磁シート等を貼り付けることによるノイズ対策では、防磁シート等の材料費や貼り付け作業工数等のために製品コストが高くなってしまう。   However, noise countermeasures by attaching a magnetic shielding sheet or the like increase the product cost due to the material cost of the magnetic shielding sheet or the like and the number of man-hours for attaching.

従って、最近では、半導体素子等のノイズ発生源やボンディングワイヤーや配線パターン等のノイズの影響を受けやすい部品を、電磁波吸収モールド樹脂で封止するという技術が提案されている。   Therefore, recently, a technique has been proposed in which a noise generating source such as a semiconductor element or a component that is susceptible to noise such as a bonding wire or a wiring pattern is sealed with an electromagnetic wave absorbing mold resin.

ここで、電磁波吸収モールド樹脂としては、例えば、通常のモールド樹脂にフィラー材として含まれているシリカの一部分をフェライト(純鉄)に置換することで電磁波吸収効果を持たせたものが挙げられる。   Here, examples of the electromagnetic wave absorbing mold resin include those obtained by substituting ferrite (pure iron) for a part of silica contained in a normal mold resin as a filler material to provide an electromagnetic wave absorbing effect.

以下、図面を用いて電磁波吸収モールド樹脂で封止した従来の半導体パッケージについて説明する。   Hereinafter, a conventional semiconductor package sealed with an electromagnetic wave absorbing mold resin will be described with reference to the drawings.

図3は従来の半導体パッケージを説明するための模式図であり、ここで示す半導体パッケージ101は、半導体チップ102がインターポーザー103表面に形成されたソルダーレジスト104上にダイアタッチ材105を介して接着されている。また、半導体チップ上の電極107がAuワイヤー116でAuパッド106と接続され、Auパッドは半導体チップ搭載側の配線パターン108に接続されている。更に、半導体チップ搭載側の配線パターンはビア109によりマザー基板側の配線パターン110に接続され、マザー基板側の配線パターンはマザー基板接続用の端子111と接続されている。
また、半導体チップ、Auワイヤー及び半導体チップ搭載側の配線パターンを電磁波吸収モールド樹脂112によって完全に被覆している。
FIG. 3 is a schematic diagram for explaining a conventional semiconductor package. In the semiconductor package 101 shown here, a semiconductor chip 102 is bonded onto a solder resist 104 formed on the surface of an interposer 103 via a die attach material 105. Has been. The electrode 107 on the semiconductor chip is connected to the Au pad 106 by an Au wire 116, and the Au pad is connected to the wiring pattern 108 on the semiconductor chip mounting side. Further, the wiring pattern on the semiconductor chip mounting side is connected to the wiring pattern 110 on the mother board side by vias 109, and the wiring pattern on the mother board side is connected to the terminal 111 for connecting to the mother board.
Further, the semiconductor chip, the Au wire, and the wiring pattern on the semiconductor chip mounting side are completely covered with the electromagnetic wave absorbing mold resin 112.

図4は上記した従来の半導体パッケージの製造方法を説明するための模式図である。なお、図4中の平面図では説明の便宜のために封止金型の図示を省略している。   FIG. 4 is a schematic view for explaining the above-described conventional method for manufacturing a semiconductor package. In the plan view in FIG. 4, the sealing mold is not shown for convenience of explanation.

従来の半導体パッケージの製造方法では、先ず、図4(a)で示す様に、インターポーザー103表面に形成されたソルダーレジスト上に半導体チップ102をダイアタッチ材105を用いて接着し、Auワイヤー116で半導体チップ上の電極107とAuパッド106を接続した状態で、封止金型113内に装填する。なお、説明の便宜のため半導体チップ搭載側の配線パターン、ビア、マザー基板側の配線パターン及び端子は図示を省略している。   In the conventional method of manufacturing a semiconductor package, first, as shown in FIG. 4A, a semiconductor chip 102 is bonded onto a solder resist formed on the surface of the interposer 103 using a die attach material 105, and an Au wire 116 is used. Then, the electrode 107 on the semiconductor chip and the Au pad 106 are connected and loaded into the sealing mold 113. For convenience of explanation, illustration of wiring patterns on the semiconductor chip mounting side, vias, wiring patterns on the mother substrate side, and terminals is omitted.

次に、図4(b)で示す様に、封止金型内にトランスファーモールド法によって電磁波吸収モールド樹脂を流入して封止を行う。   Next, as shown in FIG. 4B, sealing is performed by flowing an electromagnetic wave absorbing mold resin into the sealing mold by a transfer molding method.

その後、単体の半導体パッケージへ分離するために、図4(c)で示す様に、ダイヤモンド粒子を貼り付けた切断ブレード114、或いは図示しない切断成形金型等で切断加工が行われることによって、図3で示す様な半導体パッケージを得ることができる。   Thereafter, in order to separate into a single semiconductor package, as shown in FIG. 4C, cutting is performed with a cutting blade 114 to which diamond particles are attached, or a cutting molding die (not shown). A semiconductor package as shown in 3 can be obtained.

特開2003−273571号公報JP 2003-273571 A

しかしながら、電磁波吸収モールド樹脂に含まれるフェライトは、通常のモールド樹脂にフィラー材として含まれるシリカと比べて比重が約3倍と非常に重いために、トランスファーモールド法による成型の際に、電磁波吸収モールド樹脂がAuワイヤーに接触して強い抵抗力が加わりAuワイヤーが変形し、図5(a)で示す様にAuワイヤーと半導体チップの端部が接触したり、図5(b)で示す様に隣接するAuワイヤー同士が接触したりしてショート不良が発生して歩留低下の要因となってしまう。   However, the ferrite contained in the electromagnetic wave absorbing mold resin has an extremely heavy specific gravity of about three times that of silica contained as a filler material in a normal mold resin. As the resin comes into contact with the Au wire, a strong resistance force is applied and the Au wire is deformed. As shown in FIG. 5 (a), the Au wire and the end of the semiconductor chip come into contact, or as shown in FIG. 5 (b). Adjacent Au wires come into contact with each other and a short circuit occurs, which causes a decrease in yield.

このことは、シリカと置換することができるフェライトの割合が制限(例えば、置換できる割合が40%程度等に制限)されることにも繋がり、封止樹脂に含有するフェライトの割合を少なくせざるを得ないために半導体パッケージに充分な電磁波吸収効果を付加することができない。   This also leads to the fact that the ratio of ferrite that can be replaced with silica is limited (for example, the ratio that can be replaced is limited to about 40%, etc.), and the ratio of ferrite contained in the sealing resin must be reduced. Therefore, a sufficient electromagnetic wave absorbing effect cannot be added to the semiconductor package.

なお、上記した様に、フェライトがフィラー材として含まれるシリカと比べて比重が約3倍と非常に重いために、成型性や樹脂の流動性の点からも置換することができるフェライトの割合が制限されてしまう。   In addition, as described above, the specific gravity is about three times as high as that of silica containing ferrite as a filler material, so that the ratio of ferrite that can be replaced is also low in terms of moldability and resin fluidity. It will be restricted.

また、フェライトを含有する電磁波吸収モールド樹脂は製造方法が複雑であるために高価であり、従来のトランスファーモールド法での成型では図4中符号Aで示す製品として使用されない部分にまで電磁波吸収モールド樹脂が流入されるために材料の無駄が生じてしまい材料コストの増加の原因となっている。   In addition, the electromagnetic wave absorbing mold resin containing ferrite is expensive because the manufacturing method is complicated, and the electromagnetic wave absorbing mold resin is not used as a product indicated by symbol A in FIG. 4 in the molding by the conventional transfer mold method. Inflow of material causes waste of material, which increases the material cost.

本発明は、以上の点に鑑みて創案されたものであって、ショート不良による歩留低下を抑制すると共に、材料コストの低減を図ることができる半導体パッケージ及びその製造方法を提供することを目的とするものである。   The present invention has been made in view of the above points, and it is an object of the present invention to provide a semiconductor package and a method for manufacturing the same that can suppress a decrease in yield due to a short circuit defect and can reduce a material cost. It is what.

上記の目的を達成するために、本発明に係る半導体パッケージは、半導体素子と、該半導体素子を封止する封止樹脂を備える半導体パッケージにおいて、前記封止樹脂は、前記半導体素子を被覆する第1の封止樹脂層と、該第1の封止樹脂層を被覆する第2の封止樹脂層を備え、前記第1の封止樹脂層はポッティング法によって形成されると共に、電磁波吸収機能を有する。   In order to achieve the above object, a semiconductor package according to the present invention includes a semiconductor element and a sealing resin that seals the semiconductor element. The sealing resin covers the semiconductor element. 1 sealing resin layer and a second sealing resin layer covering the first sealing resin layer, and the first sealing resin layer is formed by a potting method and has an electromagnetic wave absorbing function. Have.

ここで、第1の封止樹脂層が圧力を加えないポッティング法により形成されたことによって、ボンディングワイヤーの変形を抑制することができる。   Here, since the first sealing resin layer is formed by a potting method in which no pressure is applied, deformation of the bonding wire can be suppressed.

なお、封止樹脂が第1の封止樹脂層と、第1の封止樹脂層を被覆する第2の封止樹脂層を有し、第1の封止樹脂層のみに電磁波吸収機能を付加することにより、半導体パッケージのコスト低減を図ることができる。
即ち、ボンディングワイヤーの変形を抑制するという観点からは、ポッティング法により半導体素子が電磁波吸収機能を有する封止樹脂で封止されれば良く、必ずしも封止樹脂が第1の封止樹脂層と第2の封止樹脂層を有する必要は無いが、封止樹脂を少なくとも2層構造とし、半導体パッケージに電磁波吸収機能を付加するための最小限度の範囲である半導体素子を被覆する第1の封止樹脂層のみに電磁波吸収機能を付加することによって、電磁波吸収機能を付加した高価な封止樹脂の使用量を低減できる。
The sealing resin has a first sealing resin layer and a second sealing resin layer that covers the first sealing resin layer, and an electromagnetic wave absorbing function is added only to the first sealing resin layer. By doing so, the cost of the semiconductor package can be reduced.
That is, from the viewpoint of suppressing deformation of the bonding wire, the semiconductor element may be sealed with a sealing resin having an electromagnetic wave absorption function by a potting method, and the sealing resin is not necessarily connected to the first sealing resin layer and the first sealing resin layer. It is not necessary to have two sealing resin layers, but the first sealing has at least a two-layer structure and covers a semiconductor element that is a minimum range for adding an electromagnetic wave absorbing function to a semiconductor package. By adding the electromagnetic wave absorbing function only to the resin layer, the amount of expensive sealing resin to which the electromagnetic wave absorbing function is added can be reduced.

また、上記の目的を達成するために、本発明に係る半導体パッケージの製造方法は、半導体素子を電磁波吸収機能を有する第1の封止樹脂層で被覆する工程と、前記第1の封止樹脂層を第2の封止樹脂層で被覆する工程を備える半導体パッケージの製造方法であって、少なくとも前記第1の封止樹脂層はポッティング法により形成する。   In order to achieve the above object, a semiconductor package manufacturing method according to the present invention includes a step of covering a semiconductor element with a first sealing resin layer having an electromagnetic wave absorption function, and the first sealing resin. A method of manufacturing a semiconductor package comprising a step of covering a layer with a second sealing resin layer, wherein at least the first sealing resin layer is formed by a potting method.

ここで、少なくとも第1の封止樹脂層をポッティング法により形成することによって、ボンディングワイヤーの変形を抑制することができる。   Here, deformation of the bonding wire can be suppressed by forming at least the first sealing resin layer by a potting method.

なお、第2の封止樹脂層をトランスファーモールド法により形成することにより、生産性の向上を図ることができる。
即ち、ボンディングワイヤーの変形を抑制するという観点からは、少なくとも第1の封止樹脂層をポッティング法により形成すれば良く、必ずしも第2の封止樹脂層をトランスファーモールド法により形成する必要は無いが、封止樹脂を少なくとも2層構造とし、ボンディングワイヤーの変形を抑制するための最小限度の範囲である半導体素子を被覆する第1の封止樹脂層のみをポッティング法により形成し、第2の封止樹脂層をトランスファーモールド法により形成することで半導体パッケージの生産性の向上を図ることができる。
Note that productivity can be improved by forming the second sealing resin layer by a transfer molding method.
That is, from the viewpoint of suppressing the deformation of the bonding wire, at least the first sealing resin layer may be formed by the potting method, and the second sealing resin layer is not necessarily formed by the transfer molding method. The sealing resin has at least a two-layer structure, and only the first sealing resin layer covering the semiconductor element, which is the minimum range for suppressing the deformation of the bonding wire, is formed by the potting method, and the second sealing is performed. The productivity of the semiconductor package can be improved by forming the stop resin layer by a transfer molding method.

上記した様に、本発明の半導体パッケージ及びその製造方法では、電磁波吸収機能を付加した封止樹脂をポッティング法により塗布することで、ボンディングワイヤーの変形が起こらずに、ショート不良による歩留の低下を抑制することができる。   As described above, in the semiconductor package and the manufacturing method thereof according to the present invention, by applying the sealing resin added with the electromagnetic wave absorbing function by the potting method, the bonding wire is not deformed and the yield is reduced due to the short defect. Can be suppressed.

また、ボンディングワイヤーの変形が起こらないことから、電磁波吸収機能を付加するために封止樹脂に含有する例えばフェライト等の材料の割合を高くすることができ、充分な電磁波吸収機能を半導体パッケージに付加することができる。   In addition, since deformation of the bonding wire does not occur, the ratio of materials such as ferrite contained in the sealing resin can be increased to add an electromagnetic wave absorbing function, and a sufficient electromagnetic wave absorbing function is added to the semiconductor package. can do.

更に、製品として使用しない部分に電磁波吸収機能を付加した高価な封止樹脂を用いていないために、半導体パッケージを製造するにあたって電磁波吸収機能を付加した封止樹脂の使用量を必要最小限に抑えることができ、材料費の無駄を最小限に抑えることができる。   Furthermore, since an expensive sealing resin with an electromagnetic wave absorbing function added to a portion not used as a product is not used, the amount of the sealing resin with an electromagnetic wave absorbing function added is minimized when manufacturing a semiconductor package. And the waste of material costs can be minimized.

以下、本発明の実施の形態について図面を参照しながら説明し、本発明の理解に供する。
図1は本発明を適用した半導体パッケージの一例を説明するための模式図であり、ここで示す半導体パッケージ1は、上記した従来の半導体パッケージと同様に、半導体チップ2がインターポーザー3表面に形成されたソルダーレジスト4上にダイアタッチ材5を介して接着されている。また、半導体チップ上の電極7がAuワイヤー16でAuパッド6と接続され、Auパッドは半導体チップ搭載側の配線パターン8に接続されている。更に、半導体チップ搭載側の配線パターンはビア9によりマザー基板側の配線パターン10に接続され、マザー基板側の配線パターンはマザー基板接続用の端子11と接続されている。
また、半導体チップ、Auワイヤー及び半導体チップ搭載側の配線パターンをフェライト及びシリカ(いずれも図示せず)を含有する電磁波吸収モールド樹脂12によって被覆し、電磁波吸収モールド樹脂の外側をシリカ(図示せず)を含有するエポキシ樹脂13によって被覆している。
Hereinafter, embodiments of the present invention will be described with reference to the drawings to facilitate understanding of the present invention.
FIG. 1 is a schematic diagram for explaining an example of a semiconductor package to which the present invention is applied. In the semiconductor package 1 shown here, a semiconductor chip 2 is formed on the surface of an interposer 3 as in the conventional semiconductor package described above. The solder resist 4 is bonded via a die attach material 5. Further, the electrode 7 on the semiconductor chip is connected to the Au pad 6 by an Au wire 16, and the Au pad is connected to the wiring pattern 8 on the semiconductor chip mounting side. Further, the wiring pattern on the semiconductor chip mounting side is connected to the wiring pattern 10 on the mother board side by vias 9, and the wiring pattern on the mother board side is connected to the terminal 11 for connecting to the mother board.
Moreover, the semiconductor chip, the Au wire, and the wiring pattern on the semiconductor chip mounting side are covered with an electromagnetic wave absorbing mold resin 12 containing ferrite and silica (both not shown), and the outside of the electromagnetic wave absorbing mold resin is silica (not shown). ) Containing epoxy resin 13.

なお、電磁波吸収モールド樹脂は、エポキシ樹脂に含有するフィラー材として機能するシリカの一部をフェライトに置換させたものである。   The electromagnetic wave absorbing mold resin is obtained by replacing a part of silica functioning as a filler material contained in an epoxy resin with ferrite.

以下、上記した半導体パッケージの製造方法について説明する。即ち、本発明を適用した半導体パッケージの製造方法の一例について説明する。なお、図2中の平面図では説明の便宜のために封止金型の図示を省略している。   Hereinafter, a method for manufacturing the above-described semiconductor package will be described. That is, an example of a method for manufacturing a semiconductor package to which the present invention is applied will be described. In the plan view in FIG. 2, the sealing mold is not shown for convenience of explanation.

本発明を適用した半導体パッケージの製造方法では、先ず、図2(a)で示す様に、インターポーザー3表面に形成されたソルダーレジスト4上に半導体チップ2をダイアタッチ材5を用いて接着し、Auワイヤー16で半導体チップ上の電極7とAuパッド6を接続する。なお、説明の便宜のため半導体チップ搭載側の配線パターン、ビア、マザー基板側の配線パターン及び端子は図示を省略している。   In the manufacturing method of the semiconductor package to which the present invention is applied, first, as shown in FIG. 2A, the semiconductor chip 2 is bonded onto the solder resist 4 formed on the surface of the interposer 3 by using the die attach material 5. The electrode 7 on the semiconductor chip and the Au pad 6 are connected by the Au wire 16. For convenience of explanation, illustration of wiring patterns on the semiconductor chip mounting side, vias, wiring patterns on the mother substrate side, and terminals is omitted.

次に、図2(b)で示す様に、半導体チップ、Auワイヤー及び半導体チップ搭載側の配線パターンを被覆する様にポッティング法により電磁波吸収モールド樹脂12を塗布し、電磁波モールド樹脂を硬化する。   Next, as shown in FIG. 2B, the electromagnetic wave absorbing mold resin 12 is applied by a potting method so as to cover the semiconductor chip, the Au wire, and the wiring pattern on the semiconductor chip mounting side, and the electromagnetic wave mold resin is cured.

続いて、図2(c)で示す様に、封止金型14内に装填し、封止金型内にトランスファーモールド法によってエポキシ樹脂13を流入して封止を行う。   Subsequently, as shown in FIG. 2C, the resin is loaded into the sealing mold 14, and the epoxy resin 13 is poured into the sealing mold by a transfer molding method to perform sealing.

その後、上記した従来の半導体パッケージの製造方法と同様に、単体の半導体パッケージへ分離するために、図2(d)で示す様に、ダイヤモンド粒子が貼り付けた切断ブレード15、或いは図示しない切断成形金型等で切断加工を行うことによって、図1で示す様な半導体パッケージを得ることができる。   Thereafter, as shown in FIG. 2 (d), in order to separate into a single semiconductor package, as in the conventional semiconductor package manufacturing method described above, as shown in FIG. A semiconductor package as shown in FIG. 1 can be obtained by cutting with a mold or the like.

ここで、上記の実施例では、封止樹脂の内側領域(以下、単に内側領域と言う)を電磁波吸収モールド樹脂でポッティング法により形成し、封止樹脂の外側領域(以下、単に外側領域と言う)をエポキシ樹脂でトランスファーモールド法により形成しているが、内側領域を電磁波吸収モールド樹脂でポッティング法により形成することによって、半導体パッケージに電磁波吸収機能を付加することができると共に、内側領域の形成の際にAuワイヤーの変形に起因するショート不良を抑制することができるために、必ずしも外側領域をエポキシ樹脂でトランスファーモールド法により形成する必要は無い。
但し、外側領域を電磁波吸収モールド樹脂で形成した場合には、高価な電磁波吸収モールド樹脂の使用量が増加し、半導体パッケージの製造コストが増加してしまうために、外側領域は通常のエポキシ樹脂で形成する方が好ましい。
また、外側領域をポッティング法で形成した場合には、樹脂封止に時間を要し、半導体パッケージの生産性が低下してしまうために、外側領域はトランスファーモールド法で形成した方が好ましい。
Here, in the above embodiment, the inner region of the sealing resin (hereinafter simply referred to as the inner region) is formed by potting with an electromagnetic wave absorbing mold resin, and the outer region of the sealing resin (hereinafter simply referred to as the outer region). ) Is formed by transfer molding with epoxy resin, but by forming the inner region by potting method with electromagnetic wave absorbing mold resin, an electromagnetic wave absorbing function can be added to the semiconductor package and the inner region can be formed. At this time, since it is possible to suppress short-circuit defects caused by deformation of the Au wire, it is not always necessary to form the outer region with an epoxy resin by a transfer molding method.
However, when the outer region is formed of an electromagnetic wave absorbing mold resin, the amount of expensive electromagnetic wave absorbing mold resin is increased and the manufacturing cost of the semiconductor package is increased. It is preferable to form it.
Further, when the outer region is formed by the potting method, it takes time for the resin sealing, and the productivity of the semiconductor package is lowered. Therefore, the outer region is preferably formed by the transfer molding method.

また、上記の実施例では、封止樹脂に電磁波吸収機能を付加するためにエポキシ樹脂にフィラー材として含有するシリカの一部をフェライトと置換しているが、封止樹脂に電磁波吸収機能を付加することができるのであれば、必ずしもフェライトを含有する必要は無く、その他の方法によって電磁波吸収機能を付加しても良いことは勿論である。   In the above embodiment, in order to add an electromagnetic wave absorbing function to the sealing resin, a part of silica contained as a filler material in the epoxy resin is replaced with ferrite, but the electromagnetic wave absorbing function is added to the sealing resin. It is not always necessary to contain ferrite if it can be done, and it is needless to say that an electromagnetic wave absorbing function may be added by other methods.

上記した本発明を適用した半導体パッケージ及びその製造方法では、内側領域を電磁波吸収モールド樹脂で被覆する際に、ポッティング法を採用しているために、内側領域の被覆時にAuワイヤーの変形が生じることがなく、Auワイヤーと半導体チップの端部が接触したり、隣接するAuワイヤー同士が接触したりしてショート不良が生じることが無い。   In the semiconductor package to which the present invention is applied and the manufacturing method thereof, since the potting method is adopted when the inner region is covered with the electromagnetic wave absorbing mold resin, the Au wire is deformed when the inner region is covered. There is no short circuit defect due to contact between the end of the Au wire and the semiconductor chip or contact between adjacent Au wires.

また、Auワイヤーの変形が無いために、エポキシ樹脂中のシリカと置換するフェライトの割合を高くすることができ、即ち、電磁波吸収モールド樹脂に含有するフェライトの量を増加することができるために、充分な電磁波吸収効果を有する半導体パッケージを得ることができる。   In addition, since there is no deformation of the Au wire, the ratio of ferrite replacing silica in the epoxy resin can be increased, that is, the amount of ferrite contained in the electromagnetic wave absorbing mold resin can be increased. A semiconductor package having a sufficient electromagnetic wave absorption effect can be obtained.

更に、外側領域をエポキシ樹脂で被覆する際に、トランスファーモールド法を採用しているために、半導体パッケージの生産性の向上を図ることができる。   Furthermore, when the outer region is covered with the epoxy resin, the transfer mold method is adopted, so that the productivity of the semiconductor package can be improved.

また、図2中符号Bで示す製品として使用されない部分についてはエポキシ樹脂を使用するために、高価な電磁波吸収モールド樹脂の使用量を抑制し、半導体パッケージのコスト低減を図ることができる。   In addition, since an epoxy resin is used for a portion that is not used as a product indicated by the symbol B in FIG. 2, the amount of expensive electromagnetic wave absorbing mold resin used can be suppressed, and the cost of the semiconductor package can be reduced.

本発明を適用した半導体パッケージの一例を説明するための模式図である。It is a schematic diagram for demonstrating an example of the semiconductor package to which this invention is applied. 本発明を適用した半導体パッケージの製造方法の一例を説明するための模式図である。It is a schematic diagram for demonstrating an example of the manufacturing method of the semiconductor package to which this invention is applied. 従来の半導体パッケージを説明するための模式図である。It is a schematic diagram for demonstrating the conventional semiconductor package. 従来の半導体パッケージの製造方法を説明するための模式図である。It is a schematic diagram for demonstrating the manufacturing method of the conventional semiconductor package. ショート不良を説明するための模式図である。It is a schematic diagram for demonstrating a short circuit defect.

符号の説明Explanation of symbols

1 半導体パッケージ
2 半導体チップ
3 インターポーザー
4 ソルダーレジスト
5 ダイアタッチ材
6 Auパッド
7 電極
8 半導体チップ搭載側の配線パターン
9 ビア
10 マザー基板側の配線パターン
11 端子
12 電磁波吸収モールド樹脂
13 エポキシ樹脂
14 封止金型
15 ブレード
16 Auワイヤー
DESCRIPTION OF SYMBOLS 1 Semiconductor package 2 Semiconductor chip 3 Interposer 4 Solder resist 5 Die attach material 6 Au pad 7 Electrode 8 Wiring pattern on the semiconductor chip mounting side 9 Via 10 Wiring pattern on the mother substrate side 11 Terminal 12 Electromagnetic wave absorption molding resin 13 Epoxy resin 14 Sealing Stopper mold 15 Blade 16 Au wire

Claims (4)

半導体素子と、
該半導体素子を封止する封止樹脂を備える半導体パッケージにおいて、
前記封止樹脂は、前記半導体素子を被覆する第1の封止樹脂層と、該第1の封止樹脂層を被覆する第2の封止樹脂層を備え、
前記第1の封止樹脂層はポッティング法によって形成されると共に、電磁波吸収機能を有する
ことを特徴とする半導体パッケージ。
A semiconductor element;
In a semiconductor package comprising a sealing resin for sealing the semiconductor element,
The sealing resin includes a first sealing resin layer that covers the semiconductor element, and a second sealing resin layer that covers the first sealing resin layer,
The first sealing resin layer is formed by a potting method and has an electromagnetic wave absorbing function.
前記第1の封止樹脂層はフェライトを含有する
ことを特徴とする請求項1に記載の半導体パッケージ。
The semiconductor package according to claim 1, wherein the first sealing resin layer contains ferrite.
半導体素子を電磁波吸収機能を有する第1の封止樹脂層で被覆する工程と、
前記第1の封止樹脂層を第2の封止樹脂層で被覆する工程を備える半導体パッケージの製造方法であって、
少なくとも前記第1の封止樹脂層はポッティング法により形成する
ことを特徴とする半導体パッケージの製造方法。
Coating a semiconductor element with a first sealing resin layer having an electromagnetic wave absorbing function;
A method of manufacturing a semiconductor package comprising a step of covering the first sealing resin layer with a second sealing resin layer,
At least the first sealing resin layer is formed by a potting method. A method of manufacturing a semiconductor package, wherein:
前記第2の封止樹脂層はトランスファーモールド法により形成する
ことを特徴とする請求項3に記載の半導体パッケージの製造方法。
The method for manufacturing a semiconductor package according to claim 3, wherein the second sealing resin layer is formed by a transfer molding method.
JP2004022557A 2004-01-30 2004-01-30 Semiconductor package and method for manufacturing the same Pending JP2005217221A (en)

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100690247B1 (en) 2006-01-16 2007-03-12 삼성전자주식회사 Double encapsulated semiconductor package and manufacturing method thereof
JP2008001757A (en) * 2006-06-20 2008-01-10 Kyocera Chemical Corp Resin composition for semiconductor sealing use and resin-sealed type semiconductor device
JP2010071724A (en) * 2008-09-17 2010-04-02 Mitsubishi Electric Corp Resin molded semiconductor sensor and method of manufacturing the same
JP2013525593A (en) * 2010-05-05 2013-06-20 タイコ エレクトロニクス サービシズ ゲゼルシャフト ミット ベシュレンクテル ハフツンク Potting for electronic parts
US9685412B2 (en) 2013-09-04 2017-06-20 Kabushiki Kaisha Toshiba Semiconductor apparatus and manufacturing method for same
US9871016B2 (en) 2015-07-29 2018-01-16 Samsung Electronics Co., Ltd. Semiconductor package
US9978690B2 (en) 2013-09-04 2018-05-22 Toshiba Memory Corporation Semiconductor apparatus and manufacturing method for same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63114241A (en) * 1986-10-31 1988-05-19 Texas Instr Japan Ltd Semiconductor device
JPH05129476A (en) * 1991-11-05 1993-05-25 Matsushita Electron Corp Semiconductor device and manufacture thereof
JPH1140708A (en) * 1997-07-18 1999-02-12 Hitachi Ltd Semiconductor device
JPH1140707A (en) * 1997-07-18 1999-02-12 Hitachi Ltd Semiconductor device
JPH11214592A (en) * 1998-01-21 1999-08-06 Hitachi Ltd Semiconductor device and electronic device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63114241A (en) * 1986-10-31 1988-05-19 Texas Instr Japan Ltd Semiconductor device
JPH05129476A (en) * 1991-11-05 1993-05-25 Matsushita Electron Corp Semiconductor device and manufacture thereof
JPH1140708A (en) * 1997-07-18 1999-02-12 Hitachi Ltd Semiconductor device
JPH1140707A (en) * 1997-07-18 1999-02-12 Hitachi Ltd Semiconductor device
JPH11214592A (en) * 1998-01-21 1999-08-06 Hitachi Ltd Semiconductor device and electronic device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100690247B1 (en) 2006-01-16 2007-03-12 삼성전자주식회사 Double encapsulated semiconductor package and manufacturing method thereof
JP2008001757A (en) * 2006-06-20 2008-01-10 Kyocera Chemical Corp Resin composition for semiconductor sealing use and resin-sealed type semiconductor device
JP2010071724A (en) * 2008-09-17 2010-04-02 Mitsubishi Electric Corp Resin molded semiconductor sensor and method of manufacturing the same
JP2013525593A (en) * 2010-05-05 2013-06-20 タイコ エレクトロニクス サービシズ ゲゼルシャフト ミット ベシュレンクテル ハフツンク Potting for electronic parts
US9685412B2 (en) 2013-09-04 2017-06-20 Kabushiki Kaisha Toshiba Semiconductor apparatus and manufacturing method for same
US9978690B2 (en) 2013-09-04 2018-05-22 Toshiba Memory Corporation Semiconductor apparatus and manufacturing method for same
US9871016B2 (en) 2015-07-29 2018-01-16 Samsung Electronics Co., Ltd. Semiconductor package

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