JP2005203562A - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Semiconductor device and manufacturing method of semiconductor device Download PDF

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Publication number
JP2005203562A
JP2005203562A JP2004008255A JP2004008255A JP2005203562A JP 2005203562 A JP2005203562 A JP 2005203562A JP 2004008255 A JP2004008255 A JP 2004008255A JP 2004008255 A JP2004008255 A JP 2004008255A JP 2005203562 A JP2005203562 A JP 2005203562A
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Japan
Prior art keywords
electrode
protective film
film
insulating film
forming
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JP4277692B2 (en
Inventor
Suketsugu Funato
祐嗣 舩戸
Kazuo Akamatsu
和夫 赤松
Yasushi Higuchi
安史 樋口
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Denso Corp
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Denso Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device of a low cost with a protecting film which is excellent in step coverage, and to provide its manufacturing method. <P>SOLUTION: The level difference of a device surface is relaxed by making a protecting film 1 expand toward the end by burying up to the side wall 87a of a copper electrode 87 by properly setting the viscosity of an application insulating film for forming the protecting film 1. A protecting film 2 covers from top of the upper circumferential part 87b of the copper electrode 87 to a top 87c by properly setting the viscosity of the application insulating film for forming the protecting film 2. Consequently, the level difference of the device surface is relaxed by the protecting film 1. Therefore, when the application insulating film which becomes the protecting film 2 is applied, material degradation is hardly generated in the application insulating film covering from top of the upper circumferential edge part 87b of the copper electrode 87 to the top 87c and the protecting film 2 in a portion covering each of the parts 87b, 87c becomes thick, thus improving step coverage of the protecting films 1, 2. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、半導体装置および半導体装置の製造方法に係り、詳しくは、電極を保護する
保護膜を備えた半導体装置と、その半導体装置の製造方法とに関するものである。
The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a semiconductor device provided with a protective film for protecting an electrode and a method for manufacturing the semiconductor device.

従来より、電極や配線層の上にSOG(Spin coating On Glass)膜などの塗布絶縁膜を
保護膜として形成した半導体装置が種々提案されている(例えば、特許文献1参照)。
特開2003−149681号公報(第2〜3頁、図1)
Conventionally, various semiconductor devices have been proposed in which a coating insulating film such as an SOG (Spin coating On Glass) film is formed as a protective film on an electrode or a wiring layer (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 2003-149681 (pages 2 and 3, FIG. 1)

図12および図13は、電極の上に塗布絶縁膜を保護膜として形成した従来の半導体装
置の製造方法を説明するための概略断面図である。
12 and 13 are schematic cross-sectional views for explaining a conventional method of manufacturing a semiconductor device in which a coating insulating film is formed as a protective film on an electrode.

工程1(図12(A)):単結晶シリコン基板81上にPVD(Physical Vapor Depos
ition)法を用いてアルミニウム合金膜を形成し、そのアルミニウム合金膜をパターニング
して配線層82を形成する。次に、配線層82上を含む基板81の全面にCVD(Chemic
al Vapor Deposition)法を用いて保護用のシリコン窒化膜83を形成し、配線層82上の
シリコン窒化膜83をドライエッチング法を用いて除去(エッチバック)する。続いて、
露出された配線層82上およびシリコン窒化膜83上にPVD法を用いてバリアメタル層
84とシード層85とをこの順番で形成する。
Step 1 (FIG. 12A): PVD (Physical Vapor Depos) on the single crystal silicon substrate 81.
The aluminum alloy film is formed by using the (ition) method, and the wiring layer 82 is formed by patterning the aluminum alloy film. Next, CVD (Chemic) is formed on the entire surface of the substrate 81 including the wiring layer 82.
A protective silicon nitride film 83 is formed using an al Vapor Deposition method, and the silicon nitride film 83 on the wiring layer 82 is removed (etched back) using a dry etching method. continue,
A barrier metal layer 84 and a seed layer 85 are formed in this order on the exposed wiring layer 82 and silicon nitride film 83 by using the PVD method.

そして、シード層85上に厚いフォトレジスト膜86を形成し、フォトリソグラフィ法
を用いて配線層82の上方のフォトレジスト膜86を除去し、フォトレジスト膜86に電
極形成用開孔部86aを形成する。ここで、フォトレジスト膜86の膜厚は、後述する銅
電極87の膜厚(高さ)に比べて十分に厚くなるように形成する必要がある。
Then, a thick photoresist film 86 is formed on the seed layer 85, the photoresist film 86 above the wiring layer 82 is removed by using a photolithography method, and an electrode forming aperture 86a is formed in the photoresist film 86. To do. Here, the film thickness of the photoresist film 86 needs to be formed to be sufficiently thicker than the film thickness (height) of a copper electrode 87 described later.

このように、フォトレジスト膜86の膜厚が厚い場合には、フォトリソグラフィ法の露
光特性から、電極形成用開孔部86aの形状は、上部から下部に向かって横断面積が次第
に小さくなり窄まったものになる。例えば、電極形成用開孔部86aの平面形状が略円形
の場合、その形状は上部から下部に向かって円錐状に直径が次第に減少してゆくテーパー
状になる。
Thus, when the thickness of the photoresist film 86 is large, the shape of the electrode forming aperture 86a becomes narrower as the cross-sectional area gradually decreases from the top to the bottom due to the exposure characteristics of the photolithography method. It becomes a thing. For example, when the planar shape of the electrode forming aperture 86a is substantially circular, the shape is a tapered shape whose diameter gradually decreases conically from the top to the bottom.

工程2(図12(B)):電極形成用開孔部86a底部に露出したシード層85上にメ
ッキ法を用いて銅(または銅合金)を堆積させて電極形成用開孔部86a内を埋めること
により銅電極87を形成する。このとき、シード層85は、メッキ法により堆積される銅
のシードとして機能する。尚、シード層85の材料としては、例えば、銅、金、ルテニウ
ム、プラチナなどを用いればよい。また、バリアメタル層84は、銅電極87中の銅が基
板81やシリコン窒化膜83などに拡散するのを防止するために設けられている。尚、バ
リアメタル層84の材料としては、例えば、チタンやタングステンの合金(TiNやTi
Wなど)などを用いればよい。
Step 2 (FIG. 12B): Copper (or copper alloy) is deposited on the seed layer 85 exposed at the bottom of the electrode forming aperture 86a using a plating method, and the inside of the electrode forming aperture 86a is formed. A copper electrode 87 is formed by filling. At this time, the seed layer 85 functions as a copper seed deposited by a plating method. As a material for the seed layer 85, for example, copper, gold, ruthenium, platinum or the like may be used. The barrier metal layer 84 is provided to prevent copper in the copper electrode 87 from diffusing into the substrate 81, the silicon nitride film 83, and the like. The material of the barrier metal layer 84 is, for example, an alloy of titanium or tungsten (TiN or Ti
W etc.) may be used.

工程3(図12(C)):フォトレジスト膜86をアッシング法などを用いて除去し、
シード層85および銅電極87を露出させる。ここで、銅電極87の形状は、電極形成用
開孔部86aの形状に沿ったものになり、上部から下部に向かって横断面積が次第に小さ
くなり窄まったものになる。例えば、銅電極87の平面形状が略円形の場合、その形状は
上部から下部に向かって円錐状に直径が次第に減少してゆくテーパー状になる。そして、
銅電極87の側壁87aは、基板81表面に対して鋭角の勾配をなし、アンダーカット形
状となる。
Step 3 (FIG. 12C): The photoresist film 86 is removed using an ashing method or the like,
The seed layer 85 and the copper electrode 87 are exposed. Here, the shape of the copper electrode 87 is in accordance with the shape of the electrode-forming opening 86a, and the cross-sectional area gradually decreases from the upper part to the lower part and becomes narrower. For example, when the planar shape of the copper electrode 87 is substantially circular, the shape of the copper electrode 87 becomes a tapered shape with a diameter gradually decreasing from a top to a bottom. And
The side wall 87a of the copper electrode 87 has an acute angle gradient with respect to the surface of the substrate 81 and has an undercut shape.

工程4(図13(A)):銅電極87の下部のバリアメタル層84およびシード層85
を除き、デバイス表面に露出しているバリアメタル層84およびシード層85をウエット
エッチング法を用いて除去する。このとき、銅電極87の上部周縁も削り取られ、アール
が付けられた上部周縁部87bが形成される。
Step 4 (FIG. 13A): barrier metal layer 84 and seed layer 85 below copper electrode 87
The barrier metal layer 84 and the seed layer 85 exposed on the device surface are removed using a wet etching method. At this time, the upper peripheral edge of the copper electrode 87 is also scraped off to form an upper peripheral edge 87b with a radius.

工程5(図13(B)(C)):銅電極87上およびシリコン窒化膜83上を含むデバ
イスの全面に塗布絶縁膜を塗布した後に硬化させて保護膜88を形成する。尚、保護膜8
8を形成するための塗布絶縁膜の材料としては、例えば、SOG、ポリイミド、メチルシ
ロキサン系ポリマーなどを用いればよい。特に、ポリイミドは、透湿性が低く、耐熱性が
高く、基板81を樹脂材料(エポキシ樹脂など)でモールドする際に当該樹脂材料との密
着性が高いため、保護膜88として最適である。
Step 5 (FIGS. 13B and 13C): A coating insulating film is applied to the entire surface of the device including the copper electrode 87 and the silicon nitride film 83, and then cured to form a protective film 88. The protective film 8
For example, SOG, polyimide, methylsiloxane polymer, or the like may be used as a material of the coating insulating film for forming the film 8. In particular, polyimide is optimal as the protective film 88 because it has low moisture permeability, high heat resistance, and high adhesion to the resin material when the substrate 81 is molded with a resin material (such as an epoxy resin).

近年、リレーなどの大きな駆動電流(例えば、15アンペア)を要求される半導体デバ
イスや、DMOS(Double diffused MOS)トランジスタやLDMOS(Laterally Diffu
sed MOS)トランジスタなどのパワーデバイスにおいては、電流損失を低減するため電極部分(リレーの終端電極、MOSトランジスタのソース・ドレイン電極)の低抵抗化が要求されている。そのため、電極材料として従来一般的であったアルミニウム合金よりも電気抵抗が小さな銅を用いると共に、電極の大型化が図られている。
In recent years, semiconductor devices such as relays that require a large driving current (for example, 15 amperes), DMOS (Double diffused MOS) transistors, LDMOS (Laterally Diffu)
In power devices such as sed MOS transistors, it is required to reduce the resistance of electrode portions (relay termination electrodes, source / drain electrodes of MOS transistors) in order to reduce current loss. For this reason, copper having a smaller electrical resistance than an aluminum alloy that has been conventionally used as an electrode material is used, and the size of the electrode is increased.

そして、電極の大型化に伴い、電極の高さも大きくなっている(電極の膜厚が厚くなっ
ている)。例えば、従来のアルミニウム合金からなる電極の膜厚が1μ以下であったのに
対して、大電流が流れる銅電極の膜厚は10μm程度と従来の10倍以上にもなる場合が
ある。
And with the enlargement of an electrode, the height of the electrode is also increased (the film thickness of the electrode is increased). For example, while the film thickness of a conventional electrode made of an aluminum alloy was 1 μm or less, the film thickness of a copper electrode through which a large current flows may be about 10 μm, which is 10 times or more that of the conventional one.

図12および図13に示す銅電極87の膜厚(高さ)を10μm程度にするためには、
フォトレジスト膜86の膜厚を少なくとも10μm以上にする必要がある。そして、フォ
トレジスト膜86の膜厚を厚くすると、前記のように、フォトリソグラフィ法の露光特性
から、電極形成用開孔部86aの形状は、上部から下部に向かって横断面積が次第に小さ
くなり窄まったものになる。その結果、銅電極87の形状も、電極形成用開孔部86aの
形状に沿ったものになり、上部から下部に向かって横断面積が次第に小さくなり窄まった
ものになる。
In order to set the film thickness (height) of the copper electrode 87 shown in FIGS. 12 and 13 to about 10 μm,
The film thickness of the photoresist film 86 needs to be at least 10 μm. When the thickness of the photoresist film 86 is increased, as described above, due to the exposure characteristics of the photolithography method, the shape of the electrode forming aperture 86a gradually decreases in cross section from the top to the bottom. It will be a waste. As a result, the shape of the copper electrode 87 also conforms to the shape of the electrode forming aperture 86a, and the cross-sectional area gradually decreases from the upper part to the lower part and becomes narrower.

すると、図13(B)(C)に示すように保護膜88を形成する際に、保護膜88とな
る塗布絶縁膜を塗布したとき、その塗布絶縁膜の表面張力によって銅電極87の上部周縁
部87b上および頂部87c上を覆う当該塗布絶縁膜に肉退けが生じて膜厚が薄くなり、
保護膜88の段差被覆性(ステップカバレッジ)が低下するという問題がある。
Then, when forming the protective film 88 as shown in FIGS. 13B and 13C, when a coating insulating film serving as the protective film 88 is applied, the upper peripheral edge of the copper electrode 87 is applied by the surface tension of the coating insulating film. The thickness of the coating insulating film covering the portion 87b and the top portion 87c is reduced by thinning,
There is a problem that the step coverage of the protective film 88 is lowered.

ここで、保護膜88となる塗布絶縁膜の塗布量が少ない場合には、図13(C)に示す
ように、電極87の上部周縁部87bを覆う保護膜88が極めて薄くなり、亀裂88aや
剥離88bが生じることがある。保護膜88に亀裂88aや剥離88bといった水分進入
経路が生じると、その水分進入経路から電極87へ水分が進入し、短絡を起こすおそれが
ある。
Here, when the coating amount of the coating insulating film serving as the protective film 88 is small, as shown in FIG. 13C, the protective film 88 covering the upper peripheral edge 87b of the electrode 87 becomes extremely thin, and cracks 88a and Separation 88b may occur. If a moisture ingress path such as a crack 88a or a separation 88b occurs in the protective film 88, moisture may enter the electrode 87 from the moisture ingress path and cause a short circuit.

保護膜88の亀裂88aや剥離88bを防止するには、保護膜88となる塗布絶縁膜の
塗布量を多くし、図13(B)に示すように、電極87の上部周縁部87bを覆う保護膜
88を厚くすればよい。しかし、保護膜88を形成するための塗布絶縁膜の材料は一般に
高価であり、特に保護膜88として最適なポリイミドは非常に高価であるため、保護膜8
8を厚くすると製造コスト(材料コスト)が増大するという問題がある。
In order to prevent the crack 88a and the peeling 88b of the protective film 88, the coating amount of the coating insulating film to be the protective film 88 is increased, and the protection covering the upper peripheral edge 87b of the electrode 87 as shown in FIG. The film 88 may be thickened. However, the material of the coating insulating film for forming the protective film 88 is generally expensive. In particular, the optimum polyimide as the protective film 88 is very expensive.
If 8 is thickened, there is a problem that the manufacturing cost (material cost) increases.

本発明は上記問題を解決するためになされたものであって、その目的は、段差被覆性に
優れた保護膜を備えた低コストな半導体装置およびその製造方法を提供することにある。
The present invention has been made to solve the above problems, and an object of the present invention is to provide a low-cost semiconductor device including a protective film excellent in step coverage and a method for manufacturing the same.

(請求項1:第1〜第3実施形態に該当)
請求項1に記載の発明は、基板上に形成された電極と、その電極を保護するために塗布
絶縁膜によって形成された保護膜とを備えた半導体装置であって、前記保護膜は、前記電
極の側壁部分までを埋め込んで裾野状に広がる第1保護膜と、前記電極の上部を覆う第2
保護膜とからなることを技術的特徴とする。
(Claim 1: corresponds to the first to third embodiments)
Invention of Claim 1 is a semiconductor device provided with the electrode formed on the board | substrate, and the protective film formed with the coating insulating film in order to protect the electrode, Comprising: The said protective film is the said protective film, A first protective film embedded in the side wall of the electrode and spreading in a skirt shape; and a second covering the upper part of the electrode
It is technically characterized by comprising a protective film.

(請求項2:第2実施形態に該当)
請求項2に記載の発明は、請求項1に記載の半導体装置において、前記第2保護膜は、
前記電極の上部周縁部および頂部のみを覆うことを技術的特徴とする。
(Claim 2: corresponds to the second embodiment)
According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the second protective film is
A technical feature is to cover only the upper peripheral edge and top of the electrode.

(請求項3:第3実施形態に該当)
請求項3に記載の発明は、請求項1に記載の半導体装置において、前記第1保護膜また
は前記第2保護膜の少なくともいずれかが多層構造をなすことを技術的特徴とする。
(Claim 3: corresponds to the third embodiment)
According to a third aspect of the present invention, in the semiconductor device according to the first aspect, at least one of the first protective film and the second protective film has a multilayer structure.

(請求項4:第1〜第3実施形態に該当)
請求項4に記載の発明は、基板上に電極を形成する第1工程と、前記電極を含む基板上
に第1塗布絶縁膜を塗布させた後に硬化させて第1保護膜を形成する第2工程と、前記電
極上および前記第1保護膜上に第2塗布絶縁膜を塗布させた後に硬化させて第2保護膜を
形成する第3工程とを備え、前記第1保護膜は前記電極の側壁部分までを埋め込んで裾野
状に広がり、前記第2保護膜は前記電極の上部を覆うことを技術的特徴とする。
(Claim 4: Corresponds to the first to third embodiments)
According to a fourth aspect of the present invention, there is provided a first step of forming an electrode on a substrate, and a second step of forming a first protective film by applying a first coating insulating film on the substrate including the electrode and then curing the coating. And a third step of forming a second protective film by applying a second coating insulating film on the electrode and the first protective film, and then curing the second coated insulating film. It is technically characterized that the side wall portion is buried and spreads in a skirt shape, and the second protective film covers the upper portion of the electrode.

(請求項5:第4実施形態または第5実施形態に該当)
請求項5に記載の発明は、基板上に形成された電極と、その電極の近傍の基板上に形成
されたダミー部材と、前記電極および前記ダミー部材を覆って保護するために塗布絶縁膜
によって形成された保護膜とを備えたことを技術的特徴とする。
(Claim 5: Corresponds to the fourth embodiment or the fifth embodiment)
The invention according to claim 5 includes an electrode formed on the substrate, a dummy member formed on the substrate in the vicinity of the electrode, and a coating insulating film for covering and protecting the electrode and the dummy member. A technical feature is that the protective film is provided.

(請求項6:第4実施形態に該当)
請求項6に記載の発明は、請求項5に記載の半導体装置において、前記ダミー部材は前
記電極と同じ材料によって形成されていることを技術的特徴とする。
(Claim 6: corresponds to the fourth embodiment)
The invention according to claim 6 is the semiconductor device according to claim 5, wherein the dummy member is formed of the same material as the electrode.

(請求項7:第4実施形態に該当)
請求項7に記載の発明は、基板上に電極を形成し、それと同時に、前記電極の近傍の基
板上に前記電極と同じ材料によってダミー部材を形成する第1工程と、前記電極および前
記ダミー部材を含む基板上に塗布絶縁膜を塗布させた後に硬化させて保護膜を形成する第
2工程とを備えたことを技術的特徴とする。
(Claim 7: Corresponds to the fourth embodiment)
The invention according to claim 7 is a first step of forming a dummy member on the substrate in the vicinity of the electrode, and simultaneously forming a dummy member with the same material as the electrode on the substrate, and the electrode and the dummy member. And a second step of forming a protective film by applying a coating insulating film on a substrate including the second insulating layer.

(請求項8:第5実施形態に該当)
請求項8に記載の発明は、請求項5に記載の半導体装置において、前記ダミー部材は絶
縁材料によって形成されていることを技術的特徴とする。
(Claim 8: corresponds to the fifth embodiment)
The invention described in claim 8 is a semiconductor device according to claim 5, wherein the dummy member is formed of an insulating material.

(請求項9:第5実施形態に該当)
請求項9に記載の発明は、基板上に第1塗布絶縁膜を塗布させた後に硬化させてダミー
用膜を形成する第1工程と、前記ダミー用膜をパターニングして基板上の電極形成箇所の
近傍にダミー部材を形成する第2工程と、基板上の前記電極形成箇所に電極を形成する第
3工程と、前記電極および前記ダミー部材を含む基板上に第2塗布絶縁膜を塗布させた後
に硬化させて保護膜を形成する第4工程とを備えたことを技術的特徴とする。
(Claim 9: Corresponds to the fifth embodiment)
According to a ninth aspect of the present invention, there is provided a first step of forming a dummy film by applying a first coating insulating film on a substrate and then patterning the dummy film, and forming electrode positions on the substrate by patterning the dummy film A second step of forming a dummy member in the vicinity of the substrate, a third step of forming an electrode at the position where the electrode is formed on the substrate, and a second coating insulating film is applied on the substrate including the electrode and the dummy member And a fourth step of forming a protective film by subsequent curing.

(請求項1)
請求項1に記載の発明では、第1保護膜を形成するための塗布絶縁膜の粘度を適宜設定
することにより、第1保護膜が電極の側壁部分までを埋め込んで裾野状に広がるようにし
てデバイス表面の段差を緩和しておく。そして、第2保護膜を形成するための塗布絶縁膜
の粘度を適宜設定することにより、第2保護膜が電極の上部周縁部から頂部までを覆うよ
うにする。尚、各保護膜を形成するための塗布絶縁膜の粘度および塗布量は、カット・ア
ンド・トライで実験的に最適値を見つけて設定すればよい。
(Claim 1)
In the first aspect of the present invention, the viscosity of the coating insulating film for forming the first protective film is appropriately set so that the first protective film embeds up to the side wall portion of the electrode and spreads in a skirt shape. Reduce the step on the device surface. Then, by appropriately setting the viscosity of the coating insulating film for forming the second protective film, the second protective film covers from the upper peripheral edge to the top of the electrode. Note that the viscosity and the coating amount of the coating insulating film for forming each protective film may be set by experimentally finding the optimum values by cut-and-try.

その結果、第1保護膜によってデバイス表面の段差が緩和されているため、第2保護膜
となる塗布絶縁膜を塗布したとき、電極の上部周縁部から頂部までを覆う当該塗布絶縁膜
に肉退けが生じ難くなり、上部周縁部および頂部を覆う部分の第2保護膜の膜厚が厚くな
るため、電極の高さが大きくなっても(電極の膜厚が厚くなっても)、各保護膜の段差被
覆性を向上させることができる。従って、請求項1に記載の発明によれば、従来技術の図
13(C)に示すような保護膜の亀裂や剥離を防止可能であり、各保護膜が水分の進入を
確実に防ぐため短絡が起きない。
As a result, since the step on the device surface is relaxed by the first protective film, when the coating insulating film serving as the second protective film is applied, the coating insulating film covering from the upper peripheral edge to the top of the electrode is rejected. Since the thickness of the second protective film in the portion covering the upper peripheral edge and the top is increased, each protective film can be formed even if the electrode height is increased (even if the electrode film thickness is increased). The step coverage can be improved. Therefore, according to the first aspect of the present invention, it is possible to prevent cracking and peeling of the protective film as shown in FIG. 13C of the prior art, and each protective film reliably prevents moisture from entering, and thus short-circuited. Does not happen.

そして、請求項1に記載の発明によれば、従来技術の図13(B)に示すような厚い保
護膜を形成するのに比べて、各保護膜となる塗布絶縁膜の合計塗布量を少なくすることが
可能であるため、高価な塗布絶縁膜の材料コストを削減して製造コストの低コスト化を図
ることができる。
And according to invention of Claim 1, compared with forming a thick protective film as shown to FIG. 13 (B) of a prior art, the total coating amount of the coating insulating film used as each protective film is small. Therefore, it is possible to reduce the material cost of the expensive coating insulating film and to reduce the manufacturing cost.

(請求項2)
請求項2に記載の発明によれば、請求項1に記載の発明に比べて、第2保護膜となる塗
布絶縁膜の塗布量を少なくすることが可能であるため、請求項1に記載の発明よりも更に
製造コストを低減できる。
(Claim 2)
According to the invention described in claim 2, since it is possible to reduce the coating amount of the coating insulating film serving as the second protective film, compared to the invention described in claim 1, the invention described in claim 1 is provided. The manufacturing cost can be further reduced than the invention.

(請求項3)
請求項3に記載の発明によれば、請求項1に記載の発明に比べて、第1保護膜または第
2保護膜の少なくともいずれかを多層構造にした分だけ、各保護膜全体の段差被覆性を更
に向上させることが可能になり、各保護膜によって電極を確実に覆って保護することがで
きる。
(Claim 3)
According to the third aspect of the present invention, compared with the first aspect of the invention, the step coverage of the entire protective film is equivalent to the multilayer structure of at least one of the first protective film and the second protective film. It is possible to further improve the property, and the electrodes can be reliably covered and protected by each protective film.

(請求項4)
請求項4に記載の発明によれば、請求項1に記載の半導体装置を製造することが可能に
なり、請求項1に記載の発明と同様の効果が得られる。
(Claim 4)
According to the invention described in claim 4, it is possible to manufacture the semiconductor device described in claim 1, and the same effect as that of the invention described in claim 1 can be obtained.

(請求項5)
請求項5に記載の発明によれば、保護膜を形成するための塗布絶縁膜を塗布したとき、
その塗布絶縁膜は電極とダミー部材との間の空隙部分を満たし、その空隙部分を満たした
塗布絶縁膜の表面張力により、電極の上部周縁部から頂部までを覆う当該塗布絶縁膜に肉
退けが生じ難くなる。尚、保護膜を形成するための塗布絶縁膜の粘度および塗布量は、カ
ット・アンド・トライで実験的に最適値を見つけて設定すればよい。
(Claim 5)
According to the invention of claim 5, when a coating insulating film for forming a protective film is applied,
The coating insulating film fills the gap between the electrode and the dummy member, and the surface tension of the coating insulating film filling the gap causes the coating insulating film covering from the upper peripheral edge to the top of the electrode to be rejected. It becomes difficult to occur. The viscosity and the coating amount of the coating insulating film for forming the protective film may be set by experimentally finding the optimum value by cut-and-try.

その結果、電極の上部周縁部および頂部を覆う部分の保護膜の膜厚が厚くなり、保護膜
表面の段差が小さくなるため、電極の高さが大きくなっても(電極の膜厚が厚くなっても
)、保護膜の段差被覆性を向上させることができる。従って、請求項5に記載の発明によ
れば、従来技術の図13(C)に示すような保護膜の亀裂や剥離を防止可能であり、保護
膜が水分の進入を確実に防ぐため短絡が起きない。
As a result, the thickness of the protective film covering the upper peripheral edge and the top of the electrode is increased, and the step on the surface of the protective film is reduced, so that even if the electrode height is increased (the electrode thickness is increased). However, the step coverage of the protective film can be improved. Therefore, according to the invention described in claim 5, it is possible to prevent cracking and peeling of the protective film as shown in FIG. 13C of the prior art, and the protective film reliably prevents moisture from entering, so that a short circuit is prevented. I don't get up.

そして、請求項5に記載の発明によれば、従来技術の図13(B)に示すような厚い保
護膜を形成するのに比べて、ダミー部材の体積分だけ、保護膜となる塗布絶縁膜の塗布量
を少なくすることが可能であるため、高価な塗布絶縁膜の材料コストを削減して製造コス
トの低コスト化を図ることができる。
According to the invention described in claim 5, compared to forming a thick protective film as shown in FIG. 13B of the prior art, the coating insulating film that becomes the protective film only by the volume of the dummy member Therefore, it is possible to reduce the manufacturing cost by reducing the material cost of the expensive coating insulating film.

(請求項6)
請求項6に記載の発明によれば、ダミー部材が電極と同じ材料によって形成されている
ため、ダミー部材を電極と同一工程で同時に形成可能であることから、ダミー部材を形成
するための特別な工程の追加が不要であり、ダミー部材を形成することによる製造コスト
の増大がない。
(Claim 6)
According to the sixth aspect of the present invention, since the dummy member is formed of the same material as the electrode, the dummy member can be formed at the same time in the same process as the electrode. No additional process is required, and there is no increase in manufacturing cost due to the formation of the dummy member.

(請求項7)
請求項7に記載の発明によれば、請求項6に記載の半導体装置を製造することが可能に
なり、請求項6に記載の発明と同様の効果が得られる。
(Claim 7)
According to the seventh aspect of the invention, the semiconductor device according to the sixth aspect can be manufactured, and the same effect as that of the sixth aspect of the invention can be obtained.

(請求項8)
請求項8に記載の発明によれば、ダミー部材を電極とは別材料である絶縁材料によって
形成するため、基板表面から電極の頂部までの高さ(電極高さ)に対して、基板表面から
ダミー部材の頂部までの高さ(ダミー部材高さ)を小さく形成することが可能である。そ
のため、電極高さに対してダミー部材高さを小さくした分だけ、保護膜となる塗布絶縁膜
の塗布量を少なくすることができる。尚、ダミー部材高さは、カット・アンド・トライで
実験的に最適値を見つけて設定すればよい。
(Claim 8)
According to the eighth aspect of the present invention, since the dummy member is formed of an insulating material that is a different material from the electrode, the height from the substrate surface to the top of the electrode (electrode height) is reduced from the substrate surface. It is possible to reduce the height to the top of the dummy member (dummy member height). Therefore, the coating amount of the coating insulating film serving as the protective film can be reduced by the amount that the dummy member height is reduced with respect to the electrode height. The dummy member height may be set by experimentally finding the optimum value by cutting and trying.

(請求項9)
請求項9に記載の発明によれば、ダミー部材を絶縁材料である第1塗布絶縁膜によって
形成するため、請求項8に記載の半導体装置を製造することが可能になり、請求項8に記
載の発明と同様の効果が得られる。
(Claim 9)
According to the invention described in claim 9, since the dummy member is formed by the first coating insulating film which is an insulating material, the semiconductor device according to claim 8 can be manufactured. The same effect as that of the present invention can be obtained.

以下、本発明を具体化した各実施形態について図面を参照しながら説明する。尚、各実
施形態において、図12および図13に示した従来技術と同一構成部材については符号を
等しくしてある。また、各実施形態において、第1実施形態と同一内容の箇所については
説明を省略してある。
Hereinafter, embodiments embodying the present invention will be described with reference to the drawings. In each embodiment, the same constituent members as those in the prior art shown in FIGS. 12 and 13 are denoted by the same reference numerals. Moreover, in each embodiment, description is abbreviate | omitted about the location of the same content as 1st Embodiment.

(第1実施形態)
図1および図12は、第1実施形態の半導体装置の製造方法を説明するための概略断面
図である。
(First embodiment)
1 and 12 are schematic cross-sectional views for explaining the semiconductor device manufacturing method of the first embodiment.

工程1〜工程3(図12(A)〜(C)):従来技術の工程1〜工程3と同じである。
工程4(図1(A)):従来技術の工程4(図13(A))と同じである。
Step 1 to Step 3 (FIGS. 12A to 12C): The same as Step 1 to Step 3 of the prior art.
Step 4 (FIG. 1A): Same as step 4 in the prior art (FIG. 13A).

工程5(図1(B)):銅電極87上およびシリコン窒化膜83上を含むデバイスの全
面に塗布絶縁膜を塗布した後に硬化させて保護膜1を形成する。
Step 5 (FIG. 1B): A coating insulating film is applied to the entire surface of the device including the copper electrode 87 and the silicon nitride film 83 and then cured to form the protective film 1.

工程6(図1(C)):銅電極87上および保護膜1上を含むデバイスの全面に塗布絶
縁膜を塗布した後に硬化させて保護膜2を形成する。
Step 6 (FIG. 1C): A coating insulating film is applied to the entire surface of the device including the copper electrode 87 and the protective film 1 and then cured to form the protective film 2.

[第1実施形態の作用・効果]
第1実施形態の半導体装置では、デバイスの表面を覆って保護するための保護膜1,2
が、銅電極87の側壁87aまでを埋め込む保護膜1(第1保護膜)と、保護膜1および
銅電極87の上部周縁部87b上から頂部87c上を覆う保護膜2(第2保護膜)との2
層構造になっている。尚、各保護膜1,2を形成するための塗布絶縁膜の材料としては、
従来技術の保護膜88と同様に各種塗布絶縁膜を用いればよい。
[Operations and effects of the first embodiment]
In the semiconductor device of the first embodiment, protective films 1 and 2 for covering and protecting the surface of the device
The protective film 1 (first protective film) that embeds up to the side wall 87a of the copper electrode 87, and the protective film 2 (second protective film) that covers the protective film 1 and the upper peripheral portion 87b of the copper electrode 87 from the top 87c. And 2
It has a layered structure. In addition, as a material of the coating insulating film for forming each protective film 1, 2,
Various coating insulating films may be used in the same manner as the protective film 88 of the prior art.

そして、工程5(図1(B))では、保護膜1を形成するための塗布絶縁膜の粘度を適
宜設定することにより、保護膜1が銅電極87の側壁87aまでを埋め込んで裾野状に広
がるようにしてデバイス表面の段差を緩和しておく。また、工程6(図1(C))では、
保護膜2を形成するための塗布絶縁膜の粘度を適宜設定することにより、保護膜2が銅電
極87の上部周縁部87b上から頂部87c上までを覆うようにする。
Then, in step 5 (FIG. 1B), the protective film 1 embeds up to the side wall 87a of the copper electrode 87 by setting the viscosity of the coating insulating film for forming the protective film 1 as appropriate. The steps on the device surface are alleviated so as to spread. In step 6 (FIG. 1C),
By appropriately setting the viscosity of the coating insulating film for forming the protective film 2, the protective film 2 covers the upper peripheral portion 87 b to the top portion 87 c of the copper electrode 87.

尚、各保護膜1,2を形成するための塗布絶縁膜の粘度および塗布量は、カット・アン
ド・トライで実験的に最適値を見つけて設定すればよい。例えば、保護膜1の粘度を保護
膜2の粘度よりも小さく設定すればよい。つまり、保護膜1の目的は、銅電極87の側壁
87aのアンダーカット形状部分を埋めることにあるためである。
The viscosity and the coating amount of the coating insulating film for forming the protective films 1 and 2 may be set by experimentally finding the optimum values by cut and try. For example, the viscosity of the protective film 1 may be set smaller than the viscosity of the protective film 2. That is, the purpose of the protective film 1 is to fill the undercut portion of the side wall 87 a of the copper electrode 87.

その結果、保護膜1によってデバイス表面の段差が緩和されているため、保護膜2とな
る塗布絶縁膜を塗布したとき、銅電極87の上部周縁部87b上から頂部87c上までを
覆う当該塗布絶縁膜に肉退けが生じ難くなり、各部87b,87cを覆う部分の保護膜2
の膜厚が厚くなる。そのため、銅電極87の膜厚が厚くなっても(例えば、10μm程度
)、保護膜1,2の段差被覆性を向上させることができる。
As a result, since the step on the device surface is relaxed by the protective film 1, the coating insulation covering from the upper peripheral edge 87 b to the top 87 c of the copper electrode 87 when the coating insulating film to be the protective film 2 is applied. Protective film 2 in the part covering each part 87b, 87c is less likely to cause meat erosion.
The film thickness becomes thicker. Therefore, even if the copper electrode 87 is thick (for example, about 10 μm), the step coverage of the protective films 1 and 2 can be improved.

従って、第1実施形態によれば、従来技術の図13(C)に示すような保護膜88の亀
裂88aや剥離88bを防止可能であり、保護膜1,2が水分の進入を確実に防ぐため短
絡が起きない。
Therefore, according to the first embodiment, it is possible to prevent the crack 88a and the separation 88b of the protective film 88 as shown in FIG. 13C of the prior art, and the protective films 1 and 2 reliably prevent moisture from entering. Therefore, a short circuit does not occur.

加えて、第1実施形態によれば、従来技術の図13(B)に示すような厚い保護膜88
を形成するのに比べて、各保護膜1,2となる塗布絶縁膜の合計塗布量を少なくすること
が可能であるため、高価な塗布絶縁膜の材料コストを削減して製造コストの低コスト化を
図ることができる。
In addition, according to the first embodiment, a thick protective film 88 as shown in FIG.
The total coating amount of the coating insulating film that becomes each of the protective films 1 and 2 can be reduced compared to forming the protective film 1, thereby reducing the material cost of the expensive coating insulating film and reducing the manufacturing cost. Can be achieved.

(第2実施形態)
図2および図12は、第2実施形態の半導体装置の製造方法を説明するための概略断面
図である。
(Second Embodiment)
2 and 12 are schematic cross-sectional views for explaining the semiconductor device manufacturing method of the second embodiment.

工程1〜工程3(図12(A)〜(C)):従来技術の工程1〜工程3と同じである。
工程4(図2(A)):従来技術の工程4(図13(A))と同じである。工程5(図2
(B)):第1実施形態の工程5(図1(B))と同じである。
Step 1 to Step 3 (FIGS. 12A to 12C): The same as Step 1 to Step 3 of the prior art.
Step 4 (FIG. 2A): Same as step 4 in the prior art (FIG. 13A). Step 5 (FIG. 2
(B)): Same as step 5 in the first embodiment (FIG. 1B).

工程6(図2(C)):銅電極87の上部周縁部87b上から頂部87c上だけに塗布
絶縁膜を塗布した後に硬化させて保護膜3を形成する。
Step 6 (FIG. 2C): A coating insulating film is applied only from the upper peripheral edge 87b of the copper electrode 87 to the top 87c, and then cured to form the protective film 3.

[第2実施形態の作用・効果]
第2実施形態の半導体装置では、デバイスの表面を覆って保護するための保護膜1,3
が、銅電極87の側壁87aまでを埋め込む保護膜1(第1保護膜)と、銅電極87の上
部周縁部87b上から頂部87c上のみを覆う保護膜3(第2保護膜)との2層構造にな
っている。尚、各保護膜1,3を形成するための塗布絶縁膜の材料としては、従来技術の
保護膜88と同様に各種塗布絶縁膜を用いればよい。
[Operation and Effect of Second Embodiment]
In the semiconductor device of the second embodiment, protective films 1 and 3 for covering and protecting the surface of the device
2 of the protective film 1 (first protective film) that embeds up to the side wall 87a of the copper electrode 87 and the protective film 3 (second protective film) that covers only the top portion 87c from the upper peripheral edge portion 87b of the copper electrode 87. It has a layered structure. In addition, as a material of the coating insulating film for forming the protective films 1 and 3, various coating insulating films may be used similarly to the protective film 88 of the prior art.

そして、工程6(図2(C))では、保護膜3を形成するための塗布絶縁膜の粘度を適
宜な高い粘度に設定することにより、保護膜3が銅電極87の上部周縁部87b上から頂
部87c上のみを覆うようにする。
In step 6 (FIG. 2C), the protective film 3 is formed on the upper peripheral edge 87b of the copper electrode 87 by setting the viscosity of the coating insulating film for forming the protective film 3 to an appropriate high viscosity. Only the top 87c is covered.

尚、各保護膜1,3を形成するための塗布絶縁膜の粘度および塗布量は、カット・アン
ド・トライで実験的に最適値を見つけて設定すればよい。例えば、保護膜1の粘度を保護
膜3の粘度よりも小さく設定すればよい。つまり、保護膜1の目的は、銅電極87の側壁
87aのアンダーカット形状部分を埋めることにあるためである。
Note that the viscosity and the coating amount of the coating insulating film for forming the protective films 1 and 3 may be set by experimentally finding the optimum values by cut-and-try. For example, the viscosity of the protective film 1 may be set smaller than the viscosity of the protective film 3. That is, the purpose of the protective film 1 is to fill the undercut portion of the side wall 87 a of the copper electrode 87.

その結果、保護膜3となる塗布絶縁膜を塗布したとき、その塗布絶縁膜の表面張力によ
って銅電極87の上部周縁部87b上から頂部87c上のみを厚い塗布絶縁膜が覆い、各
部87b,87cを覆う保護膜3の膜厚が厚くなる。そのため、銅電極87の膜厚が厚く
なっても(例えば、10μm程度)、保護膜1,3の段差被覆性を向上させることができ
る。
As a result, when a coating insulating film serving as the protective film 3 is applied, the thick coating insulating film covers only the top peripheral portion 87c from the upper peripheral portion 87b of the copper electrode 87 due to the surface tension of the coating insulating film, and the respective portions 87b, 87c. The film thickness of the protective film 3 covering the film increases. Therefore, even if the copper electrode 87 is thick (for example, about 10 μm), the step coverage of the protective films 1 and 3 can be improved.

従って、第2実施形態によれば、第1実施形態と同様に、従来技術の図13(C)に示
すような保護膜88の亀裂88aや剥離88bを防止可能であり、保護膜1,3が水分の
進入を確実に防ぐため短絡が起きない。
Therefore, according to the second embodiment, similarly to the first embodiment, it is possible to prevent the crack 88a and the separation 88b of the protective film 88 as shown in FIG. Does not cause a short circuit to prevent moisture from entering.

加えて、第2実施形態によれば、第1実施形態の保護膜2に比べて、保護膜3となる塗
布絶縁膜の塗布量を少なくすることが可能であるため、第1実施形態よりも更に製造コス
トを低減できる。
In addition, according to the second embodiment, it is possible to reduce the coating amount of the coating insulating film to be the protective film 3 as compared with the protective film 2 of the first embodiment. Furthermore, the manufacturing cost can be reduced.

(第3実施形態)
図3および図12は、第3実施形態の半導体装置の製造方法を説明するための概略断面
図である。
(Third embodiment)
3 and 12 are schematic cross-sectional views for explaining the semiconductor device manufacturing method of the third embodiment.

工程1〜工程3(図12(A)〜(C)):従来技術の工程1〜工程3と同じである。
工程4(図2(A)):従来技術の工程4(図13(A))と同じである。
Step 1 to Step 3 (FIGS. 12A to 12C): The same as Step 1 to Step 3 of the prior art.
Step 4 (FIG. 2A): Same as step 4 in the prior art (FIG. 13A).

工程5(図3(B)):銅電極87上およびシリコン窒化膜83上を含むデバイスの全
面に塗布絶縁膜を塗布した後に硬化させて保護膜4を形成する。次に、銅電極87上およ
び保護膜4上を含むデバイスの全面に塗布絶縁膜を塗布した後に硬化させて保護膜5を形
成する。
Step 5 (FIG. 3B): A coating insulating film is applied to the entire surface of the device including the copper electrode 87 and the silicon nitride film 83 and then cured to form the protective film 4. Next, a coating insulating film is applied to the entire surface of the device including the copper electrode 87 and the protective film 4 and then cured to form the protective film 5.

工程6(図3(C)):銅電極87上および保護膜4上を含むデバイスの全面に塗布絶
縁膜を塗布した後に硬化させて保護膜6を形成する。次に、保護膜4上に塗布絶縁膜を塗
布した後に硬化させて保護膜7を形成する。
Step 6 (FIG. 3C): A coating insulating film is applied to the entire surface of the device including the copper electrode 87 and the protective film 4 and then cured to form the protective film 6. Next, a coating insulating film is applied on the protective film 4 and then cured to form the protective film 7.

[第3実施形態の作用・効果]
第3実施形態の半導体装置では、デバイスの表面を覆って保護するための保護膜4〜7
が、銅電極87の側壁87aまでを埋め込む2層の保護膜4,5(第1保護膜)と、銅電
極87の上部周縁部87b上から頂部87c上を覆う2層保護膜6,7(第2保護膜)と
の合計4層構造になっている。尚、各保護膜4〜7を形成するための塗布絶縁膜の材料と
しては、従来技術の保護膜88と同様に各種塗布絶縁膜を用いればよい。
[Operation and Effect of Third Embodiment]
In the semiconductor device of the third embodiment, protective films 4 to 7 are provided to cover and protect the surface of the device.
However, the two-layer protective films 4 and 5 (first protective film) that embed up to the side wall 87a of the copper electrode 87 and the two-layer protective films 6 and 7 (from the upper peripheral edge 87b to the top 87c of the copper electrode 87) 4 layers in total with the second protective film). In addition, as a material of the coating insulating film for forming each protective film 4-7, various coating insulating films may be used similarly to the protective film 88 of the prior art.

そして、工程5(図3(B))では、各保護膜4,5を形成するための塗布絶縁膜の粘
度を適宜設定することにより、各保護膜4,5が銅電極87の側壁87aまでを埋め込ん
で裾野状に広がるようにしてデバイス表面の段差を緩和しておく。ここで、第1実施形態
のように1層の保護膜1だけで銅電極87の側壁87aまでを埋め込むのに比べて、第3
実施形態では、2層の保護膜4,5を順次形成することにより、銅電極87の側壁87a
までを各保護膜4,5によって確実に埋め込むことができる。
In step 5 (FIG. 3B), the viscosity of the coating insulating film for forming the protective films 4 and 5 is appropriately set so that the protective films 4 and 5 reach the side wall 87a of the copper electrode 87. The step on the surface of the device is eased by embedding and spreading in a skirt shape. Here, as compared with the case where the side wall 87a of the copper electrode 87 is buried with only one protective film 1 as in the first embodiment, the third
In the embodiment, the side walls 87a of the copper electrode 87 are formed by sequentially forming the two protective films 4 and 5.
Can be reliably embedded by the protective films 4 and 5.

また、工程6(図3(C))では、各保護膜6,7を形成するための塗布絶縁膜の粘度
を適宜設定することにより、各保護膜6,7が銅電極87の上部周縁部87b上から頂部
87c上までを覆うようにする。
Further, in step 6 (FIG. 3C), the protective film 6, 7 is formed on the upper peripheral portion of the copper electrode 87 by appropriately setting the viscosity of the coating insulating film for forming the protective film 6, 7. Cover from 87b to the top 87c.

尚、各保護膜4〜7を形成するための塗布絶縁膜の粘度および塗布量は、カット・アン
ド・トライで実験的に最適値を見つけて設定すればよい。例えば、保護膜4,5の粘度を
保護膜6,7の粘度よりも小さく設定すればよい。つまり、保護膜4,5の目的は、銅電
極87の側壁87aのアンダーカット形状部分を埋めることにあるためである。
Note that the viscosity and the coating amount of the coating insulating film for forming each of the protective films 4 to 7 may be set by experimentally finding the optimum values by cut-and-try. For example, the viscosity of the protective films 4 and 5 may be set smaller than the viscosity of the protective films 6 and 7. That is, the purpose of the protective films 4 and 5 is to fill the undercut shape portion of the side wall 87 a of the copper electrode 87.

その結果、各保護膜4,5によってデバイス表面の段差が緩和されているため、保護膜
6となる塗布絶縁膜を塗布したとき、銅電極87の上部周縁部87b上から頂部87c上
までを覆う当該塗布絶縁膜に肉退けが生じ難くなり、各部87b,87cを覆う部分の保
護膜6の膜厚が厚くなる。そして、各保護膜4,5に加えた保護膜6によってデバイス表
面の段差が更に緩和されるため、保護膜7となる塗布絶縁膜を塗布したとき、各部87b
,87cを覆う部分の保護膜7の膜厚が厚くなる。
As a result, the steps on the device surface are alleviated by the protective films 4 and 5, so that when the coating insulating film to be the protective film 6 is applied, the copper electrode 87 is covered from the upper peripheral edge 87 b to the top 87 c. It is difficult for the coating insulating film to lose its thickness, and the thickness of the protective film 6 covering the portions 87b and 87c increases. Further, since the step on the device surface is further relaxed by the protective film 6 added to the protective films 4 and 5, when the coating insulating film to be the protective film 7 is applied, each portion 87b
, 87c, the thickness of the protective film 7 is increased.

従って、第1実施形態のように2層の保護膜1,2だけで銅電極87を覆うのに比べて
、第3実施形態によれば、各保護膜4〜7全体の段差被覆性を更に向上させることが可能
になり、2層の保護膜4〜7によって銅電極87を確実に覆って保護することができる。
尚、第3実施形態では4層の保護膜4〜7を形成したが、3層または5層以上の保護膜を
形成してもよい。
Therefore, compared to covering the copper electrode 87 with only the two protective films 1 and 2 as in the first embodiment, the third embodiment further increases the step coverage of each of the protective films 4 to 7. Thus, the copper electrode 87 can be reliably covered and protected by the two protective films 4 to 7.
In the third embodiment, the four protective films 4 to 7 are formed. However, three or more protective films may be formed.

(第4実施形態)
図4および図5は、第4実施形態の半導体装置の製造方法を説明するための概略断面図
である。
(Fourth embodiment)
4 and 5 are schematic cross-sectional views for explaining the method for manufacturing the semiconductor device of the fourth embodiment.

工程1(図4(A)):従来技術の工程1(図12(A))と同様に、基板81上に、
配線層82、シリコン窒化膜83、バリアメタル層84、シード層85を順次形成する。
Step 1 (FIG. 4A): Similar to Step 1 of the prior art (FIG. 12A), on the substrate 81,
A wiring layer 82, a silicon nitride film 83, a barrier metal layer 84, and a seed layer 85 are sequentially formed.

そして、シード層85上に厚いフォトレジスト膜86を形成し、フォトリソグラフィ法
を用い、配線層82の上方のフォトレジスト膜86を除去して電極形成用開孔部86aを
形成すると共に、配線層82の両側近傍のフォトレジスト膜86を除去してダミー部材形
成用開孔部86b,86cを形成する。ここで、フォトレジスト膜86の膜厚は、後述す
る銅電極87の膜厚(高さ)に比べて十分に厚くなるように形成する必要がある。
Then, a thick photoresist film 86 is formed on the seed layer 85, and the photoresist film 86 above the wiring layer 82 is removed by using a photolithography method to form an electrode forming hole 86a, and the wiring layer The photoresist film 86 in the vicinity of both sides of 82 is removed to form dummy member forming openings 86b and 86c. Here, the film thickness of the photoresist film 86 needs to be formed to be sufficiently thicker than the film thickness (height) of a copper electrode 87 described later.

このように、フォトレジスト膜86の膜厚が厚い場合には、フォトリソグラフィ法の露
光特性から、各開孔部86a〜86cの形状は、上部から下部に向かって横断面積が次第
に小さくなり窄まったものになる。
Thus, when the thickness of the photoresist film 86 is large, the shape of each of the apertures 86a to 86c becomes narrower as the cross-sectional area gradually decreases from the top to the bottom due to the exposure characteristics of the photolithography method. It becomes a thing.

工程2(図4(B)):各開孔部86a〜86c底部に露出したシード層85上にメッ
キ法を用いて銅を堆積させて各開孔部86a〜86c内を埋めることにより銅電極87お
よび各ダミー部材11a,11bを同時に形成する。
Step 2 (FIG. 4B): Copper is deposited on the seed layer 85 exposed at the bottoms of the openings 86a to 86c by using a plating method to fill the openings 86a to 86c with copper electrodes. 87 and the dummy members 11a and 11b are formed simultaneously.

工程3(図4(C)):フォトレジスト膜86をアッシング法などを用いて除去し、バ
リアメタル層84、シード層85、銅電極87、各ダミー部材11a,11bを露出させ
る。ここで、銅電極87および各ダミー部材11a,11bの形状はそれぞれ、各開孔部
86a〜86cの形状に沿ったものになり、上部から下部に向かって横断面積が次第に小
さくなり窄まったものになる。そして、銅電極87の側壁87aは、基板81表面に対し
て鋭角の勾配をなし、アンダーカット形状となる。
Step 3 (FIG. 4C): The photoresist film 86 is removed using an ashing method or the like to expose the barrier metal layer 84, the seed layer 85, the copper electrode 87, and the dummy members 11a and 11b. Here, the shapes of the copper electrode 87 and the dummy members 11a and 11b are in accordance with the shapes of the openings 86a to 86c, respectively, and the cross-sectional area gradually decreases from the upper part toward the lower part and becomes narrower. become. The side wall 87a of the copper electrode 87 has an acute angle gradient with respect to the surface of the substrate 81 and has an undercut shape.

工程4(図5(A)):銅電極87の下部のバリアメタル層84およびシード層85を
除き、デバイス表面に露出しているバリアメタル層84およびシード層85をウエットエ
ッチング法を用いて除去する。このとき、銅電極87の上部周縁も削り取られ、アールが
付けられた上部周縁部87bが形成される。また、各ダミー部材11a,11bの上部周
縁も削り取られてアールが付けられる。
Step 4 (FIG. 5A): The barrier metal layer 84 and the seed layer 85 exposed on the device surface are removed using a wet etching method except for the barrier metal layer 84 and the seed layer 85 below the copper electrode 87. To do. At this time, the upper peripheral edge of the copper electrode 87 is also scraped off to form an upper peripheral edge 87b with a radius. Moreover, the upper periphery of each dummy member 11a, 11b is also scraped off and rounded.

工程5(図5(B)):銅電極87上と各ダミー部材11a,11b上およびシリコン
窒化膜83上を含むデバイスの全面に塗布絶縁膜を塗布した後に硬化させて保護膜12を
形成する。尚、保護膜12を形成するための塗布絶縁膜の材料としては、従来技術の保護
膜88と同様に各種塗布絶縁膜を用いればよい。
Step 5 (FIG. 5B): A coating insulating film is applied to the entire surface of the device including the copper electrode 87, the dummy members 11a and 11b, and the silicon nitride film 83, and then cured to form the protective film 12. . In addition, as a material of the coating insulating film for forming the protective film 12, various coating insulating films may be used like the protective film 88 of the prior art.

[第4実施形態の作用・効果]
第4実施形態の半導体装置では、配線層82上に形成された銅電極87の両側近傍に、
銅電極87と同じ材料(銅または銅合金)からなる各ダミー部材11a,11bが形成さ
れており、銅電極87および各ダミー部材11a,11bを覆う保護膜12が形成されて
いる。
[Operations and effects of the fourth embodiment]
In the semiconductor device of the fourth embodiment, near both sides of the copper electrode 87 formed on the wiring layer 82,
Dummy members 11a and 11b made of the same material (copper or copper alloy) as the copper electrode 87 are formed, and a protective film 12 covering the copper electrode 87 and the dummy members 11a and 11b is formed.

そのため、保護膜12となる塗布絶縁膜を塗布したとき、その塗布絶縁膜は銅電極87
と各ダミー部材11a,11bとの間の空隙部分Sを満たし、その空隙部分Sを満たした
塗布絶縁膜の表面張力により、銅電極87の上部周縁部87b上から頂部87c上までを
覆う当該塗布絶縁膜に肉退けが生じ難くなる。尚、保護膜12を形成するための塗布絶縁
膜の粘度および塗布量は、カット・アンド・トライで実験的に最適値を見つけて設定すれ
ばよい。
Therefore, when a coating insulating film to be the protective film 12 is applied, the coating insulating film is a copper electrode 87.
Is applied to cover from the upper peripheral edge 87b to the top 87c of the copper electrode 87 by the surface tension of the coating insulating film that fills the gap S between each of the dummy members 11a and 11b. The insulation film is less likely to be rejected. It should be noted that the viscosity and the coating amount of the coating insulating film for forming the protective film 12 may be set by experimentally finding optimum values by cut-and-try.

その結果、銅電極87の各部87b,87cを覆う部分の保護膜12の膜厚が厚くなり
、保護膜12表面の段差12aが小さくなるため、銅電極87の膜厚が厚くなっても(例
えば、10μm程度)、保護膜12の段差被覆性を向上させることができる。従って、第
4実施形態によれば、従来技術の図13(C)に示すような保護膜88の亀裂88aや剥
離88bを防止可能であり、保護膜12が水分の進入を確実に防ぐため短絡が起きない。
As a result, the thickness of the protective film 12 covering the portions 87b and 87c of the copper electrode 87 is increased and the step 12a on the surface of the protective film 12 is reduced, so that even if the thickness of the copper electrode 87 is increased (for example, 10 μm), the step coverage of the protective film 12 can be improved. Therefore, according to the fourth embodiment, it is possible to prevent the crack 88a and the separation 88b of the protective film 88 as shown in FIG. 13C of the prior art, and the protective film 12 reliably prevents the ingress of moisture. Does not happen.

そして、第4実施形態によれば、従来技術の図13(B)に示すような厚い保護膜88
を形成するのに比べて、各ダミー部材11a,11bの体積分だけ、保護膜12となる塗
布絶縁膜の塗布量を少なくすることが可能であるため、高価な塗布絶縁膜の材料コストを
削減して製造コストの低コスト化を図ることができる。
And according to 4th Embodiment, the thick protective film 88 as shown to FIG. 13 (B) of a prior art.
Compared with the formation of the film, the amount of the coating insulating film to be the protective film 12 can be reduced by the volume of each dummy member 11a, 11b, thereby reducing the material cost of the expensive coating insulating film. Thus, the manufacturing cost can be reduced.

加えて、第4実施形態によれば、各ダミー部材11a,11bを銅電極87と同一工程
で同時に形成可能であるため、各ダミー部材11a,11bを形成するための特別な工程
の追加が不要であり、各ダミー部材11a,11bを形成することによる製造コストの増
大がない。
In addition, according to the fourth embodiment, since the dummy members 11a and 11b can be formed simultaneously with the copper electrode 87 in the same process, it is not necessary to add a special process for forming the dummy members 11a and 11b. Thus, there is no increase in manufacturing cost due to the formation of the dummy members 11a and 11b.

図6(A)〜図6(C)は、銅電極87とダミー部材11a〜11dの平面配置の各例
を示すための平面図である。尚、図5は、図6(A)(B)に示すX−X線断面図である
FIGS. 6A to 6C are plan views for illustrating examples of the planar arrangement of the copper electrode 87 and the dummy members 11a to 11d. 5 is a cross-sectional view taken along the line XX shown in FIGS. 6 (A) and 6 (B).

図6(A)は、略四角形状の銅電極87の周囲近傍の四方に直線帯状の各ダミー部材1
1a〜11dを配置した例である。
FIG. 6A shows each of the dummy members 1 in the form of straight strips in the four directions near the periphery of the substantially rectangular copper electrode 87.
This is an example in which 1a to 11d are arranged.

図6(B)は、略四角形状の銅電極87の周囲近傍の二方に直線帯状の各ダミー部材1
1b,11dを配置した例(つまり、図6(A)から各ダミー部材11a,11cを省い
た例)である。尚、図6(A)から各ダミー部材11c,11dを省くようにしてもよい
。また、図6(A)の各ダミー部材11a〜11dから選択されたいずれか1つのダミー
部材だけを残すようにしてもよい。
FIG. 6B shows each dummy member 1 in the form of a straight strip in two directions near the periphery of the substantially rectangular copper electrode 87.
This is an example in which 1b and 11d are arranged (that is, an example in which the dummy members 11a and 11c are omitted from FIG. 6A). Note that the dummy members 11c and 11d may be omitted from FIG. Moreover, you may make it leave only any one dummy member selected from each dummy member 11a-11d of FIG. 6 (A).

図6(C)は、略四角形状の銅電極87の周囲近傍を取り囲む略円環帯状のダミー部材
11a,11bを配置した例である。尚、各ダミー部材11a〜11dの幅および銅電極
87との間隔は、カット・アンド・トライで実験的に最適値を見つけて設定すればよい。
FIG. 6C shows an example in which substantially annular belt-like dummy members 11 a and 11 b surrounding the vicinity of the substantially rectangular copper electrode 87 are arranged. The width of each dummy member 11a to 11d and the distance from the copper electrode 87 may be set by finding an optimum value experimentally by cut-and-try.

図7は、第4実施形態を適用した半導体装置(半導体チップ)の一例を示す概略断面図
である。基板81上には、LDMOSトランジスタ21、CMOS22、バイポーラトラ
ンジスタ23、パッド部24が形成されており、各素子21〜24は素子分離絶縁膜25
によって素子分離され、各素子21〜24上には層間絶縁膜26,27を介して配線層8
2が形成されている。
FIG. 7 is a schematic cross-sectional view showing an example of a semiconductor device (semiconductor chip) to which the fourth embodiment is applied. An LDMOS transistor 21, a CMOS 22, a bipolar transistor 23, and a pad portion 24 are formed on the substrate 81, and each element 21 to 24 is an element isolation insulating film 25.
The element is separated by the wiring layer 8 on each element 21 to 24 via the interlayer insulating films 26 and 27.
2 is formed.

そして、銅電極87は、LDMOSトランジスタ21およびCMOS22のソース・ド
レイン電極、パッド部24の電極として設けられている。また、各ダミー部材11a,1
1bは、銅電極87間の距離が離れているため保護膜12となる塗布絶縁膜の肉退けが起
こりやすい部分(この例では、CMOS22の上方)に設けられている。
The copper electrode 87 is provided as a source / drain electrode of the LDMOS transistor 21 and the CMOS 22 and an electrode of the pad portion 24. Also, each dummy member 11a, 1
1b is provided at a portion (in this example, above the CMOS 22) where the coating insulating film serving as the protective film 12 is likely to lose its thickness because the distance between the copper electrodes 87 is large.

(第5実施形態)
図8〜図10は、第5実施形態の半導体装置の製造方法を説明するための概略断面図で
ある。
(Fifth embodiment)
8 to 10 are schematic cross-sectional views for explaining the semiconductor device manufacturing method of the fifth embodiment.

工程1(図8(A)):基板81上にPVD法を用いてアルミニウム合金膜を形成し、
そのアルミニウム合金膜をパターニングして配線層82を形成する。次に、配線層82上
を含む基板81の全面にCVD法を用いて保護用のシリコン窒化膜83を形成する。続い
て、シリコン窒化膜83上に厚い塗布絶縁膜を塗布した後に硬化させてダミー用膜31を
形成する。尚、ダミー用膜31を形成するための塗布絶縁膜の材料としては、従来技術の
保護膜88と同様に各種塗布絶縁膜を用いればよい。
Step 1 (FIG. 8A): An aluminum alloy film is formed on the substrate 81 using the PVD method,
The wiring layer 82 is formed by patterning the aluminum alloy film. Next, a protective silicon nitride film 83 is formed on the entire surface of the substrate 81 including the wiring layer 82 by CVD. Subsequently, a thick coating insulating film is applied on the silicon nitride film 83 and then cured to form the dummy film 31. As a material for the coating insulating film for forming the dummy film 31, various coating insulating films may be used as in the case of the protective film 88 of the prior art.

工程2(図8(B)):フォトリソグラフィ法およびドライエッチング法を用い、配線
層82の両側近傍(電極87の形成箇所の両側近傍)のダミー用膜31だけを所望の形状
に残して各ダミー部材31a,31bを形成し(ダミー用膜31をパターニングして各ダ
ミー部材31a,31bを形成し)、その他の部分のダミー用膜31を除去する。
Step 2 (FIG. 8B): Using the photolithography method and the dry etching method, each of the dummy films 31 in the vicinity of both sides of the wiring layer 82 (in the vicinity of both sides of the portion where the electrode 87 is formed) is left in a desired shape. Dummy members 31a and 31b are formed (the dummy film 31 is patterned to form the dummy members 31a and 31b), and the other portions of the dummy film 31 are removed.

工程3(図8(C)):配線層82上のシリコン窒化膜83をドライエッチング法を用
いて除去する。次に、露出された配線層82上とシリコン窒化膜83上および各ダミー部
材31a,31b上にPVD法を用いてバリアメタル層84とシード層85とをこの順番
で形成する。
Step 3 (FIG. 8C): The silicon nitride film 83 on the wiring layer 82 is removed using a dry etching method. Next, a barrier metal layer 84 and a seed layer 85 are formed in this order on the exposed wiring layer 82, the silicon nitride film 83, and the dummy members 31 a and 31 b using the PVD method.

工程4(図9(A)):ダミー部材31a,31b上を含むシード層85上に厚いフォ
トレジスト膜86を形成し、フォトリソグラフィ法を用いて配線層82の上方のフォトレ
ジスト膜86を除去し、フォトレジスト膜86に電極形成用開孔部86aを形成する。
Step 4 (FIG. 9A): A thick photoresist film 86 is formed on the seed layer 85 including the dummy members 31a and 31b, and the photoresist film 86 above the wiring layer 82 is removed by photolithography. Then, an electrode forming hole 86 a is formed in the photoresist film 86.

工程5(図9(B)):電極形成用開孔部86a底部に露出したシード層85上にメッ
キ法を用いて銅を堆積させて電極形成用開孔部86a内を埋めることにより銅電極87を
形成する。
Step 5 (FIG. 9B): Copper is deposited on the seed layer 85 exposed at the bottom of the electrode forming aperture 86a by plating to fill the inside of the electrode forming aperture 86a with a copper electrode. 87 is formed.

工程6(図9(C)):フォトレジスト膜86をアッシング法などを用いて除去し、バ
リアメタル層84、シード層85、銅電極87を露出させる。ここで、銅電極87の側壁
87aは、基板81表面に対して鋭角の勾配をなし、アンダーカット形状となる。
Step 6 (FIG. 9C): The photoresist film 86 is removed using an ashing method or the like to expose the barrier metal layer 84, the seed layer 85, and the copper electrode 87. Here, the side wall 87a of the copper electrode 87 has an acute angle gradient with respect to the surface of the substrate 81 and has an undercut shape.

工程7(図10(A)):銅電極87の下部のバリアメタル層84およびシード層85
を除き、デバイス表面に露出しているバリアメタル層84およびシード層85をウエット
エッチング法を用いて除去する。このとき、銅電極87の上部周縁も削り取られ、アール
が付けられた上部周縁部87bが形成される。
Step 7 (FIG. 10A): barrier metal layer 84 and seed layer 85 under copper electrode 87
The barrier metal layer 84 and the seed layer 85 exposed on the device surface are removed using a wet etching method. At this time, the upper peripheral edge of the copper electrode 87 is also scraped off to form an upper peripheral edge 87b with a radius.

工程8(図10(B)):銅電極87上およびシリコン窒化膜83上を含むデバイスの
全面に塗布絶縁膜を塗布した後に硬化させて保護膜12を形成する。
Step 8 (FIG. 10B): A coating insulating film is applied to the entire surface of the device including the copper electrode 87 and the silicon nitride film 83 and then cured to form the protective film 12.

[第5実施形態の作用・効果]
第5実施形態の半導体装置では、配線層82上に形成された銅電極87の両側近傍にダ
ミー用膜31からなる各ダミー部材31a,31bが形成されており、銅電極87および
各ダミー部材31a,31bを覆う保護膜12が形成されている。
[Operation and Effect of Fifth Embodiment]
In the semiconductor device of the fifth embodiment, the dummy members 31a and 31b made of the dummy film 31 are formed near both sides of the copper electrode 87 formed on the wiring layer 82. The copper electrode 87 and the dummy members 31a are formed. , 31b is formed.

そのため、保護膜12となる塗布絶縁膜を塗布したとき、その塗布絶縁膜は銅電極87
と各ダミー部材31a,31bとの間の空隙部分Sを満たし、その空隙部分Sを満たした
塗布絶縁膜の表面張力により、銅電極87の上部周縁部87b上から頂部87c上までを
覆う当該塗布絶縁膜に肉退けが生じ難くなる。尚、保護膜12を形成するための塗布絶縁
膜の粘度および塗布量は、カット・アンド・トライで実験的に最適値を見つけて設定すれ
ばよい。
Therefore, when a coating insulating film to be the protective film 12 is applied, the coating insulating film is a copper electrode 87.
And the coating covering the space from the upper peripheral edge 87b to the top 87c of the copper electrode 87 by the surface tension of the coating insulating film filling the space S between the dummy members 31a and 31b. The insulation film is less likely to be rejected. It should be noted that the viscosity and the coating amount of the coating insulating film for forming the protective film 12 may be set by experimentally finding optimum values by cut-and-try.

その結果、第5実施形態によれば、第4実施形態と同様に、銅電極87の各部87b,
87cを覆う部分の保護膜12の膜厚が厚くなり、保護膜12表面の段差12aが小さく
なるため、保護膜12の段差被覆性を向上させることができる。
As a result, according to the fifth embodiment, each part 87b of the copper electrode 87, as in the fourth embodiment.
Since the thickness of the protective film 12 covering the portion 87c is increased and the step 12a on the surface of the protective film 12 is reduced, the step coverage of the protective film 12 can be improved.

そして、第5実施形態によれば、従来技術の図13(B)に示すような厚い保護膜88
を形成するのに比べて、各ダミー部材31a,31bの体積分だけ、保護膜12となる塗
布絶縁膜の塗布量を少なくすることが可能であるため、高価な塗布絶縁膜の材料コストを
削減して製造コストの低コスト化を図ることができる。
Then, according to the fifth embodiment, a thick protective film 88 as shown in FIG.
Compared to forming the film, the amount of the coating insulating film to be the protective film 12 can be reduced by the volume of each of the dummy members 31a and 31b, thereby reducing the material cost of the expensive coating insulating film. Thus, the manufacturing cost can be reduced.

加えて、第5実施形態によれば、図10(B)に示すように、シリコン窒化膜83表面
から銅電極87の頂部87cまでの高さh1に対して、シリコン窒化膜83表面から各ダ
ミー部材31a,31bの頂部までの高さh2を小さく形成することが可能である。その
ため、高さh1に対して高さh2を小さくした分だけ、保護膜12となる塗布絶縁膜の塗
布量を少なくすることができる。尚、高さh2は、カット・アンド・トライで実験的に最
適値を見つけて設定すればよい。
In addition, according to the fifth embodiment, each dummy from the surface of the silicon nitride film 83 to the height h1 from the surface of the silicon nitride film 83 to the top 87c of the copper electrode 87, as shown in FIG. It is possible to reduce the height h2 to the top of the members 31a and 31b. Therefore, the coating amount of the coating insulating film that becomes the protective film 12 can be reduced by the amount that the height h2 is reduced with respect to the height h1. The height h2 may be set by experimentally finding the optimum value by cut-and-try.

ところで、第5実施形態では、工程1(図8(A))にてデバイス全面に一旦形成した
ダミー用膜31を、工程2(図8(B))にて各ダミー部材31a,31bの部分だけを
残して除去する。そのため、製造コストを抑制するには、ダミー用膜31を形成するため
の塗布絶縁膜の材料として安価なもの(例えば、SOGなど)を用いる必要がある。
By the way, in 5th Embodiment, the dummy film | membrane 31 once formed in the device whole surface at the process 1 (FIG. 8 (A)) is the part of each dummy member 31a, 31b in the process 2 (FIG. 8 (B)). Just leave and remove. Therefore, in order to suppress the manufacturing cost, it is necessary to use an inexpensive material (for example, SOG) as the material of the coating insulating film for forming the dummy film 31.

ちなみに、図6(A)〜図6(C)に示すように、第5実施形態においても、第4実施
形態のダミー部材11a〜11dと同様に、ダミー部材31a〜31dを配置すればよい
。尚、図10は、図6(A)(B)に示すX−X線断面図である。
Incidentally, as shown in FIGS. 6 (A) to 6 (C), in the fifth embodiment, dummy members 31a to 31d may be arranged similarly to the dummy members 11a to 11d of the fourth embodiment. FIG. 10 is a cross-sectional view taken along the line XX shown in FIGS.

図11は、第4実施形態と同様に、第5実施形態を適用した半導体装置(半導体チップ
)の一例を示す概略断面図である。各ダミー部材31a,31bは、銅電極87間の距離
が離れているため保護膜12となる塗布絶縁膜の肉退けが起こりやすい部分(この例では
、CMOS22の上方)に設けられている。
FIG. 11 is a schematic cross-sectional view showing an example of a semiconductor device (semiconductor chip) to which the fifth embodiment is applied, similarly to the fourth embodiment. Each of the dummy members 31a and 31b is provided in a portion (in this example, above the CMOS 22) where the coating insulating film serving as the protective film 12 is likely to lose its thickness because the distance between the copper electrodes 87 is large.

[別の実施形態]
ところで、本発明は上記各実施形態に限定されるものではなく、以下のように具体化し
てもよく、その場合でも、上記各実施形態と同等もしくはそれ以上の作用・効果を得るこ
とができる。
[Another embodiment]
By the way, the present invention is not limited to the above-described embodiments, and may be embodied as follows. Even in this case, operations and effects equivalent to or more than those of the above-described embodiments can be obtained.

(1)図6(A)(C)に示すダミー部材11a〜11d,31a〜31dの配置例で
は各ダミー部材を直線帯状としたが、各ダミー部材の形状は、空隙部分Sを満たした塗布
絶縁膜の表面張力により銅電極87の上部周縁部87b上から頂部87c上までを覆う当
該塗布絶縁膜に肉退けが生じ難くなるのであれば、どのような形状にしてもよい。また、
図6(C)に示す例ではダミー部材を略円環状にしたが、前記と同様の作用が得られるの
であれば、略円環が適宜な箇所で部分的に途切れるような形状にしてもよい。
(1) In the arrangement example of the dummy members 11a to 11d and 31a to 31d shown in FIGS. 6 (A) and 6 (C), each dummy member has a straight belt shape, but the shape of each dummy member is an application filling the gap portion S. Any shape may be used as long as it is difficult for the coating insulating film covering the upper peripheral portion 87b of the copper electrode 87 to the top portion 87c to be easily lost due to the surface tension of the insulating film. Also,
In the example shown in FIG. 6 (C), the dummy member has a substantially annular shape. However, as long as the same effect as described above can be obtained, the dummy member may be shaped so that it is partially interrupted at an appropriate location. .

(2)上記各実施形態では電極87の形成材料として銅または銅合金を用いているが、
電極87の高さを大きくして且つ低抵抗化が可能であれば、どのような形成材料を用いて
もよい。
(2) In each of the above embodiments, copper or a copper alloy is used as a material for forming the electrode 87.
Any forming material may be used as long as the height of the electrode 87 can be increased and the resistance can be reduced.

(3)上記各実施形態は単結晶シリコン基板1上に作成したデバイスに適用したもので
あるが、その他の半導体基板(例えば、ガリウム・ヒ素基板、インジウム・ガリウム・ヒ
素基板など)やSOI(Silicon On Insulator)基板の上に作成したデバイスに適用して
もよい。
(3) Each of the above embodiments is applied to a device formed on the single crystal silicon substrate 1, but other semiconductor substrates (eg, gallium arsenide substrate, indium gallium arsenide substrate, etc.) or SOI (Silicon On Insulator) It may be applied to a device created on a substrate.

本発明を具体化した第1実施形態の半導体装置の製造方法を説明するための概略断面図。BRIEF DESCRIPTION OF THE DRAWINGS The schematic sectional drawing for demonstrating the manufacturing method of the semiconductor device of 1st Embodiment which actualized this invention. 本発明を具体化した第2実施形態の半導体装置の製造方法を説明するための概略断面図。The schematic sectional drawing for demonstrating the manufacturing method of the semiconductor device of 2nd Embodiment which actualized this invention. 本発明を具体化した第3実施形態の半導体装置の製造方法を説明するための概略断面図。The schematic sectional drawing for demonstrating the manufacturing method of the semiconductor device of 3rd Embodiment which actualized this invention. 本発明を具体化した第4実施形態の半導体装置の製造方法を説明するための概略断面図。FIG. 9 is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to a fourth embodiment embodying the present invention. 本発明を具体化した第4実施形態の半導体装置の製造方法を説明するための概略断面図。FIG. 9 is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to a fourth embodiment embodying the present invention. 銅電極87とダミー部材11a〜11d,31a〜31dの平面配置の各例を示すための平面図。The top view for showing each example of plane arrangement of copper electrode 87 and dummy members 11a-11d and 31a-31d. 第4実施形態を適用した半導体装置(半導体チップ)の一例を示す概略断面図。FIG. 10 is a schematic cross-sectional view showing an example of a semiconductor device (semiconductor chip) to which the fourth embodiment is applied. 本発明を具体化した第5実施形態の半導体装置の製造方法を説明するための概略断面図。FIG. 9 is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to a fifth embodiment embodying the present invention. 本発明を具体化した第5実施形態の半導体装置の製造方法を説明するための概略断面図。FIG. 9 is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to a fifth embodiment embodying the present invention. 本発明を具体化した第5実施形態の半導体装置の製造方法を説明するための概略断面図。FIG. 9 is a schematic cross-sectional view for explaining a method for manufacturing a semiconductor device according to a fifth embodiment embodying the present invention. 第5実施形態を適用した半導体装置(半導体チップ)の一例を示す概略断面図。FIG. 10 is a schematic cross-sectional view showing an example of a semiconductor device (semiconductor chip) to which the fifth embodiment is applied. 従来の半導体装置の製造方法を説明するための概略断面図。FIG. 10 is a schematic cross-sectional view for explaining a conventional method for manufacturing a semiconductor device. 従来の半導体装置の製造方法を説明するための概略断面図。FIG. 10 is a schematic cross-sectional view for explaining a conventional method for manufacturing a semiconductor device.

符号の説明Explanation of symbols

1〜7,12…保護膜
11a〜11d,31a〜31d…ダミー部材
31…ダミー用膜
81…シリコン基板
87…銅電極
DESCRIPTION OF SYMBOLS 1-7,12 ... Protective film 11a-11d, 31a-31d ... Dummy member 31 ... Dummy film | membrane 81 ... Silicon substrate 87 ... Copper electrode

Claims (9)

基板上に形成された電極と、その電極を保護するために塗布絶縁膜によって形成された
保護膜とを備えた半導体装置であって、
前記保護膜は、
前記電極の側壁部分までを埋め込んで裾野状に広がる第1保護膜と、
前記電極の上部を覆う第2保護膜と
からなることを特徴とする半導体装置。
A semiconductor device comprising an electrode formed on a substrate and a protective film formed by a coating insulating film to protect the electrode,
The protective film is
A first protective film embedded in the side wall portion of the electrode and spreading in a skirt shape;
A semiconductor device comprising a second protective film covering an upper portion of the electrode.
請求項1に記載の半導体装置において、
前記第2保護膜は、前記電極の上部周縁部および頂部のみを覆うことを特徴とする半導
体装置。
The semiconductor device according to claim 1,
The second protective film covers only the upper peripheral edge and the top of the electrode.
請求項1に記載の半導体装置において、
前記第1保護膜または前記第2保護膜の少なくともいずれかが多層構造をなすことを特
徴とする半導体装置。
The semiconductor device according to claim 1,
At least one of the first protective film and the second protective film has a multilayer structure.
基板上に電極を形成する第1工程と、
前記電極を含む基板上に第1塗布絶縁膜を塗布させた後に硬化させて第1保護膜を形成
する第2工程と、
前記電極上および前記第1保護膜上に第2塗布絶縁膜を塗布させた後に硬化させて第2
保護膜を形成する第3工程と
を備え、
前記第1保護膜は前記電極の側壁部分までを埋め込んで裾野状に広がり、
前記第2保護膜は前記電極の上部を覆うことを特徴とする半導体装置の製造方法。
A first step of forming an electrode on a substrate;
A second step of forming a first protective film by applying a first coating insulating film on the substrate including the electrode and then curing the coating;
A second coating insulating film is applied on the electrode and the first protective film, and then cured to be second.
A third step of forming a protective film,
The first protective film fills up the side wall portion of the electrode and spreads in a skirt shape,
The method for manufacturing a semiconductor device, wherein the second protective film covers an upper portion of the electrode.
基板上に形成された電極と、
その電極の近傍の基板上に形成されたダミー部材と、
前記電極および前記ダミー部材を覆って保護するために塗布絶縁膜によって形成された
保護膜と
を備えたことを特徴とする半導体装置。
An electrode formed on a substrate;
A dummy member formed on the substrate in the vicinity of the electrode;
A semiconductor device comprising: a protective film formed of a coating insulating film to cover and protect the electrode and the dummy member.
請求項5に記載の半導体装置において、
前記ダミー部材は前記電極と同じ材料によって形成されていることを特徴とする半導体
装置。
The semiconductor device according to claim 5,
The semiconductor device, wherein the dummy member is made of the same material as the electrode.
基板上に電極を形成し、それと同時に、前記電極の近傍の基板上に前記電極と同じ材料
によってダミー部材を形成する第1工程と、
前記電極および前記ダミー部材を含む基板上に塗布絶縁膜を塗布させた後に硬化させて
保護膜を形成する第2工程と
を備えたことを特徴とする半導体装置の製造方法。
A first step of forming an electrode on the substrate and simultaneously forming a dummy member on the substrate in the vicinity of the electrode with the same material as the electrode;
And a second step of forming a protective film by applying a coating insulating film on the substrate including the electrode and the dummy member, and forming a protective film.
請求項5に記載の半導体装置において、
前記ダミー部材は絶縁材料によって形成されていることを特徴とする半導体装置。
The semiconductor device according to claim 5,
The semiconductor device, wherein the dummy member is made of an insulating material.
基板上に第1塗布絶縁膜を塗布させた後に硬化させてダミー用膜を形成する第1工程と

前記ダミー用膜をパターニングして基板上の電極形成箇所の近傍にダミー部材を形成す
る第2工程と、
基板上の前記電極形成箇所に電極を形成する第3工程と、
前記電極および前記ダミー部材を含む基板上に第2塗布絶縁膜を塗布させた後に硬化さ
せて保護膜を形成する第4工程と
を備えたことを特徴とする半導体装置の製造方法。
A first step of forming a dummy film by applying a first coating insulating film on the substrate and then curing the first coating insulating film;
A second step of patterning the dummy film to form a dummy member in the vicinity of an electrode formation location on the substrate;
A third step of forming an electrode at the electrode formation location on the substrate;
And a fourth step of forming a protective film by applying a second coating insulating film on the substrate including the electrode and the dummy member, and then forming the protective film.
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008047786A (en) * 2006-08-21 2008-02-28 Fuji Electric Device Technology Co Ltd Insulating film forming method
JP2009512191A (en) * 2005-10-07 2009-03-19 インターナショナル・ビジネス・マシーンズ・コーポレーション Plating seed layer with oxygen / nitrogen transition region for improved barrier properties
JP2014183177A (en) * 2013-03-19 2014-09-29 Seiko Epson Corp Semiconductor device and manufacturing method of the same
JP2015185783A (en) * 2014-03-26 2015-10-22 三菱電機株式会社 Semiconductor device and manufacturing method therefor
CN108993835A (en) * 2018-07-16 2018-12-14 成都捷翼电子科技有限公司 A kind of novel segment difference fill method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009512191A (en) * 2005-10-07 2009-03-19 インターナショナル・ビジネス・マシーンズ・コーポレーション Plating seed layer with oxygen / nitrogen transition region for improved barrier properties
JP2008047786A (en) * 2006-08-21 2008-02-28 Fuji Electric Device Technology Co Ltd Insulating film forming method
JP2014183177A (en) * 2013-03-19 2014-09-29 Seiko Epson Corp Semiconductor device and manufacturing method of the same
JP2015185783A (en) * 2014-03-26 2015-10-22 三菱電機株式会社 Semiconductor device and manufacturing method therefor
CN108993835A (en) * 2018-07-16 2018-12-14 成都捷翼电子科技有限公司 A kind of novel segment difference fill method

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