JP2005191267A - Method of manufacturing cmos semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a CMOS semiconductor device that maximizes saturation drain current, while restraining roll-off in threshold voltage. <P>SOLUTION: When shallow junction regions 29, 30 in the semiconductor substrate 11 are formed on a first region 15 where p-type transistor 12 is formed and on a second region 16 where n-type transistor 13 is formed, respectively, p-type impurities are doped using a gate electrode 21, and lamination of a first sidewall dielectric 23 and a second sidewall dielectric as a mask in the first region 15, while n-type impurities are injected in the second region 16, using a gate electrode 21 and a first sidewall dielectric as a mask. The n-type shallow junction region 30 is disposed nearer to the end of the gate 22 than to the p-type shallow junction region 29, thereby preventing the infiltration of the p-type shallow junction region 29 into a region directly below the gate and restraining the parasitic resistance of the n-type shallow junction region 30, after the shallow junction regions have to be relocated due to diffusion by an activating heat treatment. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method of manufacturing a CMOS semiconductor device having p-type and n-type MOS (Metal Oxide Semiconductor) transistors, and more particularly to a method of manufacturing a CMOS semiconductor device in which an impurity diffusion region is formed with high accuracy.

  Semiconductor devices such as CMOS-LSI satisfy Moore's law and miniaturization of the minimum processing size has been promoted. As miniaturization progresses, the degree of integration and the speed of electrons are expected to increase dramatically, and an ultra-high speed device operation is realized.

  However, various problems arise with miniaturization. For example, when the gate length is shortened, the threshold voltage rolls off, and a short channel effect in which the drain current flows even when the applied voltage is zero occurs.

  Normally, as shown in FIG. 1, impurity ions in the shallow junction region 101 are implanted into the surface of the semiconductor substrate by ion implantation using the gate electrode 102 as a mask, and shallow junction regions 101 a are formed in the semiconductor regions on both sides of the gate 103. . By the heat treatment for activating the impurity ions in the process after the implantation, the impurity ions are thermally diffused to form the shallow junction region 101b up to just below the gate 103. In this case, a short channel effect occurs, and a problem arises that the threshold voltage Vth rolls off. In particular, as the gate length Lg becomes shorter due to miniaturization of the semiconductor device, there is a concern that penetration of a shallow junction region immediately below the gate becomes remarkable.

  Therefore, as a countermeasure, as shown in FIG. 2, when impurity ions are implanted into the shallow junction region 101c, a thin sidewall insulating film 104 is formed on the side wall surface of the gate 103, so that the gate length direction is longer than the gate length Lg. It has been proposed to implant impurity ions in the shallow junction region 101 c into a region separated from the end of the gate 103 using a mask having a large thickness. In this way, even after heat treatment for activation, it is expected that the shallow junction region 101d can be prevented from entering directly under the gate and the short channel effect can be suppressed.

  In Patent Document 1, when forming shallow junction regions, impurity ions are implanted using a gate as a mask, and when forming source / drain regions which are deep junction regions, n-type MOS transistors and p-type MOS transistors are used. It has been proposed to use a sidewall insulating film having a different gate length thickness as a mask. A source / drain region of the n-type MOS transistor is formed with a sidewall insulating film having a large thickness in the gate length direction, the sidewall insulating film is thinned by etching, and the source / drain region of the p-type MOS transistor is formed at the gate end. It is formed closer and then an activation heat treatment.

In Patent Document 2, a stacked body of sidewall insulating films is formed, and impurity ions are implanted using a sidewall insulating film stacked body having a large thickness in the gate length direction as a mask to form source / drain regions. Heat treatment for activating the impurity ions, removing the outer side wall insulating film and implanting impurity ions using the inner side wall insulating film as a mask to form a shallow junction region and activating heat treatment for the shallow junction region at low temperature I do. These processes are performed similarly for the n-type and p-type MOS transistors to suppress the short channel effect.
JP-A-10-223772 Japanese Patent Laid-Open No. 2001-15737

By the way, in the case of a p-type MOS transistor having a gate length of 40 nm, for example, the thickness of the sidewall insulating film in the gate length direction when implanting B ⁺ that is p-type impurity ions is 10 nm in order to suppress the short channel effect. A degree is necessary. However, As ⁺ is used as impurity ions in n-type MOS transistors, and As + has a much lower diffusion coefficient than B +. Even after the heat treatment, there is a problem that the shallow junction region from the gate end portion is too far away, the parasitic resistance is increased, and the current driving capability is lowered.

  In the method disclosed in Patent Document 1, since the sidewall insulating film is simply etched, it is difficult to accurately control the thickness of the sidewall insulating film in the gate length direction. Since the n-type and p-type MOS transistors are formed using the electrode as a mask, it is difficult to suppress the short channel effect.

  In the method disclosed in Patent Document 2, since the shallow junction region is formed by using the same length mask for the n-type MOS transistor and the p-type MOS transistor, diffusion of n-type and p-type impurity ions is performed. There is a problem that a short channel effect is caused by different coefficients.

  Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to provide a method of manufacturing a CMOS semiconductor device that can maximize saturation drain current while suppressing roll-off of a threshold voltage. is there.

  According to one aspect of the present invention, there is provided a method of manufacturing a CMOS semiconductor device including a first region in which a p-type transistor is formed and a second region in which an n-type transistor is formed on a semiconductor substrate, Forming a gate comprising a gate insulating film and a gate electrode on the substrate; forming a sidewall insulating film on the side wall surface of the gate; and first and second gates using the gate electrode and the sidewall insulating film as a mask. Forming first and second shallow junction regions by respectively implanting p-type and n-type impurities into the first region, and in the step of forming the first and second shallow junction regions, The side wall insulating film used as a mask when implanting p is more in the gate length direction than the side wall insulating film used as a mask when implanting p-type impurities. Method of manufacturing a CMOS semiconductor device thickness is characterized by comprising small is provided.

According to the present invention, a p-type impurity and an n-type impurity having a diffusion coefficient in a semiconductor substrate are implanted at different distances from the gate side wall surface to form a shallow junction region. The type impurities are diffused by heat, and the shallow junction region is rearranged. A mask used for implantation is a gate electrode and sidewall insulating films formed on both side wall surfaces thereof, and the position where the shallow junction region is formed is controlled by varying the thickness of the sidewall insulating film.
By making the thickness in the gate length direction of the sidewall insulating film used when implanting the n-type impurity smaller than the thickness in the gate length direction of the sidewall insulating film used when implanting the p-type impurity, n A second shallow junction region made of a p-type impurity is formed closer to the side wall surface of the gate than a first shallow junction region made of a p-type impurity. As a result, when the shallow junction region is rearranged, the first shallow junction region is prevented from excessively intruding directly under the gate, and the second shallow junction region is excessively separated from the gate sidewall surface. Can be prevented. As a result, it is possible to maximize the saturation drain current while suppressing the roll-off of the threshold voltage.

  According to another aspect of the present invention, there is provided a method for manufacturing a CMOS semiconductor device comprising a first region in which a p-type transistor is formed on a semiconductor substrate and a second region in which an n-type transistor is formed. Forming a gate comprising a gate insulating film and a gate electrode on a semiconductor substrate; forming a first sidewall insulating film on a side wall surface of the gate; and a second covering the first sidewall insulating film. And forming a first shallow junction region by implanting p-type impurities using the gate electrode and the first and second sidewall insulation films as a mask in the first region. A step of removing the second sidewall insulating film, and implanting an n-type impurity in the second region using the gate electrode and the first sidewall insulating film as a mask. Method of manufacturing a CMOS semiconductor device characterized by comprising a step of forming a second shallow junction regions Te is provided.

  According to the present invention, the sidewall insulating film used when implanting the n-type impurity is the first sidewall insulating film, and the sidewall insulating film used when implanting the p-type impurity is the first sidewall. By forming a stacked body of the insulating film and the second sidewall insulating film, the second shallow junction region made of n-type impurities is closer to the side wall surface of the gate than the first shallow junction region made of p-type impurities. Form. Therefore, the first and second shallow junction regions can be accurately formed by controlling the thickness of the second sidewall insulating film in the gate length direction.

  According to another aspect of the present invention, there is provided a method for manufacturing a CMOS semiconductor device comprising a first region in which a p-type transistor is formed on a semiconductor substrate and a second region in which an n-type transistor is formed. Forming a gate made of a gate insulating film and a gate electrode on a semiconductor substrate; forming a first sidewall insulating film on a side wall surface of the gate; and in the second region, the gate electrode and the first Forming a second shallow junction region by implanting n-type impurities using the side wall insulating film as a mask, and forming a second side wall insulating film covering the first side wall insulating film; Forming a first shallow junction region by implanting p-type impurities in the first region using the gate electrode and the first and second sidewall insulating films as a mask; Method of manufacturing a CMOS semiconductor device characterized by obtaining is provided.

  According to the present invention, since the first and second shallow junction regions are formed without removing the second sidewall insulating film, the short channel effect (n-type MOS transistor of the n-type MOS transistor) caused by excessive etching at the time of removal is formed. Threshold voltage roll-off) can be avoided, and the number of processes can be reduced.

  According to the present invention, the shallow junction region is rearranged by controlling the position where the shallow junction region is formed by changing the thickness of the sidewall insulating film used as a mask when forming the shallow junction region. In this case, it is possible to prevent the first shallow junction region from excessively penetrating directly under the gate and to prevent the second shallow junction region from being excessively separated from the gate side wall surface. As a result, it is possible to maximize the saturation drain current while suppressing the roll-off of the threshold voltage.

  Embodiments will be described below with reference to the drawings.

(First embodiment)
FIG. 3 is a cross-sectional view of the semiconductor device formed by the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

  Referring to FIG. 3, the semiconductor device 10 includes a p-type MOS transistor 12 and an n-type MOS transistor 13 formed on a semiconductor substrate, for example, a silicon substrate 11, and shallow junction regions 29 of the MOS transistors 12 and 13. , 30 are formed at substantially the same distance from the end of the gate 22. As a result, in the p-type and n-type MOS transistors 12 and 13, it is possible to achieve both suppression of the short channel effect and maximization of the saturation drain current. Hereinafter, a method for manufacturing this semiconductor device will be described in detail.

  4 to 7 are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the first embodiment.

  In the step of FIG. 4A, an element isolation region 14 is formed on the silicon substrate 11 by the STI method. Specifically, a trench 11-1 is formed by trench etching of the silicon substrate 11, the inner wall of the trench 11-1 is thermally oxidized, a silicon oxide film is filled by a CVD method, and then planarized by a CMP method. An isolation region 14 is formed. The silicon substrate 11 may be a bulk substrate or an SOI substrate (Silicon on Insulating substrate). By using an SOI substrate, parasitic capacitance due to a depletion layer generated between a source / drain region formed in a later step and the substrate can be reduced, and the operation speed of the transistor can be improved. The STI method can be formed using a known method.

Further, in the step of FIG. 4A, n-type impurity ions such as As ⁺ and P ⁺ are implanted into the element region 15 where the p-type MOS transistor is formed by ion implantation, and the element region 16 where the p-type MOS transistor is formed. P-type impurity ions such as B ⁺ and BF ₂ ⁺ are implanted to form an n-type well region 18 and a p-type well region 19, respectively.

  Next, in the process of FIG. 4B, a silicon natural oxide film (not shown) on the surface of the silicon substrate 11 is removed by HF treatment, and silicon having a thickness of, for example, 3 nm is obtained by CVD, sputtering, or thermal oxidation. An oxide film (which will be a gate insulating film later) 20a is formed. The thermal oxidation treatment is performed, for example, at a temperature of 600 ° C. to 1100 ° C. for 1 minute to 20 minutes in an oxygen atmosphere. Instead of the silicon oxide film 20a, a silicon oxynitride film or a silicon nitride film may be used, and a laminate of these films and a silicon oxide film may be used.

In the step of FIG. 4B, a non-doped polysilicon film 21a is further formed on the silicon oxide film 20a by the CVD method. For example, by a low pressure CVD method, the pressure in the chamber is heated in the range of 10 Pa to 50 Pa, the substrate temperature is in the range of 600 ° C. to 650 ° C., and the monosilane gas is flowed at a flow rate of 50 sccm to 300 sccm for 5 minutes to 60 minutes. A silicon film 21a (to be a gate electrode later) is formed. A doped polysilicon film doped with P ⁺ or B ⁺ may be formed by mixing PH ₃ gas or the like.

  4C, a resist film (not shown) is formed on the polysilicon film 21a and patterned, and the polysilicon film 21a and the silicon oxide film 20a are etched by RIE using the resist film as a mask. Then, a gate 22 composed of the gate electrode 21 and the gate insulating film 20 is formed. Here, the gate length is set to 40 nm, for example.

  Next, in the step of FIG. 4D, a silicon nitride film 23a having a thickness of, for example, 5 nm is formed by a CVD method so as to cover the structure of FIG. The silicon nitride film 23a is formed, for example, using dichlorosilane gas (flow rate 660 sccm) and ammonia gas (flow rate 870 sccm) at a substrate temperature of 650 ° C. and a pressure of 20 Pa.

In the step of FIG. 5 (A) then etched back by RIE using the silicon nitride film 23a by using the C _x H _y F _z gas, first sidewall insulating film 23 made of silicon nitride film on the sidewall surfaces of the gate 22 Form. The thickness L1 in the gate length direction of the first sidewall insulating film 23 is set to a range of 1 nm to 10 nm (preferably 3 to 5 nm). Here, L1 is set to 5 nm.

Next, in the process of FIG. 5B, a silicon oxide film (not shown) having a thickness of, for example, 5 nm is formed by a CVD method so as to cover the structure of FIG. The silicon oxide film is formed using, for example, silane gas (flow rate 800 sccm) and oxygen gas (flow rate 600 sccm) at a substrate temperature of 850 ° C. and a pressure of 100 Pa. Next, the silicon oxide film is etched back by RIE using a mixed gas of CF ₄ and H ₂ to form a second sidewall insulating film 24 made of a silicon oxide film. The thickness L2 in the gate length direction of the second sidewall insulating film 24 is set to a range of 1 nm to 10 nm (preferably 3 to 5 nm). Here, L2 is set to 5 nm.

5C, the structure of FIG. 5B is covered with a resist film 25, and an opening 25-1 is formed in the element region 15 of the p-type MOS transistor. Next, using the gate electrode 21 and the first and second sidewall insulating films 23 and 24 as a mask, As ⁺ (for example, implantation energy 30 keV, dose amount 1 × 10 ¹³ cm ⁻² ) is applied to the element region 16 of the p-type MOS transistor. For example, implantation is performed at an implantation angle of 35 degrees, and n-type pocket regions 26 are formed in the silicon substrate 11 on both sides of the gate 22.

In the step of FIG. 5C, B ⁺ (for example, implantation energy 1 keV, dose amount 4 × 10 ¹⁴ cm ⁻² ) is formed on the substrate using the gate electrode 21 and the first and second sidewall insulating films 23 and 24 as a mask. A p-type shallow junction region 29 is formed on both sides of the gate 22 by implanting substantially perpendicularly to the surface. Here, the shallow junction region 29 of the p-type MOS transistor is formed on the upper side of the pocket region 26, that is, on the surface side of the silicon substrate 11, and in the region outside the surface of the second sidewall insulating film 24. That is, it is formed in a region outside from the position of about 10 nm from the side wall surface of the gate 22.

  Next, in the step of FIG. 6A, the resist film 25 is removed, and then the second sidewall insulating film 24 is removed by isotropic etching, for example, wet etching.

6B, the structure shown in FIG. 6A is covered with a resist film 31, and an opening 31-1 is formed in the element region 16 of the n-type MOS transistor. Next, using the gate electrode 21 and the first sidewall insulating film 23 as a mask, B ⁺ (for example, implantation energy of 10 keV, dose amount of 1 × 10 ¹³ cm ⁻² ) is set at an incident angle of 35 degrees, for example, and implanted. P-type pocket regions 28 are formed in the silicon substrates 11 on both sides.

6B, As ⁺ (injection energy 1 keV) is implanted almost perpendicularly to the substrate surface using the gate electrode 21 and the first sidewall insulating film 23 as a mask, and shallow junction regions 30 are formed on both sides of the gate. Form. Here, the shallow junction region 30 is formed on the upper side of the pocket region, that is, on the silicon substrate surface side, and is formed on the outer side from the surface of the first sidewall insulating film 23. That is, it is formed in a region outside from the position of, for example, about 5 nm from the side wall surface of the gate 22.

6C, the resist film 31 is removed, and a silicon nitride film (not shown) that covers the surface of the structure is formed to a thickness of, for example, 50 nm. The formation method is the same as the method described in FIG. Next, the silicon nitride film is etched back by RIE using C _x H _y F _z gas to form a third sidewall insulating film 32 made of a silicon nitride film. The gate length direction thickness L3 of the third sidewall insulating film 32 is set in a range of 10 nm to 100 nm (preferably 30 to 50 nm), and is set to 50 nm here.

7A, the structure surface of FIG. 6C is covered with a resist film 33, and the element region 15 of the p-type MOS transistor is opened. Next, using the gate electrode 21 and the first and third sidewall insulating films 23 and 32 as a mask, B ⁺ (for example, implantation energy 5 keV, dose amount 2 × 10 ¹⁵ cm ⁻² ) is implanted substantially perpendicularly to the substrate surface. A source / drain region 34 which is a deep junction region is formed in the device region 15 on both sides of the substrate 22. The source / drain region 34 is formed in a region outside the surface of the third sidewall insulating film 32.

7B, the resist film 33 is removed, and then the surface of the structure is covered with the resist film 36, and an opening 36-1 is formed in the element region 16 of the n-type MOS transistor. Next, using the gate electrode 21 and the first and third sidewall insulating films 23 and 32 as a mask, P ⁺ (for example, implantation energy 6 keV, dose amount 2 × 10 ¹⁵ cm ⁻² ) is implanted almost perpendicularly to the substrate surface. Source / drain regions 35 which are deep junction regions are formed in the device regions 16 on both sides of the substrate 22. Here, the source / drain region 35 is formed in a region outside the surface of the third sidewall insulating film 32.

Next, in the process of FIG. 7C, the structure is heated to, for example, 800 ° C. with an RTP apparatus or the like, and activation heat treatment of impurity ions in the source / drain regions 34 and 35, the shallow junction region 2, and the pocket region is performed. Since the diffusion coefficient of B ⁺ in the silicon substrate is larger than As ⁺ , the p-type shallow junction region 29 is larger than the n-type shallow junction region 30, and the p-type and n near the lower side of the gate 22 are expanded. The distribution of the shallow junction regions 29 and 30 is almost the same as that of the n-type MOS transistor 13. For example, since the shallow junction region 29 of the p-type MOS transistor 12 is implanted away from the side wall surface of the gate 22 as compared with the n-type MOS transistor, the occurrence of the short channel effect is suppressed even if it is diffused by the activation heat treatment. can do. In the temperature range where the activation heat treatment is performed (for example, 400 ° C. to 1000 ° C.), the diffusion coefficient of impurity ions in the silicon substrate has a relationship of B ⁺ > BF ₂ ⁺ > Sb ⁺ > As ⁺ . . As impurity ions in the shallow junction regions 29 and 30, BF ₂ ⁺ may be used instead of B ⁺ , and Sb ⁺ may be used instead of As ⁺ .

In the step of FIG. 7C, the resist film 36 is further removed, a Ti film or a Co film (not shown) is formed on the surface of the structure by sputtering, and heat treatment is performed to form the substrate surface and the gate electrode surface. Silicide is performed to form a silicide film such as a TiSi ₂ film or a CoSi ₂ film. Next, the Ti film and Co film that have not been silicided are removed. Although the illustration and detailed description of the subsequent steps are omitted, the structure shown in FIG. 7C is covered with an interlayer insulating film, and a wiring layer is formed on the interlayer insulating film. The wiring layer and the p-type and n-type MOS transistors are electrically connected by contacts in contact with the source / drain regions, and a multilayer interlayer insulating film, a wiring layer, and the like are formed to complete the semiconductor device.

  According to the present embodiment, the first sidewall insulating film alone or the stacked body of the first and second sidewall insulating films, in addition to the gate electrode, is used as a mask when impurity ions are implanted. Since the shallow junction regions 30 and 29 of the type are selectively used, the n-type shallow junction region 30 is closer to the gate side wall surface than the p-type shallow junction region 29 depending on the thickness in the gate length direction. Can be placed well. As a result, the distribution of the rearranged shallow junction regions 29 and 30 after the activation heat treatment is such that the distance between the gate side wall surface and the gate side end of the shallow junction region is almost the same in the n-type MOS transistor 13 and the p-type MOS transistor 12. Since they are arranged in the same manner, the short channel effect can be prevented and the parasitic resistance of the n-type MOS transistor 13 can be suppressed. Therefore, it is possible to maximize the saturation drain current while suppressing the threshold voltage roll-off.

  As an example of this embodiment, a CMOS semiconductor device having a gate length of 40 nm was manufactured by the manufacturing method of this embodiment. The threshold voltage of this CMOS semiconductor device was +0.1 V for the n-type MOS transistor and −0.1 V for the p-type MOS transistor. In addition, when the drain voltage is 1 V (n-type MOS transistor) and -1 V (p-type MOS transistor), the saturation drain current per 1 μm gate width is 1 mA for the n-type MOS transistor and 450 μA for the p-type MOS transistor. It was. This shows that even when the gate length is shortened to 40 nm, a semiconductor device capable of suppressing the roll-off of the threshold voltage and obtaining a large saturation drain current can be realized.

In the above embodiment, BF ₂ ⁺ may be used instead of B ⁺ . Sb ⁺ may be used instead of As ⁺ .

  In the step of FIG. 5C, the shallow junction region 29 may be formed before the pocket region 26 is formed. The same applies to the process of FIG.

  In the manufacturing method of the semiconductor device of this embodiment, the deep junction region is formed after the shallow junction region. However, the deep junction region may be formed before the shallow junction region is formed. For example, after the step of FIG. 4C, a fourth sidewall insulating film having a gate length direction thickness comparable to the gate length direction thickness of the stacked body of the first sidewall insulating film and the third sidewall insulating film. Is formed on the gate side wall surface, a deep junction region is formed in the same manner as in the steps of FIGS. 7A and 7B, and then an activation heat treatment is performed, and the fourth side wall insulating film is further removed. Next, the process is performed in the same manner as in the steps of FIGS. 4D to 6C, and then an active heat treatment is performed on the shallow junction region. According to this method, since the activation heat treatment of the high-temperature deep junction region is performed before forming the shallow junction region, the activation heat treatment of the shallow junction region can be performed at a lower temperature, and the shallow junction region is regenerated by diffusion. Arrangement can be performed with good control. This effect is further increased as the gate length is reduced.

  Hereinafter, a method for manufacturing a semiconductor device according to a modification of the first embodiment will be described. In this modification, the shallow junction region is formed in the same manner as in the first embodiment except that the n-type MOS transistor is formed first and the p-type MOS transistor is formed later.

  8 to 9 are cross-sectional views showing the manufacturing steps of the semiconductor device according to the modification of the first embodiment. In the figure, portions corresponding to the portions described above are denoted by the same reference numerals, and description thereof is omitted.

  In the process of FIG. 8A, silicon oxide is formed on the element regions 15 and 16 of the p-type MOS transistor and the n-type transistor on the silicon substrate 11 in the same manner as in the processes of FIG. 4A to FIG. A gate 22 comprising a gate insulating film 20 of a film and a gate electrode 21 of a polysilicon film is formed.

8B, the structure surface of FIG. 8A is covered with a resist film 41, and an opening 41-1 is formed in the region of the n-type MOS transistor. Next, using the gate electrode 21 and the first sidewall insulating film 23 as a mask, B ⁺ is implanted obliquely into the substrate surface in the same manner as in the step of FIG. 6B, and then As ⁺ is implanted perpendicularly to the substrate surface. A p-type pocket region 28 and an n-type shallow junction region 30 are formed in the element region 16 outside the first sidewall insulating film 23.

  Next, in the step of FIG. 8C, the resist film 41 is removed, and a silicon oxide film is formed by the CVD method and etched back in the same manner as in the step of FIG. 5B so as to cover the surface of the structure. A second sidewall insulating film 24 having a gate length direction thickness L2 is then formed.

Next, in the process of FIG. 9, as in the process of FIG. 5C, the structure surface of FIG. 8C is covered with a resist film 42, and an opening 42-1 is formed in the element region 15 of the p-type MOS transistor. Then, using the gate electrode 21 and the first and second sidewall insulating films 23 and 24 as a mask, As ⁺ is implanted from an oblique direction, and B ⁺ is implanted substantially perpendicularly to the substrate surface. A p-type shallow junction region 29 is formed. Next, although not shown, the resist film 42 is removed, and the second sidewall insulating film 24 is removed by isotropic etching such as wet etching. Further, similarly to the first embodiment, the steps of FIGS. 6C to 7C are performed.

  According to this modification, a p-type shallow junction region is first formed using the gate electrode and the first sidewall insulating film as a mask, and then the second sidewall insulation covering the first sidewall insulating film is formed. Since the n-type shallow junction region is formed using the film as a mask, both shallow junction regions are formed without going through the etching process of the second sidewall insulating film in the first embodiment. Therefore, it is possible to avoid problems when etching becomes excessive, and it is possible to simplify and facilitate the manufacturing method by reducing the number of processes.

  In this modification, when the second sidewall insulating film has the same thickness in the gate length direction of the third wall insulating film (L2 = L3), the source / drain regions are not removed without removing the second sidewall insulating film. It may be formed. The number of steps can be further reduced and simplified as compared with the manufacturing method according to the first embodiment.

(Second Embodiment)
The semiconductor device manufacturing method according to the second embodiment of the present invention is mainly characterized in that the side wall surface of the gate electrode is oxidized to provide the first side wall insulating film of the silicon oxide film.

  10A to 10D are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the second embodiment.

  In the step of FIG. 10A, as in FIGS. 4A and 4B, the element isolation region 14 is formed in the semiconductor substrate 11, and the silicon oxide film 20a serving as the gate insulating film and the polysilicon serving as the gate electrode are formed. A silicon film 21a is formed.

  In the step of FIG. 10A, a silicon oxide film 51a (thickness: 200 nm) is further formed on the polysilicon film 21a by CVD or sputtering.

  10B, a resist film (not shown) is formed and patterned on the silicon oxide film 51a, and the silicon oxide film 51a and the polysilicon film 21a are sequentially etched by RIE using the resist film as a mask. Then, a stacked body 52 of a gate electrode 21 made of a polysilicon film and a tip mask 51 made of a silicon oxide film is formed on the silicon oxide film 20a. At this time, the thickness L4 of the stacked body 52 in the gate length direction is set longer than the final gate length. That is, gate length direction thickness L4 = gate length + gate length direction thickness L1 × 2 of the first sidewall insulating film.

  Next, in the process of FIG. 10C, the sidewall surface of the polysilicon film 21 is thermally oxidized by heating for 5 seconds to 10 seconds in the temperature range of 800 ° C. to 900 ° C. using an RTP apparatus. A first sidewall insulating film 53 having a gate length direction thickness L1 set to 1 nm to 10 nm (preferably 3 nm to 5 nm) is formed. Next, the silicon oxide film 20a on the semiconductor substrate 11 except for the tip mask 51 on the gate and the structure 52 directly below is removed by anisotropic etching to form the structure shown in FIG. Next, the steps of FIGS. 5B to 7C of the first embodiment are substantially the same as in the present embodiment except that the second sidewall insulating film is formed of a silicon nitride film. A semiconductor device is formed.

  According to the present embodiment, since the first sidewall insulating film 53 is formed by oxidizing the sidewall surface of the polysilicon film, the film thickness can be controlled reliably and easily, so that the shallow junction region is formed. The length of the mask in the gate length direction can be controlled well, and a shallow junction region can be formed with high accuracy.

In the above description, the n-type MOS transistor and the p-type MOS transistor are replaced, and n-type impurity ions (As ⁺ or As ⁺ or Sb ⁺ ) is used to form a shallow junction of the n-type MOS transistor, and p-type impurity ions (B ⁺ or BF ₂ ⁺ ) are used as a mask using the thin sidewall insulating film, for example, the first sidewall insulating film as a mask. A shallow junction of the type MOS transistor may be formed.

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the present invention described in the claims. It can be changed. For example, the semiconductor device of the present invention may be a combination of the modification of the first embodiment and the second embodiment.

In addition, the following additional remarks are disclosed regarding description of the above embodiment.
(Supplementary Note 1) A method of manufacturing a CMOS semiconductor device including a first region in which a p-type transistor is formed and a second region in which an n-type transistor is formed on a semiconductor substrate,
Forming a gate comprising a gate insulating film and a gate electrode on the semiconductor substrate;
Forming a sidewall insulating film on the sidewall surface of the gate;
Forming p-type and n-type impurities in the first and second regions using the gate electrode and the sidewall insulating film as a mask to form first and second shallow junction regions, respectively.
In the step of forming the first and second shallow junction regions, the sidewall insulating film used as a mask when implanting n-type impurities is used as the sidewall insulating film used as a mask when implanting p-type impurities. A method of manufacturing a CMOS semiconductor device, wherein the thickness in the gate length direction is smaller than that of the CMOS semiconductor device.
(Supplementary Note 2) A method of manufacturing a CMOS semiconductor device including a first region in which a p-type transistor is formed and a second region in which an n-type transistor is formed on a semiconductor substrate,
Forming a gate comprising a gate insulating film and a gate electrode on the semiconductor substrate;
Forming a first sidewall insulating film on the side wall surface of the gate;
Forming a second sidewall insulating film covering the first sidewall insulating film;
In the first region, forming a first shallow junction region by implanting p-type impurities using the gate electrode and the first and second sidewall insulating films as a mask;
Removing the second sidewall insulating film;
And a step of forming a second shallow junction region by implanting an n-type impurity using the gate electrode and the first sidewall insulating film as a mask in the second region. Method.
(Supplementary Note 3) After the step of forming the second shallow junction region,
Forming a third sidewall insulating film covering the first sidewall insulating film;
Forming deep junction regions by implanting p-type impurities in the first region and n-type impurities in the second region using the gate electrode and the first and third sidewall insulating films as a mask; The method for manufacturing a CMOS semiconductor device according to appendix 2, wherein:
(Supplementary Note 4) A method of manufacturing a CMOS semiconductor device including a first region in which a p-type transistor is formed and a second region in which an n-type transistor is formed on a semiconductor substrate,
Forming a gate comprising a gate insulating film and a gate electrode on the semiconductor substrate;
Forming a first sidewall insulating film on the side wall surface of the gate;
Forming a second shallow junction region by implanting an n-type impurity using the gate electrode and the first sidewall insulating film as a mask in the second region;
Forming a second sidewall insulating film covering the first sidewall insulating film;
And a step of forming a first shallow junction region by implanting a p-type impurity using the gate electrode and the first and second sidewall insulating films as a mask in the first region. Device manufacturing method.
(Supplementary Note 5) After the step of forming the first shallow junction region,
Removing the second sidewall insulating film;
Forming a third sidewall insulating film covering the first sidewall insulating film;
Forming a deep junction region by implanting p-type impurities in the first region and n-type impurities in the second region, using the gate electrode and the first and third sidewall insulating films as a mask. A method for manufacturing a CMOS semiconductor device according to appendix 4, wherein the method is provided.
(Appendix 6) Between the step of forming the gate and the step of forming the first sidewall insulating film,
Forming a fourth sidewall insulating film on the side wall surface of the gate;
Forming a deep junction region by implanting p-type impurities in the first region and n-type impurities in the second region using the gate electrode and the fourth sidewall insulating film as a mask;
Removing the fourth sidewall insulating film,
The fourth sidewall insulating film has a thickness in the gate length direction that is approximately the same as or larger than that of the stacked first sidewall insulating film and second sidewall insulating film. A method for manufacturing a CMOS semiconductor device according to appendix 2 or 4.
(Supplementary Note 7) In the step of forming the gate, a gate having a length larger than the final gate length is formed,
In the step of forming the first sidewall insulating film, the side wall surface of the gate electrode is oxidized to be modified into a silicon oxide film to form a first sidewall insulating film. The manufacturing method of the CMOS semiconductor device as described in any one of them.
(Supplementary Note 8) A step of activating p-type and n-type impurities in the first and second shallow junction regions by heating to a predetermined temperature,
8. The CMOS semiconductor device according to any one of appendices 1 to 7, wherein the p-type impurity has a diffusion coefficient in the semiconductor substrate larger than that of the n-type impurity at the predetermined temperature. Production method.
(Supplementary Note 9) The method for manufacturing a CMOS semiconductor device according to any one of Supplementary notes 2 to 8, wherein the first sidewall insulating film and the second sidewall insulating film are made of different materials.
(Supplementary Note 10) The p-type impurity is at least one impurity ion of B ⁺ and BF ₂ ⁺ , and the n-type impurity is at least one impurity ion of As ⁺ and Sb ^+. The manufacturing method of a CMOS semiconductor device according to any one of Supplementary notes 1 to 9.

It is a figure for demonstrating the problem (the 1) of the conventional semiconductor device. It is a figure for demonstrating the problem (the 2) of the conventional semiconductor device. It is sectional drawing of the semiconductor device formed by the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. (A)-(D) are sectional drawings which show the manufacturing process (the 1) of the semiconductor device which concerns on 1st Embodiment. (A)-(C) are sectional drawings which show the manufacturing process (the 2) of the semiconductor device which concerns on 1st Embodiment. (A)-(C) are sectional drawings which show the manufacturing process (the 3) of the semiconductor device which concerns on 1st Embodiment. (A)-(C) are sectional drawings which show the manufacturing process (the 4) of the semiconductor device which concerns on 1st Embodiment. (A)-(C) are sectional drawings which show the manufacturing process (the 1) of the semiconductor device which concerns on the modification of 1st Embodiment. It is sectional drawing which shows the manufacturing process (the 2) of the semiconductor device which concerns on the modification of 1st Embodiment. (A)-(D) are sectional drawings which show the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Silicon substrate 12 p-type MOS transistor 13 n-type MOS transistor 15 Element region for forming p-type MOS transistor 16 Element region for forming n-type MOS transistor 18 n-type well region 19 p-type well region 20 Gate insulating film 20a Silicon oxide film 21 Gate electrode 21a Polysilicon film 22 Gate 23, 53 First sidewall insulating film 23a Silicon nitride film 24 Second sidewall insulating film 26 n-type pocket region 28 p-type pocket region 29, 30 Shallow junction region 32 Third sidewall insulating film 34, 35 Source / drain regions 38a, 38b Silicide film

Claims (5)

A method for manufacturing a CMOS semiconductor device comprising a first region in which a p-type transistor is formed on a semiconductor substrate and a second region in which an n-type transistor is formed,
Forming a gate comprising a gate insulating film and a gate electrode on the semiconductor substrate;
Forming a sidewall insulating film on the sidewall surface of the gate;
Forming p-type and n-type impurities in the first and second regions using the gate electrode and the sidewall insulating film as a mask to form first and second shallow junction regions, respectively.
In the step of forming the first and second shallow junction regions, the sidewall insulating film used as a mask when implanting n-type impurities is used as the sidewall insulating film used as a mask when implanting p-type impurities. A method of manufacturing a CMOS semiconductor device, wherein the thickness in the gate length direction is smaller than that of the CMOS semiconductor device. A method for manufacturing a CMOS semiconductor device comprising a first region in which a p-type transistor is formed on a semiconductor substrate and a second region in which an n-type transistor is formed,
Forming a gate comprising a gate insulating film and a gate electrode on the semiconductor substrate;
Forming a first sidewall insulating film on the side wall surface of the gate;
Forming a second sidewall insulating film covering the first sidewall insulating film;
In the first region, forming a first shallow junction region by implanting p-type impurities using the gate electrode and the first and second sidewall insulating films as a mask;
Removing the second sidewall insulating film;
And a step of forming a second shallow junction region by implanting an n-type impurity using the gate electrode and the first sidewall insulating film as a mask in the second region. Method. A method for manufacturing a CMOS semiconductor device comprising a first region in which a p-type transistor is formed on a semiconductor substrate and a second region in which an n-type transistor is formed,
Forming a gate comprising a gate insulating film and a gate electrode on the semiconductor substrate;
Forming a first sidewall insulating film on the side wall surface of the gate;
Forming a second shallow junction region by implanting an n-type impurity using the gate electrode and the first sidewall insulating film as a mask in the second region;
Forming a second sidewall insulating film covering the first sidewall insulating film;
And a step of forming a first shallow junction region by implanting a p-type impurity using the gate electrode and the first and second sidewall insulating films as a mask in the first region. Device manufacturing method. In the step of forming the gate, forming a gate having a length larger than the final gate length,
4. The step of forming the first sidewall insulating film includes oxidizing the sidewall surface of the gate electrode to form a silicon oxide film to form a first sidewall insulating film. A manufacturing method of the described CMOS semiconductor device. 5. The method of manufacturing a CMOS semiconductor device according to claim 2, wherein the first sidewall insulating film and the second sidewall insulating film are made of different materials. 6.

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