CN105575876A - Formation method of semiconductor structure - Google Patents
Formation method of semiconductor structure Download PDFInfo
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- CN105575876A CN105575876A CN201410549363.0A CN201410549363A CN105575876A CN 105575876 A CN105575876 A CN 105575876A CN 201410549363 A CN201410549363 A CN 201410549363A CN 105575876 A CN105575876 A CN 105575876A
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Abstract
A formation method of a semiconductor structure is disclosed. The method comprises the following steps of providing a semiconductor substrate including a first area and a second area, forming a first gate structure on the first area and forming a second gate structure on the second area; forming a first side wall on sidewall surfaces of the first gate structure and the second gate structure and forming a second side wall on a first side wall surface; injecting P-type impurity ions into the semiconductor substrate of two sides of the first gate structure and the second side wall to form a shallow doping source/leakage area of a PMOS; removing the second side wall; injecting N-type impurity ions into the semiconductor substrate of two sides of the second gate structure and the first side wall to form a shallow doping source/leakage area of an NMOS, wherein mass of the N-type impurity ions is greater than mass of the P-type impurity ions; and carrying out annealing process. During PMOS shallow doping source/leakage area injection, because of a large side wall width, a short channel effect of a PMOS transistor formed by an integration technology is reduced.
Description
Technical field
The present invention relates to field of semiconductor fabrication, particularly a kind of formation method of semiconductor structure.
Background technology
Metal-oxide-semicondutor (MOS) transistor is the most basic device in semiconductor manufacturing, and it is widely used in various integrated circuit, and the doping type according to principal carrier and when manufacturing is different, is divided into nmos pass transistor and PMOS transistor.
Prior art provides a kind of manufacture method of MOS transistor.Fig. 1 to Fig. 5 is the nmos pass transistor of prior art and the cross-sectional view of the integrated manufacturing process of PMOS transistor.
Please refer to Fig. 1, provide Semiconductor substrate 100, described Semiconductor substrate 100 comprises first area 11 and second area 12; The Semiconductor substrate 100 of described first area 11 forms first grid structure 103, the Semiconductor substrate 100 of second area 12 forms second grid structure 104.
Described first grid structure 103 is as the grid of PMOS transistor, and described second grid structure 104 is as the grid of nmos pass transistor.
Fleet plough groove isolation structure 101 can be formed in the Semiconductor substrate 100 of described first area 11 and second area 12.
Please refer to Fig. 2, the sidewall surfaces of described first grid structure 103 and second grid structure 104 both sides forms side wall 105.
The formation process of described side wall 105 is: form the spacer material layer covering described Semiconductor substrate 100, first grid structure 103 and second grid structure 104 surface; Without spacer material layer described in mask etching, the sidewall surfaces of first grid structure 103 and second grid structure 104 both sides forms side wall 105.
Described side wall 105 can be individual layer or double stacked structure.
Please refer to Fig. 3, form the first mask layer 106 of Semiconductor substrate 100, second grid structure 104 and the side wall 105 covering described second area 12; Carry out the first ion implantation technology, implanting p-type foreign ion in the Semiconductor substrate 100 of the first area 11 in first grid structure 103 and side wall 105 both sides, forms the shallow doped source/drain regions 107 of PMOS transistor in the Semiconductor substrate 100 of the first area 11 of first grid structure 103 and side wall 105 both sides.
Please refer to Fig. 4, remove described first mask layer 106 (with reference to figure 3), form the second mask layer 108 of Semiconductor substrate 100, first grid structure 103 and the side wall 105 covering first area 11; Carry out the second ion implantation, N-type impurity ion is injected, the shallow doped source/drain regions 109 of formation nmos pass transistor in the Semiconductor substrate 100 of the second area 12 of second grid structure 104 and side wall 105 both sides in the Semiconductor substrate 100 of the second area 12 of second grid structure 104 and side wall 105 both sides.
Please refer to Fig. 5, carry out annealing process, activate foreign ion in the shallow doped source/drain regions 107 of PMOS transistor and the shallow doped source/drain regions 109 of nmos pass transistor.
But the PMOS transistor adopting existing nmos pass transistor and PMOS transistor integration making technology to be formed more easily produces the problem of short channel relative to nmos pass transistor.
Summary of the invention
The problem that the present invention solves is how in nmos pass transistor and PMOS transistor integration making technology, weakens the short-channel effect of the PMOS transistor of formation.
For solving the problem, the invention provides a kind of formation method of semiconductor structure, comprising: provide Semiconductor substrate, described Semiconductor substrate comprises first area and second area; The Semiconductor substrate of described first area is formed first grid structure, the Semiconductor substrate of second area is formed second grid structure; Form the first side wall on the surface in described first grid structure and second grid structure side wall, form the second side wall on the first side wall surface; With described first side wall, the second side wall and first grid structure for mask, implanting p-type foreign ion in the Semiconductor substrate of the first area of first grid structure and the second side wall both sides, forms the shallow doped source/drain regions of PMOS transistor; Remove described second side wall; With described first side wall and second grid structure for mask, N-type impurity ion is injected in the Semiconductor substrate of the second area of second grid structure and the first side wall both sides, form the shallow doped source/drain regions of nmos pass transistor, the quality of described N-type impurity ion is greater than the quality of p type impurity ion; Carry out annealing process, activate PMOS transistor shallow doped source/drain regions in p type impurity ion and nmos pass transistor shallow doped source/drain regions in N-type impurity ion.
Optionally, the forming process of described first side wall and the second side wall is: form the first spacer material layer covering described Semiconductor substrate, first grid structure and second grid structure; Without the first spacer material layer described in mask etching, the sidewall surfaces of first grid structure and second grid structure forms the first side wall; Form the second spacer material layer covering described Semiconductor substrate, first grid structure, second grid structure and the first side wall surface; Without mask etching second spacer material layer, form the second side wall on the first side wall surface.
Optionally, the forming process of described first side wall and the second side wall is: form the first spacer material layer and the second spacer material layer that cover described Semiconductor substrate, first grid structure and second grid structure; Without the first spacer material layer described in mask etching and the second spacer material layer, the sidewall surfaces of first grid structure and second grid structure forms the first side wall, form the second side wall on the first side wall surface.
Optionally, after described second side wall of removal, the first side wall of the part that contacts with the bottom of the second side wall of etching removal first side wall.
Optionally, the material of described first side wall is not identical with the material of the second side wall.
Optionally, the material of described first side wall is low-K dielectric material, and low-K dielectric material is SiCON, SiCOH, FSG or BSG, and the material of described second side wall is SiN or SiC.
Optionally, remove described second side wall and adopt wet-etching technology.
Optionally, when described second spacer material is SiN, the solution that described wet-etching technology adopts is concentrated phosphoric acid.
Optionally, the mass concentration of described concentrated phosphoric acid is 70-90%, and temperature is 120-170 degree Celsius.
Optionally, the width of described first side wall is greater than the width of the second side wall.
Optionally, the width of described first side wall is 40 ~ 70 dusts, and the width of the second side wall is 20 ~ 40 dusts.
Optionally, described p type impurity ion is boron ion, boron fluoride ion, gallium ion or indium ion.
Optionally, described N-type impurity ion is phosphonium ion, arsenic ion or antimony ion.
Optionally, described p type impurity ion is boron ion or boron fluoride ion, and described N-type impurity ion is phosphonium ion or arsenic ion.
Optionally, the energy injecting N-type impurity ion is 1-5kev, and dosage is 1E14-5E15atom/cm
2.The energy of implanting p-type foreign ion is 1-5kev, and dosage is 1E14-5E15atom/cm
2.
Optionally, described annealing process comprises spike annealing and laser annealing.
Optionally, behind the shallow doped source drain region forming nmos pass transistor, also comprise: on the first side wall, form the 3rd side wall; With described 3rd side wall and first grid structure for mask, implanting p-type foreign ion in the Semiconductor substrate of the first area of first grid structure and the 3rd side wall both sides, form the dark doped source/drain regions of PMOS transistor, the degree of depth of the dark doped source/drain regions of PMOS transistor is greater than the degree of depth of the shallow doped source/drain regions of PMOS transistor; With described 3rd side wall and second grid structure for mask, N-type impurity ion is injected in the Semiconductor substrate of the second area of second grid structure and the 3rd side wall both sides, form the dark doped source/drain regions of nmos pass transistor, the degree of depth of the dark doped source/drain regions of nmos pass transistor is greater than the degree of depth of the shallow doped source/drain regions of nmos pass transistor.
Optionally, in the Semiconductor substrate of the first area of first grid structure both sides before implanting p-type foreign ion, also comprise: the first mask layer forming Semiconductor substrate, second grid structure and the second side wall covering described second area.
Optionally, before removal second side wall, remove described first mask layer.
Optionally, inject N-type impurity ion in the Semiconductor substrate of the second area of second grid structure both sides before, also comprise: the second mask layer forming Semiconductor substrate, first grid structure and the first side wall covering described first area; After injecting N-type impurity ion, remove described second mask layer.
Compared with prior art, technical scheme of the present invention has the following advantages:
The first side wall is formed on the surface in described first grid structure and second grid structure side wall, after the first side wall surface forms the second side wall, with described first side wall, the second side wall and first grid structure for mask, implanting p-type foreign ion in the Semiconductor substrate of the first area of first grid structure both sides, forms the shallow doped source/drain regions of PMOS transistor; Then, described second side wall is removed; With described first side wall and second grid structure for mask, N-type impurity ion is injected in the Semiconductor substrate of the second area of second grid structure both sides, form the shallow doped source/drain regions of nmos pass transistor, the quality of described N-type impurity ion is greater than the quality of p type impurity ion; Then, annealing process, activate PMOS transistor shallow doped source/drain regions in p type impurity ion and nmos pass transistor shallow doped source/drain regions in N-type impurity ion.In the present invention, when the first side wall and the second side wall exist simultaneously, only p type impurity ion implantation is carried out to the Semiconductor substrate of first area, in first grid structure, the shallow doped source/drain regions of PMOS transistor is formed in the Semiconductor substrate of the first area of the first side wall and the second side wall both sides, after removal second side wall, only N-type impurity ion implantation is carried out to the Semiconductor substrate of second area, the shallow doped source/drain regions of nmos pass transistor is formed in the Semiconductor substrate of second grid structure and the first side wall both sides, thus make the shallow doped source/drain regions of PMOS transistor and the first distance of first grid structure side wall be greater than the shallow doped source/drain regions of nmos pass transistor and the second distance of second grid structure side wall, and the quality of the N-type impurity ion injected in the present invention is greater than the quality of p type impurity ion, by injecting the different of the distance of the shallow doped source/drain regions of PMOS transistor and the shallow doped source/drain regions of nmos pass transistor and corresponding first grid structure side wall and the second grid structure side wall formed, with the difference of the shallow doped source/drain regions foreign ion diffusion rate of the shallow doped source/drain regions and nmos pass transistor that compensate PMOS transistor, thus it is suitable relative to the complexity of nmos pass transistor generation short-channel effect to make nmos pass transistor and PMOS transistor integration making technology form PMOS transistor.
Further, the width of described first side wall is 40 ~ 70 dusts, the width of the second side wall is 20 ~ 40 dusts, the shallow doped source/drain regions of the PMOS transistor formed after ion implantation and the sidewall of first grid structure have the first distance, described first distance is 60 ~ 110 dusts, the shallow doped source/drain regions of the nmos pass transistor formed after ion implantation and the sidewall of second grid structure have second distance, described second distance is 40 ~ 70 dusts, when annealing, the different compensation effects of the shallow doped source/drain regions of pair pmos transistor and the shallow doped source/drain regions foreign ion diffusion rate of nmos pass transistor are better.
Accompanying drawing explanation
Fig. 1 to Fig. 5 is the nmos pass transistor of prior art and the cross-sectional view of the integrated manufacturing process of PMOS transistor;
Fig. 6 ~ Figure 12 is the cross-sectional view of the forming process of embodiment of the present invention semiconductor structure.
Embodiment
As background technology sayed, the PMOS transistor adopting the nmos pass transistor of prior art and PMOS transistor integration making technology to be formed more easily produces the problem of short channel relative to nmos pass transistor.
Pair nmos transistor and PMOS transistor integration making technology carry out studying rear discovery: in the nmos pass transistor of prior art and the integration making technology of PMOS transistor, side wall on first grid structure and second grid structure both sides sidewall is that same processing step is formed, the width of the side wall that first grid structure side wall is formed is made to be identical with the width of the sidewall that second grid structure side wall is formed, the shallow doped source/drain regions of the PMOS transistor thus formed after the first ion implantation is to the shallow doped source/drain regions of the nmos pass transistor formed after the first distance of first grid structure side wall equals the second ion implantation to the second distance of second grid structure side wall, and the foreign ion that the first ion implantation is injected is p type impurity ion, be generally boron ion or boron fluoride ion, the foreign ion that second ion implantation is injected is N-type impurity ion, be generally phosphonium ion or arsenic ion, the quality of the p type impurity ion namely injected is less than the quality of the N-type impurity ion of injection, when annealing, the diffusion rate of the p type impurity ion of the shallow doped source/drain regions doping of PMOS transistor can be greater than the diffusion rate of the N-type impurity ion of the shallow doped source/drain regions doping of nmos pass transistor, after making annealing, overlapping width bottom the shallow doped source/drain regions 109 that shallow doped source/drain regions 107 and the overlapping width bottom first grid structure 103 of (specifically please refer to Fig. 5) PMOS transistor can be greater than nmos pass transistor and second grid structure 104, thus, make to form PMOS transistor by nmos pass transistor and PMOS transistor integration making technology and more easily produce short-channel effect relative to nmos pass transistor.
For this reason, the invention provides a kind of formation method of semiconductor structure, first grid structure and second grid structure side wall are formed the first side wall and the second side wall, when the first side wall and the second side wall exist simultaneously, only p type impurity ion implantation is carried out to the Semiconductor substrate of first area, in first grid structure, the shallow doped source/drain regions of PMOS transistor is formed in the Semiconductor substrate of the first area of the first side wall and the second side wall both sides, after removal second side wall, only N-type impurity ion implantation is carried out to the Semiconductor substrate of second area, the shallow doped source/drain regions of nmos pass transistor is formed in the Semiconductor substrate of second grid structure and the first side wall both sides, thus make the shallow doped source/drain regions of PMOS transistor and the first distance of first grid structure side wall be greater than the shallow doped source/drain regions of nmos pass transistor and the second distance of second grid structure side wall, and the quality of the N-type impurity ion injected in the present invention is greater than the quality of p type impurity ion, by injecting the different of the distance of the shallow doped source/drain regions of PMOS transistor and the shallow doped source/drain regions of nmos pass transistor and corresponding first grid structure side wall and the second grid structure side wall formed, with the difference of the shallow doped source/drain regions foreign ion diffusion rate of the shallow doped source/drain regions and nmos pass transistor that compensate PMOS transistor, thus it is suitable relative to the complexity of nmos pass transistor generation short-channel effect to make nmos pass transistor and PMOS transistor integration making technology form PMOS transistor.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.When describing the embodiment of the present invention in detail, for ease of illustrating, schematic diagram can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, and it should not limit the scope of the invention at this.In addition, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
Fig. 6 ~ Figure 12 is the cross-sectional view of the forming process of embodiment of the present invention semiconductor structure.
With reference to figure 6, provide Semiconductor substrate 200, described Semiconductor substrate 200 comprises first area 11 and second area 12.
The material of described Semiconductor substrate 200 can be silicon (Si), germanium (Ge) or SiGe (GeSi), carborundum (SiC); Also can be silicon-on-insulator (SOI), germanium on insulator (GOI); Or can also be other material, such as GaAs etc. III-V compounds of group.
Follow-up formation PMOS transistor in the Semiconductor substrate 200 of described first area 11, follow-up formation nmos pass transistor in the Semiconductor substrate 200 of described second area 12.
Can N-type well region be formed in the Semiconductor substrate 200 of described first area 11, in the Semiconductor substrate 200 of described second area 12, can P type trap zone be formed.
Fleet plough groove isolation structure 201 can be formed, for the active area that electric isolation is adjacent in Semiconductor substrate 200 between described first area 11 and second area 12.
Please refer to Fig. 7, the Semiconductor substrate 200 of described first area 11 forms first grid structure 203, the Semiconductor substrate 200 of second area 12 forms second grid structure 204.
The follow-up grid structure as PMOS transistor of described first grid structure 203, the follow-up grid structure as nmos pass transistor of described second grid structure 204.
Described first grid structure 203 and second grid structure 204 comprise the gate dielectric layer be positioned in Semiconductor substrate 200 and the gate electrode be positioned on gate dielectric layer.
In one embodiment, the material of described gate dielectric layer is silica, and the material of described gate electrode is polysilicon.
In the present embodiment, the forming process of described first grid structure 203 and second grid structure 204 is: form the gate dielectric material layer covering described Semiconductor substrate; Described gate dielectric material layer forms layer of gate electrode material; Described layer of gate electrode material is formed patterned hard mask layer 205; With described hard mask layer 205 for mask, etch described layer of gate electrode material, the Semiconductor substrate 200 of first area 11 forms first grid structure 203, the Semiconductor substrate 200 of second area 12 forms second grid structure 204.
With reference to figure 8, described first grid structure 203 and second grid structure 204 sidewall surfaces form the first side wall 208, form the second side wall 209 on the first side wall 208 surface.
In the present embodiment, the forming process of described first side wall 208 and the second side wall 209 is: form the first spacer material layer covering described Semiconductor substrate 200, first grid structure 203 and second grid structure 204; Without the first spacer material layer described in mask etching, the sidewall surfaces of first grid structure 203 and second grid structure 204 forms the first side wall 208; Form the second spacer material layer covering described Semiconductor substrate 200, first grid structure 203, second grid structure 204 and the first side wall 208 surface; Without mask etching second spacer material layer, form the second side wall 209 on the first side wall 208 surface.In the present embodiment, described first side wall 208 goes back the sidewall surfaces of the hard mask layer 205 of cover graphics.
In another embodiment, the forming process of described first side wall and the second side wall is: form the first spacer material layer and the second spacer material layer that cover described Semiconductor substrate, first grid structure and second grid structure; Without the first spacer material layer described in mask etching and the second spacer material layer, the sidewall surfaces of first grid structure and second grid structure forms the first side wall, form the second side wall on the first side wall surface.The second sidewall section formed is positioned at the first side wall in Semiconductor substrate on the surface, thus follow-up after removal two side wall, more accurate in order to ensure the distance between the shallow doped source/drain regions of the nmos pass transistor formed and the sidewall of second grid structure, thus with described first side wall and second grid structure for mask, inject N-type impurity ion step in the Semiconductor substrate of the second area of second grid structure and the first side wall both sides before, need the first side wall of the part that contacts with the bottom of the second side wall etching removal first side wall.
The material of described first side wall 208 is not identical with the material of the second side wall 209, follow-up when removal the second side wall 209, second side wall 209 has high etching selection ratio relative to the first side wall 208, the pattern of the first side wall 208 keeps good, makes the positional precision of the shallow doped source/drain regions of the nmos pass transistor formed in the Semiconductor substrate of the second area 12 of second grid structure 204 and the first side wall 208 both sides by ion implantation technology higher.
The material of described first side wall 208 is low-K dielectric material, and to reduce the parasitic capacitance between grid structure and source region (or drain region), low-K dielectric material is SiCON, SiCOH, FSG or BSG, and the material of described second side wall 209 is SiN or SiC.In the present embodiment, the material of described first side wall 208 is SiCON, the material SiN of the second side wall 209.
In order to the short-channel effect of PMOS transistor after controlling well to anneal, consider the difference of the diffusion rate of p type impurity ion and N-type impurity ion, and the concentration of foreign ion in the shallow doped source/drain regions of the PMOS transistor of follow-up formation in the concentration of p type impurity ion and the shallow doped source/drain regions of the degree of depth and nmos pass transistor and the degree of depth, the width of described first side wall 208 is 40 ~ 70 dusts, and the width of the second side wall 209 is 20 ~ 40 dusts.
With reference to figure 9, with described first side wall 208, second side wall 209 and first grid structure 203 for mask, implanting p-type foreign ion in the Semiconductor substrate 200 of the first area 11 of first grid structure 203 and the second side wall 209 both sides, forms the shallow doped source/drain regions 214 of PMOS transistor.
Before carrying out P type ion implantation, also comprise: form the first mask layer 210 covering the Semiconductor substrate 200 of described second area 12, second grid structure 204 and the second side wall 209 surface.
Described first mask layer 210 prevents p type impurity ion implantation in the Semiconductor substrate 200 of second area 12.In one embodiment, the material of described first mask layer 210 is photoresist.
The quality of the p type impurity ion of described injection is less than the quality of the N-type impurity ion that the follow-up Semiconductor substrate 200 at second area 12 is injected, and described p type impurity ion is boron ion, boron fluoride ion, gallium ion or indium ion.In the present embodiment, described p type impurity ion is boron fluoride ion.
The energy of implanting p-type foreign ion is 1-5kev, and dosage is 1E14-5E15atom/cm
2.
The shallow doped source/drain regions 214 of the PMOS transistor of described formation has the first distance with the sidewall of first grid structure 203, and described first distance is 60 ~ 110 dusts.
With reference to Figure 10, remove described second side wall 209 (with reference to figure 9).
Remove described second side wall 209 and adopt wet-etching technology.
In the present embodiment, the solution that described wet-etching technology adopts is concentrated phosphoric acid, and the mass concentration of described concentrated phosphoric acid is 70-90%, and temperature is 120-170 degree Celsius.When removal second side wall 209 material, the second side wall 209 is made to be greater than 7:1 relative to the first side wall 208 tool etching selection ratio, thus the etching decreased the first side wall 208 and damage, the positional precision of the shallow doped source/drain regions of the nmos pass transistor of follow-up formation is improved.
Before described second side wall 209 of removal, also comprise, remove described first mask layer.
With reference to Figure 11, with described first side wall 208 and second grid structure 204 for mask, N-type impurity ion is injected in the Semiconductor substrate 200 of the second area 12 of second grid structure 204 and the first side wall 208 both sides, form the shallow doped source/drain regions 213 of nmos pass transistor, the quality of described N-type impurity ion is greater than the quality of p type impurity ion.
Inject N-type impurity ion in the Semiconductor substrate 200 of the second area 12 of second grid structure 204 and the first side wall 208 both sides before, also comprise: formed and cover the Semiconductor substrate 200 of described first area 11, the second mask layer 212 of first grid structure 203.In one embodiment, the material of described second mask layer 212 is photoresist
In the shallow doped source/drain regions 213 of described nmos pass transistor, the quality of the N-type impurity ion of doping is greater than the quality of doped p-type foreign ion in the shallow doped source/drain regions 214 of PMOS transistor.
Described N-type impurity ion is phosphonium ion, arsenic ion or antimony ion.In the present embodiment, described N-type impurity ion is phosphonium ion or arsenic ion.
The energy injecting N-type impurity ion is 1-5kev, and dosage is 1E14-5E15atom/cm
2.
The shallow doped source/drain regions 213 of the nmos pass transistor formed has second distance with the sidewall of second grid structure 204, and described second distance is less than the shallow doped source/drain regions 214 of PMOS transistor and the first distance of first grid structure 203.Described second distance is 40 ~ 70 dusts.
In the present embodiment, by forming the second side wall 209 (with reference to figure 9) and the first side wall 208, with the second side wall 209 (with reference to figure 9) and the first side wall 208 for mask, P type ion implantation is carried out to the Semiconductor substrate 200 of first area 11, control to form the first distance between the shallow doped source/drain regions 214 of PMOS transistor and first grid structure 203 sidewall, after removal second side wall 209, with the first side wall 208 for mask, ion implantation is carried out to the Semiconductor substrate 200 of second area 12, control to form the second distance between the shallow doped source/drain regions 213 of nmos pass transistor and second grid structure 204, second distance is made to be less than the first distance, technique is simple.
In the embodiment of the present invention, between the shallow doped source/drain regions 213 of the nmos pass transistor formed and the sidewall of second grid structure 204, second distance is less than the first distance between the shallow doped source/drain regions 214 of PMOS transistor and first grid structure 203 sidewall, and the quality of the N-type impurity ion of doping is greater than the quality of doped p-type foreign ion in the shallow doped source/drain regions 214 of PMOS transistor in the shallow doped source/drain regions 213 of described nmos pass transistor, thus follow-up carry out annealing activate foreign ion in the shallow doped source/drain regions 213 of nmos pass transistor and the shallow doped source/drain regions 214 of PMOS transistor time, the first distance between the shallow doped source/drain regions 214 of PMOS transistor and first grid structure 203 sidewall is greater than second distance between the shallow doped source/drain regions 213 of nmos pass transistor and the sidewall of second grid structure 204, to compensate the difference (p type impurity ion diffusion rates is greater than the diffusion rate of N-type impurity ion) of the shallow doped source/drain regions N-type impurity ion diffusion rates of p type impurity ion in the shallow doped source/drain regions of PMOS transistor and nmos pass transistor, thus it is suitable relative to the complexity of nmos pass transistor generation short-channel effect to make nmos pass transistor and PMOS transistor integration making technology form PMOS transistor.
Behind the shallow doped source drain region forming nmos pass transistor, also comprise: on the first side wall, form the 3rd side wall (not shown); With described 3rd side wall and first grid structure for mask, implanting p-type foreign ion in the Semiconductor substrate of the first area of first grid structure and the 3rd side wall both sides, form the dark doped source/drain regions (not shown) of PMOS transistor, the degree of depth of the dark doped source/drain regions of PMOS transistor is greater than the degree of depth of the shallow doped source/drain regions of PMOS transistor; With described 3rd side wall and second grid structure for mask, N-type impurity ion is injected in the Semiconductor substrate of the second area of second grid structure and the 3rd side wall both sides, form the dark doped source/drain regions (not shown) of nmos pass transistor, the degree of depth of the dark doped source/drain regions of nmos pass transistor is greater than the degree of depth of the shallow doped source/drain regions of nmos pass transistor.
With reference to Figure 12, annealing process, activates the N-type impurity ion in the shallow doped source/drain regions 213 of p type impurity ion in the shallow doped source/drain regions 214 of PMOS transistor and nmos pass transistor.
Before annealing, remove described second mask layer 212 (with reference to Figure 11).Cineration technics, plasma etching industrial can be adopted to remove described second mask layer 212.
When annealing, the diffusion rate of the N-type impurity ion in the shallow doped source/drain regions 213 of nmos pass transistor is less than the diffusion rate of the p type impurity ion in the shallow doped source/drain regions 214 of PMOS transistor, but because between the shallow doped source/drain regions 213 of nmos pass transistor that formed before annealing and the sidewall of second grid structure 204, second distance is less than the first distance between the shallow doped source/drain regions 214 of PMOS transistor and first grid structure 203 sidewall, thus after annealing, equal or the approximately equal of overlapping width bottom the shallow doped source/drain regions 213 of the overlapping width bottom the shallow doped source/drain regions 214 of PMOS transistor and first grid structure 203 and nmos pass transistor and second grid structure 204, thus it is suitable relative to the complexity of nmos pass transistor generation short-channel effect to make nmos pass transistor and PMOS transistor integration making technology form PMOS transistor.
Described annealing process comprises spike annealing and laser annealing.When annealing, the foreign ion adulterated in the dark doped source/drain regions of foreign ion and the nmos pass transistor adulterated in the dark doped source/drain regions of PMOS transistor can be activated simultaneously.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (20)
1. a formation method for semiconductor structure, is characterized in that, comprising:
There is provided Semiconductor substrate, described Semiconductor substrate comprises first area and second area;
The Semiconductor substrate of described first area is formed first grid structure, the Semiconductor substrate of second area is formed second grid structure;
Form the first side wall on the surface in described first grid structure and second grid structure side wall, form the second side wall on the first side wall surface;
With described first side wall, the second side wall and first grid structure for mask, implanting p-type foreign ion in the Semiconductor substrate of the first area of first grid structure and the second side wall both sides, forms the shallow doped source/drain regions of PMOS transistor;
Remove described second side wall;
With described first side wall and second grid structure for mask, N-type impurity ion is injected in the Semiconductor substrate of the second area of second grid structure and the first side wall both sides, form the shallow doped source/drain regions of nmos pass transistor, the quality of described N-type impurity ion is greater than the quality of p type impurity ion;
Carry out annealing process, activate PMOS transistor shallow doped source/drain regions in p type impurity ion and nmos pass transistor shallow doped source/drain regions in N-type impurity ion.
2. the formation method of semiconductor structure as claimed in claim 1, it is characterized in that, the forming process of described first side wall and the second side wall is: form the first spacer material layer covering described Semiconductor substrate, first grid structure and second grid structure; Without the first spacer material layer described in mask etching, the sidewall surfaces of first grid structure and second grid structure forms the first side wall; Form the second spacer material layer covering described Semiconductor substrate, first grid structure, second grid structure and the first side wall surface; Without mask etching second spacer material layer, form the second side wall on the first side wall surface.
3. the formation method of semiconductor structure as claimed in claim 1, it is characterized in that, the forming process of described first side wall and the second side wall is: form the first spacer material layer and the second spacer material layer that cover described Semiconductor substrate, first grid structure and second grid structure; Without the first spacer material layer described in mask etching and the second spacer material layer, the sidewall surfaces of first grid structure and second grid structure forms the first side wall, form the second side wall on the first side wall surface.
4. the formation method of semiconductor structure as claimed in claim 3, is characterized in that, after described second side wall of removal, and the first side wall of the part that contacts with the bottom of the second side wall of etching removal first side wall.
5. the formation method of semiconductor structure as claimed in claim 2 or claim 3, it is characterized in that, the material of described first side wall is not identical with the material of the second side wall.
6. the formation method of semiconductor structure as claimed in claim 5, it is characterized in that, the material of described first side wall is low-K dielectric material, and low-K dielectric material is SiCON, SiCOH, FSG or BSG, and the material of described second side wall is SiN or SiC.
7. the formation method of semiconductor structure as claimed in claim 6, is characterized in that, removes described second side wall and adopts wet-etching technology.
8. the formation method of semiconductor structure as claimed in claim 7, is characterized in that, when described second spacer material is SiN, the solution that described wet-etching technology adopts is concentrated phosphoric acid.
9. the formation method of semiconductor structure as claimed in claim 8, it is characterized in that, the mass concentration of described concentrated phosphoric acid is 70-90%, and temperature is 120-170 degree Celsius.
10. the formation method of semiconductor structure as claimed in claim 1, it is characterized in that, the width of described first side wall is greater than the width of the second side wall.
The formation method of 11. semiconductor structures as claimed in claim 10, it is characterized in that, the width of described first side wall is 40 ~ 70 dusts, the width of the second side wall is 20 ~ 40 dusts.
The formation method of 12. semiconductor structures as described in claim 1 or 11, it is characterized in that, described p type impurity ion is boron ion, boron fluoride ion, gallium ion or indium ion.
The formation method of 13. semiconductor structures as claimed in claim 12, it is characterized in that, described N-type impurity ion is phosphonium ion, arsenic ion or antimony ion.
The formation method of 14. semiconductor structures as claimed in claim 13, is characterized in that, described p type impurity ion is boron ion or boron fluoride ion, and described N-type impurity ion is phosphonium ion or arsenic ion.
The formation method of 15. semiconductor structures as claimed in claim 14, is characterized in that, the energy injecting N-type impurity ion is 1-5kev, and dosage is 1E14-5E15atom/cm
2.The energy of implanting p-type foreign ion is 1-5kev, and dosage is 1E14-5E15atom/cm
2.
The formation method of 16. semiconductor structures as claimed in claim 15, it is characterized in that, described annealing process comprises spike annealing and laser annealing.
The formation method of 17. semiconductor structures as claimed in claim 1, is characterized in that, behind the shallow doped source drain region forming nmos pass transistor, also comprises: on the first side wall, form the 3rd side wall; With described 3rd side wall and first grid structure for mask, implanting p-type foreign ion in the Semiconductor substrate of the first area of first grid structure and the 3rd side wall both sides, form the dark doped source/drain regions of PMOS transistor, the degree of depth of the dark doped source/drain regions of PMOS transistor is greater than the degree of depth of the shallow doped source/drain regions of PMOS transistor; With described 3rd side wall and second grid structure for mask, N-type impurity ion is injected in the Semiconductor substrate of the second area of second grid structure and the 3rd side wall both sides, form the dark doped source/drain regions of nmos pass transistor, the degree of depth of the dark doped source/drain regions of nmos pass transistor is greater than the degree of depth of the shallow doped source/drain regions of nmos pass transistor.
The formation method of 18. semiconductor structures as claimed in claim 1, it is characterized in that, in the Semiconductor substrate of the first area of first grid structure both sides before implanting p-type foreign ion, also comprise: the first mask layer forming Semiconductor substrate, second grid structure and the second side wall covering described second area.
The formation method of 19. semiconductor structures as claimed in claim 17, is characterized in that, before removal second side wall, removes described first mask layer.
The formation method of 20. semiconductor structures as claimed in claim 1, it is characterized in that, inject N-type impurity ion in the Semiconductor substrate of the second area of second grid structure both sides before, also comprise: the second mask layer forming Semiconductor substrate, first grid structure and the first side wall covering described first area; After injecting N-type impurity ion, remove described second mask layer.
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| US20030107104A1 (en) * | 2001-12-12 | 2003-06-12 | Zhiqiang Wu | Complementary transistors with controlled drain extension overlap |
| JP2004349372A (en) * | 2003-05-21 | 2004-12-09 | Renesas Technology Corp | Semiconductor device |
| JP2005191267A (en) * | 2003-12-25 | 2005-07-14 | Fujitsu Ltd | Method of manufacturing cmos semiconductor device |
| US20060226558A1 (en) * | 2005-04-11 | 2006-10-12 | Nec Electronics Corporation | Method of manufacturing a semiconductor device and semiconductor device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030107104A1 (en) * | 2001-12-12 | 2003-06-12 | Zhiqiang Wu | Complementary transistors with controlled drain extension overlap |
| JP2004349372A (en) * | 2003-05-21 | 2004-12-09 | Renesas Technology Corp | Semiconductor device |
| JP2005191267A (en) * | 2003-12-25 | 2005-07-14 | Fujitsu Ltd | Method of manufacturing cmos semiconductor device |
| US20060226558A1 (en) * | 2005-04-11 | 2006-10-12 | Nec Electronics Corporation | Method of manufacturing a semiconductor device and semiconductor device |
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Application publication date: 20160511 |