JP2005167258A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a MOS transistor in which a short channel effect can be effectively suppressed in spite of further miniaturization. <P>SOLUTION: In a MOS transistor formation region 18, a gate electrode 6 is formed through an element isolation region 4 and a gate insulation film 5; and a cavity region covered with a thermally-oxidized film 10 is provided in a silicon substrate 1 beneath a channel region and beneath a source diffused layer 7 and a drain diffused layer 8. Thus, a semiconductor device is obtained. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a semiconductor device and a method for manufacturing the semiconductor device in which short channel effect of a MOS transistor is suppressed.

  In recent years, a large-scale integrated circuit (LSI) formed by integrating a large number of transistors, resistors, and the like so as to achieve an electric circuit and integrated on a single chip is often used as an important part of computers and communication devices.

  For this reason, the performance of the entire device is greatly linked to the performance of the LSI alone. The performance improvement of a single LSI can be realized by miniaturizing elements. For example, in the case of a MOS transistor, it has been possible to achieve high speed, low power consumption, and high integration by reducing its dimensions.

  However, various problems have arisen by reducing the element size. For example, shortening the channel length has the effect of reducing the channel resistance, but causes the short channel effect.

  In order to suppress this short channel effect, the junction depth of the source / drain is made shallow, particularly when the power supply voltage is low, a shallow high impurity concentration is formed near the gate electrode, in other words, the LLD structure. It has been found that replacing the shallow low impurity concentration diffusion layer with a shallow high impurity concentration diffusion layer is effective. This high impurity concentration diffusion layer is usually called an extension layer. Alternatively, by increasing the impurity concentration in the region immediately below the channel region (by forming a punch-through prevention layer), there is an effect of suppressing the punch-through phenomenon.

  However, in either method, the smaller the size (the smaller the size), the more steep profile is formed, that is, the formation of a very shallow extension layer with a high impurity concentration, or the very shallow profile. It is difficult to form a punch-through prevention layer under the channel region.

  Further, by reducing the element size, the ratio of various parasitic components is relatively increased. For example, the junction capacitance of the source / drain becomes a ratio that affects the operation speed.

  As one of the solutions, an attempt has been made to eliminate the junction capacitance by using a very thin SOI substrate and bringing the bottom surface of the junction into contact with the buried oxide film of the SOI substrate.

  However, in this method, in addition to the problem that the SOI substrate is expensive and expensive, since the element operation region is on the buried oxide film, carriers generated by the element operation are accumulated. Since the storage effect occurs, there is a problem that it is difficult to operate the element stably.

  In addition, an attempt is made to suppress the short channel effect by creating a back gate in the buried oxide film of the ultrathin SOI substrate and applying a voltage to this to deplete the region under the channel to prevent punch through. Proposed.

  As described above, in order to suppress the short channel effect of the MOS transistor, the introduction of an extension layer or a punch-through prevention layer has been proposed, but as the miniaturization progresses, it becomes difficult to suppress the short channel effect of the MOS transistor. There was a problem of becoming.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device capable of effectively suppressing the short channel effect of a field effect transistor even if miniaturization is advanced, and a method for manufacturing the same. There is.

[Constitution]
In order to achieve the above object, a semiconductor device according to the present invention is formed in a semiconductor substrate, a field effect transistor formed on the semiconductor substrate, and the semiconductor substrate under a formation region of the field effect transistor, Unlike the semiconductor element constituting the semiconductor substrate, the semiconductor element includes a semiconductor layer that suppresses extension of a depletion layer under the field effect transistor formation region.

  Another semiconductor device according to the present invention is formed in a semiconductor substrate, a field effect transistor formed on a flat portion of the semiconductor substrate, and the semiconductor substrate under a source region and a drain region of the field effect transistor. And an insulator having a dimension in the channel width direction of the field effect transistor larger than a dimension in the channel width direction of the field effect transistor formation region.

  Here, it is preferable that the semiconductor layer or the insulator is formed in the semiconductor substrate under a channel region of the field effect transistor.

  The semiconductor layer or the insulator is preferably formed in the semiconductor substrate under the source region and the drain region of the field effect transistor.

  The semiconductor layer or the insulator is more preferably formed in the silicon substrate under the channel region, the source region, and the drain region.

  The field effect transistor is, for example, a MOS transistor or a MESFET.

  In the case of a semiconductor layer, the field effect transistor may be formed on either a flat part or a convex part on the surface of the substrate.

  Another semiconductor device according to the present invention includes a field effect transistor formed on a semiconductor substrate, an electrode formed in the semiconductor substrate under the field effect transistor formation region, and an interface between the electrode and the semiconductor substrate. And an insulating gate structure constituted by the formed insulating film.

  A method of manufacturing a semiconductor device according to the present invention includes a step of forming a groove on a surface of a semiconductor substrate, a step of closing an opening of the groove by a heat treatment under reduced pressure, and forming a cavity, and a region including the cavity And a step of forming a field effect transistor.

  Here, the heat treatment under reduced pressure is preferably performed in a non-oxidizing atmosphere. The non-oxidizing atmosphere is, for example, a hydrogen atmosphere.

  A method of manufacturing a semiconductor device according to the present invention includes a step of forming a groove on a surface of a semiconductor substrate, a step of filling the inside of the groove with an insulator to a midway depth, and a step of depositing an amorphous semiconductor film on the entire surface. The amorphous semiconductor film is epitaxially grown by heat treatment in a reducing atmosphere, and the remaining portion inside the trench is filled with a single crystal semiconductor, and a lateral field effect transistor is formed on the region including the insulator. And a step of performing.

[Action]
According to the semiconductor device of the present invention, since the extension of the depletion layer from the source and the drain stops at the semiconductor layer or the insulator, it is possible to prevent the depletion layer from spreading in the channel region. Therefore, according to the present invention, the short channel effect of the field effect transistor can be effectively suppressed even if miniaturization is advanced.

  Further, when the semiconductor layer or the insulator is formed in the semiconductor substrate under the source region and the drain region of the field effect transistor, unlike the case where the SOI substrate is used, there is no increase in cost and the substrate accumulation effect. The junction capacitance of the source / drain can be made sufficiently small.

  According to another semiconductor device of the present invention, the semiconductor device includes an insulated gate structure including an electrode formed in the semiconductor substrate and an insulating film formed at an interface between the electrode and the semiconductor substrate. Therefore, the electrode can be used as a back gate electrode. Therefore, by applying an appropriate voltage to the electrode, the spread of the depletion layer in the channel region of the field effect transistor can be suppressed, so that the short channel effect can be effectively suppressed even when the element is miniaturized. .

  According to the present invention, since the extension of the depletion layer from the source and drain stops at the semiconductor layer or the insulator, it is possible to prevent the depletion layer from spreading in the channel region. The short channel effect can be effectively suppressed.

  Further, according to the present invention, an insulated gate structure comprising an electrode (back gate electrode) formed in a semiconductor substrate and an insulating film (gate insulating film) formed at the interface between the electrode and the semiconductor substrate. Therefore, by applying an appropriate voltage to the electrodes, the spread of the depletion layer in the channel region can be suppressed, so that the short channel effect can be effectively suppressed even if device miniaturization is advanced. Become.

  Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings.

(First embodiment)
1A and 1B are a plan view and a cross-sectional view of a MOS transistor according to a first embodiment of the present invention, where FIG. 1A is a plan view and FIG. 1B is an arrow LL in the plan view. 'Cross-sectional view (cross-sectional view parallel to the channel length direction), FIG. 8 (c) shows an WW' cross-sectional view (cross-sectional view parallel to the channel width direction) of the plan view.

  In the figure, reference numeral 1 denotes a silicon substrate. A shallow element isolation groove 2 for element isolation (STI) is formed on the surface of the silicon substrate 1. The inside of the element isolation trench 2 is buried with a silicon oxide film 4 via a thermal oxide film 3.

  A gate electrode 6 is formed on the silicon substrate 1 in the MOS transistor formation region 18 defined by the element isolation trench 2 via a gate insulating film 5. The gate electrode 6 is formed of, for example, a polycrystalline silicon film. A source diffusion layer 7 and a drain diffusion layer 8 are formed on both sides of the gate electrode 6, respectively.

  A cavity 9 is formed in the silicon substrate 1 under the channel region of the MOS transistor, under the source diffusion layer 7 and under the drain diffusion layer 8, and the inner surface of the cavity 9 is covered with a thermal oxide film 10.

  According to the present embodiment, since the extension of the depletion layer from the source diffusion layer 7 and the drain diffusion layer 8 stops at the cavity 9, it is possible to prevent the depletion layer from spreading in the channel region. Therefore, according to the present embodiment, the short channel effect can be effectively suppressed even if the MOS transistor is miniaturized.

  Further, according to the present embodiment, since the cavity 9 is partially formed under the source diffusion layer 7 and the drain diffusion layer 8, the junction capacitance can be sufficiently reduced. Here, unlike the case where the SOI substrate is used, the MOS transistor is only partially insulated from the silicon substrate 1 by the cavity 9, so that there is no substrate accumulation effect that carriers generated by the element operation accumulate. Stable element operation can be obtained. Further, since it is not necessary to use an SOI substrate which is an expensive substrate, there is naturally no problem of an increase in cost.

  Next, a method for forming the MOS transistor of this embodiment will be described. 2 to 4 are process sectional views showing the forming method.

  First, as shown in FIG. 2A, a photoresist pattern 11 is formed on a silicon substrate 1, and the silicon substrate 1 is patterned by anisotropic etching, for example, RIE, using the photoresist pattern 11 as a mask. A groove 12 is formed. Thereafter, the photoresist pattern 11 is carbonized and peeled off.

  Next, as shown in FIG. 2B, high-temperature annealing is performed in a non-oxidizing atmosphere under reduced pressure, for example, 100% hydrogen atmosphere at 10 Torr and 1000 ° C., thereby closing the opening of the groove 12 to form the cavity 9. Form.

  Next, after forming an amorphous silicon film (not shown) having a thickness of 100 nm on the entire surface, heat treatment at a high temperature of 1100 ° C. or higher is performed in a reducing atmosphere under reduced pressure, for example, 10 Torr. Since the amorphous silicon film at this time is for facilitating the flattening of the substrate surface, the film thickness of the amorphous silicon film only needs to be such that solid phase growth can be easily performed.

  Although the substrate surface can be planarized without an amorphous silicon film, the substrate surface planarization process can be completed in a short time by depositing an amorphous silicon film that can be crystallized in advance. It becomes possible.

  However, when the substrate surface is planarized without using an amorphous silicon film, the planarization proceeds due to silicon migration (silicon reconstruction) on the substrate surface. There is an effect that the crystallinity of the substrate surface can be improved as compared with the case of planarization by phase growth.

  By the heat treatment, the amorphous silicon film is epitaxially grown from the substrate side by solid phase growth, and becomes a single crystal silicon film and is integrated with the silicon substrate 1. Then, as shown in FIG. 2C, the silicon atoms on the active substrate surface migrate by surface diffusion so that the substrate surface becomes flat. The crystallinity of the substrate surface is further improved by migration at this time, that is, by reconfiguration of silicon on the substrate surface. Further, as another method for planarizing the substrate surface, for example, there is a method of polishing and planarizing the surface of the silicon substrate 1 of FIG.

  Next, as shown in FIG. 2D, after the surface of the silicon substrate 1 is thermally oxidized to form a thermal oxide film 13, a silicon nitride film 14 is formed on the thermal oxide film 13 using a CVD method.

  Next, as shown in FIG. 3E, after forming a photoresist pattern 15 on the silicon nitride film 14, the silicon nitride film 14, the thermal oxide film 13 and the silicon substrate 1 are differently formed using the photoresist pattern 15 as a mask. The element isolation trench 2 is formed by patterning using isotropic etching, for example, RIE. Thereafter, the photoresist pattern 15 is carbonized and peeled off.

  Next, as shown in FIG. 3F, the exposed surface of the isolation trench 2 is thermally oxidized in a dry oxidation atmosphere at 950 ° C. for 30 minutes to form a thermal oxide film 3. At this time, since the inner surface of the cavity 9 is also oxidized simultaneously, a thermal oxide film 10 is formed on the inner surface of the cavity 9. By forming such a thermal oxide film 10, the extension of the depletion layer from the source diffusion layer 7 and the drain diffusion layer 8 is effectively suppressed, and the disadvantage that these depletion layers are connected can be reliably prevented. It becomes possible.

  Thereafter, a silicon oxide film 4 is deposited on the entire surface using the CVD method, and the element isolation trench 2 is buried.

  Next, as shown in FIG. 3G, the silicon oxide film 4 is polished by CMP until the surface of the silicon nitride film 13 is exposed.

Next, as shown in FIG. 3H, the silicon nitride film 14 is selectively removed using a hot H ₃ PO ₄ solution.

  Next, as shown in FIG. 4I, the thermal oxide film 13 and the silicon oxide film 4 outside the element isolation trench 2 are removed using a diluted HF solution. At this time, the thermal oxide film 3 at the upper edge portion of the element isolation trench 2 is somewhat removed, and the surface of the silicon substrate 1 at the upper edge portion of the element isolation trench 2 is exposed.

  Next, as shown in FIG. 4J, after the surface of the exposed silicon substrate 1 is thermally oxidized to form a thermal oxide film 16 having a thickness of, for example, 10 nm, the threshold voltage is adjusted. Impurity ions 17 are implanted into the surface of the silicon substrate 1 through the thermal oxide film 16. Thereafter, the thermal oxide film 16 is removed as shown in FIG.

  Next, as shown in FIG. 4L, the gate insulating film 5 is formed by exposing the silicon substrate 1 to an HCl atmosphere at 900 ° C., for example. At this time, the gate insulating film 5 is formed not only on the MOS transistor formation region but also on the upper edge portion of the element isolation trench 2. As a result, there is no exposed silicon surface in the element isolation trench 2.

  Next, as shown in FIG. 1L, for example, a polycrystalline silicon film to be the gate electrode 6 is formed on the entire surface, and then the polycrystalline silicon film is patterned to form the gate electrode 6. Although the polysilicon gate electrode is formed here, a gate electrode having another structure such as a polymetal gate electrode or a metal gate electrode may be formed.

  Finally, as shown in FIG. 1L, impurity ions are implanted into the surface of the silicon substrate 1 using the gate electrode 6 as a mask, and then annealing is performed, so that the source diffusion layer 7 and the drain diffusion layer 8 are self-assembled. The MOS transistors are completed by forming them in a consistent manner.

  Next, the method for forming the cavity 9 by high temperature annealing under reduced pressure will be described in more detail. FIG. 5 is a cross-sectional view showing the difference in how the cavities are formed due to the difference in the aspect ratio of the groove. Specifically, the groove 12 having a different aspect ratio (AR) is 1000 ° C., 10 Torr (under reduced pressure). FIG. 5 shows the result of heat treatment (high-temperature annealing) for 10 minutes in a hydrogen atmosphere. FIG. 5A shows AR = 1, FIG. 5B shows AR = 5, and FIG. 5C shows AR. = 10 results are shown.

  From FIG. 5A, it can be seen that the cavity 9 cannot be formed when the aspect ratio is small.

  Further, FIG. 5B shows that when the aspect ratio is 5 or more, the cavity 9 separated from the bottom of the groove 12 in a shape close to a sphere can be formed.

  Further, FIG. 5C shows that when the aspect ratio is further increased, a plurality of nearly spherical cavities 9 can be formed at equal intervals from the bottom of the groove 12.

From the above results, it can be seen that in order to form the cavity 9, it is necessary to form the groove 12 with an aspect ratio of a certain degree or more. If high-temperature annealing is continued, the substrate surface is finally flattened as shown by the broken line in the figure. FIG. 6 is a process cross-sectional view for explaining a method for controlling the shape and size of the cavity. When the grooves 12 are formed by changing the upper and lower taper angles θ and β (θ> β) as shown in FIGS. 6A and 6B, the positions having different taper angles are hollow. Therefore, the shape and size of the cavity 9 can be controlled as shown in FIGS. 6 (c) and 6 (d). The groove 12 having such a shape can be realized, for example, by forming a groove having a tapered side wall by RIE and subsequently forming a groove having a vertical side wall by RIE under different conditions.

  In FIG. 6, the shape and size of the cavity 9 are controlled by making the depth of the groove 12 at the taper angle θ the same and changing the depth of the groove 12 at the taper angle β, but vice versa. May be.

Further, as shown in the plan view of FIG. 7A and the AA ′ sectional view of FIG. 7B, the pattern viewed from above the silicon substrate 1 is rectangular (short side: a, long side: b). After the grooves 12 of FIG. 7 are arranged at intervals of 2 (ab / π) ^0.5 or less, high-temperature annealing is performed, so that the plan view of FIG. 7C and the AA ′ cross-sectional view of FIG. As shown, a rod-like cavity 9 can also be formed.

During annealing at a high temperature (for example, 1100 ° C.) under reduced pressure (for example, at 10 Torr), the groove 12 is deformed into a circle by migration of Si atoms in the vicinity of the surface of the silicon substrate 1 while keeping the cross-sectional area constant. Therefore, as described above, if the grooves 12 are arranged at intervals of a circle diameter 2 (ab / π) ^0.5 or less, which is the final form of the grooves 12, the adjacent grooves 12 are integrated by high-temperature annealing.

  By using this rod-shaped cavity 9 and arranging a plurality of MOS transistor formation regions 18 as shown in the plan view of FIG. 8A, one cavity 9 is commonly used for a plurality of MOS transistors. be able to. FIGS. 8B and 8C are an L-L ′ sectional view and a W-W ′ sectional view of the MOS transistor Tr of FIG.

  Further, as shown in FIG. 9, by forming the cavity 9 and the insulating film 4 immediately below the source diffusion layer 7 and the drain diffusion layer 8, the source / drain junction capacitance can be greatly reduced. In order to obtain such a structure, first, two cavities 9 are formed as shown in FIG. 10A, then a resist pattern 15 is formed as shown in FIG. 10B, and then FIG. ), The element isolation groove 2 connected to the cavity 9 using the resist pattern 15 as a mask, in other words, the element isolation groove 2 integrated with the cavity 9 is formed. After this, the process after FIG.3 (f) is followed.

  As described above, the shape of the cavity 9 (FIGS. 1, 6, and 7) and the formation position (FIGS. 1, 8, and 9) are arbitrary. Furthermore, the number and size of the cavities 9 are also arbitrary. What is important about the cavity 9 is that the high-aspect-ratio groove opening is closed by high temperature annealing to turn the groove into a cavity.

  Next, a method for aligning the cavity 9 will be described with reference to the process cross-sectional view of FIG.

  First, as shown in FIG. 11A, when the groove 12 is formed, an element isolation groove 12 ′ having a diameter larger than that of the element isolation groove 12 and shallower than the MOS transistor formation region is formed. 11 (b), in the step of flattening the surface of the region where the groove 12 is formed, the surface of the region where the groove 12 ′ is formed is not flattened, and the groove 12 ′ remains in the form of a depression. By using this as the alignment mark, the element isolation trench 2 that defines the MOS transistor formation region including the cavity 9 can be easily formed.

  FIG. 12 is a process chart showing another method for aligning the cavity 9.

  In this case, in the step of FIG. 2A, the groove 12 is formed using the insulating film mask 19 instead of the photoresist pattern 11, and the cavity 9 is formed by high-temperature annealing (FIG. 12A). As shown in FIG. 12B, the insulating mask 19 on the silicon substrate 1 is patterned to form a mark 19a made of an insulator outside the MOS transistor formation region.

  Next, as shown in FIG. 12C, an amorphous silicon film 20 is deposited on the entire surface.

  Next, as shown in FIG. 12D, the amorphous silicon film 20 is single-crystallized by heat treatment, and after the surface is flattened, the surface is receded by etch back or CMP to expose the surface of the mark 19a. . At this time, the mark 19a is used as an etching stopper. Since the exposed surface of the mark 19a is an insulator and has optical properties different from that of silicon, it can be used as an alignment mark when the element isolation trench 2 is formed.

  In this embodiment, the MOS transistor formed on the flat portion of the silicon substrate has been described. However, the present invention can also be applied to a MOS transistor such as an SGT (Surrounding Gate Transistor) formed on the convex portion of the silicon substrate. It is.

(Second Embodiment)
FIG. 13 is a plan view and a sectional view showing a MOS transistor according to the second embodiment of the present invention. In the following drawings, the same reference numerals (including those with different subscripts) as those in the previous figures indicate the same reference numerals or corresponding parts.

  This embodiment is different from the first embodiment in that an insulating film 21 (insulator) is used instead of the cavity 9. With such a configuration, the depletion layer from the source diffusion layer 7 and the drain diffusion layer 8 stops at the insulating film 21, so that the same effect as in the first embodiment can be obtained.

  FIG. 14 is a process cross-sectional view illustrating the method for forming the MOS transistor of this embodiment. First, as in the first embodiment, as shown in FIG. 14A, grooves 12 are formed on the surface of the silicon substrate 1.

  Next, as shown in FIG. 14B, after filling the bottom of the trench 12 with the insulating film 21, an amorphous silicon film 22 of, eg, a 100 nm-thickness is deposited on the entire surface. For example, a silicon oxide film is used as the insulating film 21.

  The insulating film 21 is embedded as follows, for example. First, after forming the trench 12, an insulating film is deposited on the entire surface. Next, the insulating film is polished by CMP using the silicon substrate 1 as a stopper, so that the insulating film is left only in the trench 12. Finally, etching back is performed by RIE, and the insulating film 21 is formed by leaving the insulating film only at the bottom of the trench.

  Here, the insulating film 21 can be formed only at the bottom of the trench even if time-controlled wet etching is performed instead of RIE. For example, when a silicon oxide film is used as the insulating film 21, a hydrofluoric acid aqueous solution may be used as the etchant.

  Thereafter, high-temperature heat treatment at 1100 ° C. or higher is performed in a reducing atmosphere under reduced pressure, for example, 10 Torr. By this heat treatment, the amorphous silicon film 22 is epitaxially grown from the substrate side by solid phase growth and becomes a single crystal silicon film and is integrated with the silicon substrate 1. As a result, as shown in FIG. 14C, the inside of the groove 12 is filled with single crystal silicon, and the substrate surface is planarized.

  If the amorphous silicon film 22 is not deposited, the inside of the groove 12 on the insulating film 21 cannot be filled, and thus a film thickness that can be easily crystallized by solid phase growth as in the present embodiment (here In this case, it is necessary to deposit an amorphous silicon film 22 of 100 nm).

  Thereafter, a MOS transistor is formed according to the step of FIG. 3E of the first embodiment. However, the process of the thermal oxide film 10 covering the inner surface of the cavity 9 is not necessary.

  The planar pattern of the grooves 12 may be a rectangle having a larger ratio of long side / short side as in the third embodiment described below.

(Third embodiment)
FIG. 15 is a process cross-sectional view illustrating a MOS transistor formation method according to the third embodiment of the present invention. In the present embodiment, a rod-shaped insulating film is used instead of the rod-shaped cavity of FIG.

  First, as shown in FIG. 15A, after the bottom of the trench 12 is filled with an insulating film 21, an amorphous silicon film 22 is deposited on the entire surface. Here, the planar pattern of the groove 12 in FIG. 15 is a rectangle having a larger ratio of long side / short side than the planar pattern of the groove 12 in FIG.

  Next, by high-temperature heat treatment in a reducing atmosphere, as shown in FIG. 15B, the inside of the groove 12 is filled with a single crystal silicon film, and the substrate surface is flattened. Up to this point, this is basically the same as in the second embodiment.

  However, the size of the groove 12 is such that a plurality of MOS transistor formation regions 18 as shown in FIG. 8A can be formed. Therefore, the LL ′ and WW ′ cross-sectional views of FIG. 15 are cross-sectional views of the regions extending over the formation regions of the plurality of MOS transistors, unlike the case of FIG. 14 (one MOS transistor). ing.

  Next, as shown in FIG. 15C, the groove 12 a is formed so as to remove the peripheral portion of the insulating film 21, that is, so that the side surface of the insulating film 21 is exposed.

  Next, as shown in FIG. 15D, the insulating film 21 is removed by wet etching to form a space 9 s that becomes a cavity connected to the groove 12. Here, for example, if the insulating film 21 is a silicon oxide film, it may be removed using a hydrofluoric acid aqueous solution as an etchant.

  In the present embodiment, since the cavity 9 is formed without using the migration of surface silicon, the corner portion has an acute angle unlike the case of FIG. In the case of this embodiment, the shape of the cavity 9 can be controlled more easily than the case of using surface silicon migration.

  Next, after patterning the silicon substrate 1 on the cavity 9 to form element isolation grooves (not shown), a plurality of MOS transistor formation regions 18 are formed as shown in FIG. The trench 12a and the element isolation trench are filled with an insulating film. As a result, a cavity is formed.

  At this time, since the trench 12a is divided into a plurality of regions by the element isolation trench, that is, the trench 12a is connected to the plurality of element isolation trenches, the inside of the trench 12a can be easily embedded with the insulating film. It becomes possible. Even if a cavity remains inside the groove 12a, there is no problem because this cavity functions in the same manner as the insulating film inside the groove 12a.

  Finally, a plurality of MOS transistors are formed according to a normal process. Even with the plurality of MOS transistors formed in this way, the same effect as in the first embodiment can be obtained.

(Fourth embodiment)
16A and 16B are a plan view and a cross-sectional view of a MOS transistor according to the fourth embodiment of the present invention, in which FIG. 16A is a plan view and FIG. 16B is an arrow LL in the plan view. 'Cross-sectional view, (c) shows an WW' cross-sectional view of the plan view.

  In the figure, reference numeral 31 denotes a silicon substrate. A shallow element isolation groove 32 for element isolation (STI) is formed on the surface of the silicon substrate 31. The inside of the element isolation trench 32 is buried with a silicon oxide film 34 via a thermal oxide film 33.

  A gate electrode 36 is formed on the silicon substrate 31 in the MOS transistor formation region 48 defined by the element isolation trench 32 via a gate insulating film 35, and a gate side wall insulating film 37 is formed on the side wall of the gate electrode 36. ing. The gate electrode 36 is made of a polycrystalline silicon film, a laminated film of a polycrystalline silicon film and a metal silicide film, or a metal film.

  A source diffusion layer 38 and a drain diffusion layer 39 are formed on the surface of the silicon substrate 31 so as to face each other with the gate electrode 36 therebetween. The source diffusion layer 37 includes a shallow diffusion layer (extension layer) 38a having a low impurity concentration and a deep diffusion layer 38b having a higher impurity concentration than the diffusion layer 38a. The diffusion layer 38a is formed in a region closer to the gate electrode 36 than the diffusion layer 38b.

  Under the channel region of the MOS transistor, a cavity 40 that is in contact with the bottom corners of the shallow diffusion layers 38a and 39a and has a rectangular shape as viewed from above the element is formed. The inner surface of the cavity 40 is covered with a thermal oxide film 41.

  According to the present embodiment, since the extension of the depletion layer from the source diffusion layer 38 and the drain diffusion layer 39 stops at the cavity 40, the short channel effect can be effectively suppressed even if the MOS transistor is miniaturized. The same effects as those of the first embodiment can be obtained.

  Furthermore, the MOS transistor of this embodiment can be formed without causing misalignment between the cavity 40 and the source diffusion layer 38 and misalignment between the cavity 40 and the drain layer 39, as will be described below. Therefore, even if a large number of MOS transistors of this embodiment are formed, the variation in element characteristics is sufficiently small. Therefore, a semiconductor integrated circuit with a high yield can be realized by using the MOS transistor of this embodiment.

  Next, a method for forming the MOS transistor of this embodiment will be described. 17 to 20 are process cross-sectional views illustrating the forming method. The left side of each figure shows a cross-sectional view parallel to the channel length direction, and the right side shows a cross-sectional view parallel to the channel width direction. However, the element isolation trench is omitted in the cross-sectional view parallel to the channel length direction.

  First, as shown in FIG. 17A, an element isolation groove 32 whose inner surface is covered with a thermal oxide film 33 is formed on a silicon substrate 31 by a known technique, and then the inside of the element isolation groove 32 is filled. Then, a silicon oxide film 34 as an element isolation insulating film is deposited on the entire surface.

  Next, as shown in FIG. 17B, the silicon oxide film 34 outside the element isolation trench 32 is removed by CMP to planarize the surface, and then a silicon oxide film 42 and a silicon nitride film 43 are formed on the silicon substrate 31. The photoresist pattern 44 is formed sequentially.

  Next, as shown in FIG. 17C, using the photoresist pattern 44 as a mask, the silicon nitride film 43 and the silicon oxide film 42 are sequentially patterned by anisotropic etching, for example, RIE, followed by the photoresist pattern 44 and silicon. Using the nitride film 43 and the silicon oxide film 42 as a mask, the silicon substrate 31 is anisotropically etched to form a groove 45. Thereafter, the photoresist pattern 44 is carbonized and removed.

  Next, as shown in FIG. 18D, a silicon oxide film 46 is formed on the sidewall of the groove 45. Such a silicon oxide film 46 can be formed by forming a silicon oxide film on the entire surface, etching back the entire surface of the silicon oxide film by RIE, and leaving the silicon oxide film on the sidewall of the trench 45.

  Next, as shown in FIG. 18E, the epitaxial silicon layer 47 is exposed to the exposed portion of the silicon substrate 31 at the bottom of the groove 45 by, for example, a low temperature epitaxial technique using a mixed gas of dichlorosilane and hydrogen chloride. Selectively grow. The surface of the epitaxial silicon layer 47 is set slightly higher than the surface of the silicon substrate 31 or substantially at the same position.

  Next, as shown in FIG. 18F, the silicon oxide film 46 is removed by wet etching using a hydrofluoric acid based solution. As a result, a very narrow groove 48 is formed between the epitaxial silicon layer 47 and the silicon substrate 31.

  Next, as shown in FIG. 19G, by performing high-temperature annealing in a non-oxidizing atmosphere under reduced pressure, for example, a 100% hydrogen atmosphere of 10 Torr and 1000 ° C., the groove 48 is formed as in the first embodiment. A cavity 40 is formed in the silicon substrate 31 by closing the opening.

  In this step, the epitaxial silicon layer 47 and the silicon substrate 31 are not distinguished from each other. Therefore, the portion of the epitaxial silicon layer 47 is also referred to as the silicon substrate 31 hereinafter.

  Next, as shown in FIG. 19H, the surface of the silicon substrate 31 at the bottom of the groove 45 is thermally oxidized to form a gate insulating film 35 on the surface of the silicon substrate 31. The thermal oxidation is performed, for example, at 900 ° C. in a mixed gas atmosphere of oxygen and HCl. At this time, a small part of the oxidizing agent diffuses in the silicon substrate 31 and the inner surface of the cavity 40 is simultaneously oxidized. As a result, a thermal oxide film 41 is also formed on the inner surface of the cavity 39.

  Next, as shown in FIG. 19I, a gate electrode 36 is formed inside the trench 45. Such a gate electrode 36 is formed by depositing a polycrystalline silicon film, a stacked film of a polycrystalline silicon film and a metal silicide film, or a metal film on the entire surface so as to fill the inside of the groove 45, and It can be formed by removing unnecessary films by CMP.

  Here, the end of the gate electrode 36 is in contact with the side wall of the groove 45, and the cavity 40 is located under the side wall of the groove 45. Therefore, the gate electrode 36 is formed so that the end thereof is positioned on the cavity 40, and the positional displacement between the gate electrode 36 and the cavity 40 does not occur. Further, the depth of the cavity 40 can be optimized by appropriately selecting the depth of the groove 48, and the size of the cavity 40 can be optimized by appropriately selecting the film thickness of the silicon oxide film 46.

Next, as shown in FIG. 20J, the silicon nitride film 43 and the silicon oxide film 42 are removed. The silicon nitride film 43 is removed using a heated H ₃ PO ₄ solution. Next, as shown in FIG. 6 (j), impurity ions are implanted into the silicon substrate 31 using the gate electrode 36 as a mask, and then annealing for activating the impurity ions is performed to form the source diffusion layer 38a and the drain. A diffusion layer 39a is formed.

  Finally, as shown in FIG. 20 (k), a gate sidewall insulating film 37 is formed, and impurity ions are implanted into the silicon substrate 31 using the gate sidewall insulating film 37 and the gate electrode 36 as a mask. The source diffusion layer 37b and the drain diffusion layer 38b are formed by annealing for activating the MOS transistor, and the MOS transistor shown in FIG. 16 is completed.

  Note that the annealing in the step of FIG. 20 (j) may be omitted, and the activation of impurity ions may be performed collectively by annealing in the step of FIG. 20 (k).

(Fifth embodiment)
21A and 21B are a plan view and a sectional view of a MOS transistor according to the fifth embodiment of the present invention, in which FIG. 21A is a plan view and FIG. 21B is an arrow LL in the plan view. 'Cross-sectional view, (c) shows an WW' cross-sectional view of the plan view.

  The difference of this embodiment from the first embodiment is the shape of the cavity 40a and its position. The shape of the cavity 40a is cylindrical, and both end surfaces (the upper surface and the lower surface of the cylinder) of the cavity a are in contact with the silicon oxide film 34 as an element isolation insulating film. In the cross section of the cavity 40a in the gate width direction, as shown in FIG. 21C, the distance X between the gate insulating film 35 and the cavity 40a is constant.

  In a conventional fine MOS transistor having a gate length of 0.2 μm or less, as shown in FIG. 22, the depletion layers 49 are in contact with each other in a region where the influence of the potential of the gate electrode 36 is small (a region away from the gate electrode 36). Therefore, the drain current 50b flows not only in the vicinity of the gate insulating film 35 where the drain current 50a should originally flow, but also in a location far from the gate insulating film 35. The drain current 50b is a current that does not depend on the gate voltage, and causes a short channel effect.

In order to suppress the spread of the depletion layer 49, there is a method of increasing the impurity concentration of the source diffusion layer and the drain diffusion layer. However, in a fine element having a gate length of 0.2 μm or less, the impurity concentration of the source diffusion layer and the drain diffusion layer is approaching 1 × 10 ¹⁸ cm ⁻³ , and if the impurity concentration is further increased, other problems are caused. cause. For example, it causes problems such as an increase in junction leakage current and an increase in junction capacitance in the source diffusion layer and the drain diffusion layer.

  However, according to the present embodiment, since the path of the drain current independent of the gate voltage is divided by the cavity 40a, the drain current independent of the gate voltage does not flow between the source and the drain. As a result, even if the impurity concentration of the source diffusion layer and the drain diffusion layer is not increased, as shown in FIG. 23, the short channel effect (SCE) is shorter than that of the conventional MOS transistor without the cavity 40a. It is suppressed.

  Here, according to the study by the present inventors, it was found that the effect of suppressing the short channel effect by the cavity 40a varies depending on the position of the cavity 40a. This will be described below.

FIG. 24 is a characteristic diagram showing the relationship between the gate length Lg and the threshold voltage _Vth for a MOS transistor having an LDD structure and having a cavity 40a. The degree of deterioration of the device characteristics due to the short channel effect at a certain short gate length Lg _{depends on} the threshold voltage V _{thL at} the long channel (gate length Lg >> 1 μm) and the threshold voltage V _{th0 at the} gate length Lg0. ΔV _th (= V _thL −V _th0 ). The larger the ΔV _th is, the greater the degree of deterioration of device characteristics due to the short channel effect.

FIG. 25 is a characteristic diagram showing the relationship between the threshold voltage decrease amount ΔV _th , the gate length Lg, and the cavity-gate insulating film distance X. From the figure, it can be seen that the shorter the cavity-gate insulating film distance X is, that is, the closer the cavity 40a is to the gate insulating film 35, the greater the effect of suppressing the short channel effect by the cavity 40a.

  However, the closer the cavity 40a is to the gate insulating film 35, the better. This is because, as shown in FIG. 23, the cavity 40a also has a function of reducing the driving force of the element.

  FIG. 26 is a characteristic diagram showing the relationship between Idsat (with a cavity) / Idsat (without a cavity) and the distance X between the cavity and the gate insulating film. From the figure, the tendency of the driving force to decrease is sharply increased when the distance X between the cavity and the gate insulating film is shorter than the distance of 0.1 times the gate length Lg.

  Therefore, by setting 0.1Lg <X, the short channel effect can be effectively suppressed without reducing the driving force. The upper limit of the distance X between the cavity and the gate insulating film is, for example, Lg.

Further, according to the study by the present inventors, it was found that the threshold voltage _Vth can be controlled by the cavity-gate insulating film distance X as shown in FIG. That is, it became clear that the threshold voltage can be lowered by shortening the distance X between the cavity and the gate insulating film.

  By utilizing such a phenomenon, it is difficult to adjust the threshold voltage to a low level when the gate electrode of a fine MOS transistor having a gate length of 0.2 μm or less is formed of metal. It becomes possible to solve the problem.

  FIG. 28 is a process sectional view showing the method for forming the MOS transistor of this embodiment. This shows a cross section in the direction of the arrow A-A 'in FIG.

  First, as shown in FIG. 28A, a groove 45 is formed on the surface of the silicon substrate 31. The planar pattern of the groove 45 is a rectangle whose long side extends in the channel width direction.

  Next, as shown in FIG. 28B, as in the first embodiment, the high temperature annealing is performed in a non-oxidizing atmosphere under reduced pressure, for example, a 100% hydrogen atmosphere at 10 Torr and 1000 ° C., thereby forming the groove 45. The cavity 40a is formed in the silicon substrate 31 by closing the opening. In the case of this embodiment, the shape of the cavity 40a is cylindrical.

  Next, as shown in FIG. 28C, an element isolation trench 32 is formed on the surface of the silicon substrate 31, and the inside thereof is filled with a silicon oxide film 34 as an element isolation insulating film. At this time, the element isolation trench 32 is formed so as to cut off both ends (the upper and lower surfaces of the cylinder) of the cavity 40 a, and both ends of the remaining cavity 40 a are in contact with the silicon oxide film 34. FIG. 29A shows a plan view at this stage, and FIG. 29B shows a cross-sectional view taken along the line W-W ′ of the plan view.

  Next, as shown in FIG. 28D, after the surface of the substrate is oxidized to form a gate insulating film 35, a polycrystalline silicon film is deposited on the gate insulating film 35, and this polycrystalline silicon film is patterned. Thus, the gate electrode 36 is formed. The polycrystalline silicon film is patterned so that the gate electrode 36 is located immediately above the cavity 40a. Such patterning is possible, for example, by using the alignment method shown in FIGS.

  Thereafter, similarly to the fourth embodiment, the gate sidewall insulating film 37, the source diffusion layer 38, and the drain diffusion layer 39 are formed, and the MOS transistor having the LDD structure shown in FIG. 21 is completed.

(Sixth embodiment)
FIG. 30 is a sectional view showing a MOS transistor according to the sixth embodiment of the present invention. FIG. 21A is a cross-sectional view corresponding to FIG. 21B, and FIG. 21B is a cross-sectional view corresponding to FIG.

  This embodiment differs from the fifth embodiment in that the distance between the cavity 40b and the gate insulating film 35 (the distance X ′ between the cavity and the gate insulating film) is periodically changed in the gate width direction. There is to be. As described above, even when the cavity-gate insulating film distance X ′ changes periodically, the short channel effect can be effectively suppressed as in the fifth embodiment.

In the case of this embodiment, it is preferable that both the maximum value X ′ _max and the minimum value X ′ _{min of the} distance X ′ between the cavity and the gate insulating film are set to values larger than 0.1 Lg. The upper limit of X _'max, X' _min is likewise e.g. L _G in the fifth embodiment.

  In order to form such a MOS transistor, instead of forming one groove 45 in the step of FIG. 28A of the fifth embodiment, as shown in FIG. A plurality of grooves 45b are formed along the line. The planar pattern (opening pattern) of these grooves 45b may be square, rectangular, or circular. Further, the interval between the grooves 45b is shortened.

  Next, as shown in FIG. 31B, high-temperature annealing is performed in a non-oxidizing atmosphere under reduced pressure to form a cavity 40b having a shape in which spheres are connected. The reason for this shape is that, due to the high temperature annealing, each groove 45b closes its opening to form a spherical cavity, and since the gap between the grooves 45b is short, adjacent spherical cavities are joined together.

  The subsequent steps are the same as the steps after FIG. 28C of the fifth embodiment. However, in the case of the present embodiment, the element isolation trench 32 is formed so as to cut off both ends of the cavity 40b formed by overlapping the spheres, and both ends of the remaining cavity 40b are in contact with the silicon oxide film 34.

(Seventh embodiment)
32A and 32B are a plan view and a cross-sectional view of a MOS transistor according to the seventh embodiment of the present invention, where FIG. 32A is a plan view and FIG. 32B is a view LL of the plan view. 'Cross sectional view, (c) shows an WW sectional view of the plan view.

  In the figure, reference numeral 51 denotes a silicon substrate, and a groove 52 is formed on the surface of the silicon substrate 51. The region where the groove 52 is formed is used as an element isolation region as usual and also as a back gate region. The inner surface of the groove 52 is covered with a thermal oxide film 53. The inside of the trench 52 is filled with a silicon oxide film 55 via a polycrystalline silicon film 54.

  A gate electrode 58 is formed on the silicon substrate 51 in the MOS transistor region 56 via a first gate insulating film 57. The gate electrode 58 is made of a polycrystalline silicon film, a laminated film of a polycrystalline silicon film and a metal silicide film, or a metal film. A gate sidewall insulating film 59 is formed on the sidewall of the gate electrode 58. A source diffusion layer 60 and a drain diffusion layer 61 having an LDD structure are formed on the surface of the silicon substrate 51.

A cylindrical back gate electrode _54BG extending in the channel width direction is embedded in the silicon substrate 51 below the channel region of the MOS transistor. The back gate electrode _54BG and the polycrystalline silicon film 54 are the same polycrystalline silicon film formed in the same process.

In MOS transistor region 56 is formed a second gate insulating film 53 _G at the interface between the back gate electrode 54 _BG and the silicon substrate 51. The second gate insulating film 53 _G and the thermal oxide film 53 are the same thermal oxide film made in the same process.

An interlayer insulating film 62 is deposited on the MOS transistor, and metal wirings 63 to 66 are formed on the interlayer insulating film 62. These metal wirings 63 to 66 are connected to source diffusion layers through connection holes 67 to 70, respectively. 60, the drain diffusion layer 61, the back gate electrode _{54BG, and the} gate electrode 58 are electrically connected.

According to the present embodiment, by applying an appropriate voltage to the back gate electrode _54BG , it becomes possible to suppress the spread of the depletion eyebrows in the channel region, and the ON / OFF characteristics of the transistor are improved. Therefore, according to the present embodiment, it is possible to effectively suppress the short channel effect even if the MOS transistor is further miniaturized in order to further increase the distance and the degree of integration of the integrated circuit.

  Further, according to the present embodiment, unlike the case where the pack gate electrode is formed using the SOI substrate, the region where the MOS transistor is formed on the silicon substrate 51 is not insulated from the other portions of the silicon substrate 51. . Therefore, problems such as a substrate floating effect do not occur, and a stable element operation can be obtained. Further, since it is not necessary to use an SOI substrate which is an expensive substrate, there is naturally no problem of an increase in cost.

  Next, a method for manufacturing the MOS transistor of this embodiment will be described. 33 to 36 are process cross-sectional views illustrating the forming method. The left side of each figure shows a cross-sectional view parallel to the channel length direction, and the right side shows a cross-sectional view parallel to the channel width direction.

  First, as shown in FIG. 33A, an oxide film 71 is formed on the silicon substrate 51.

  Next, as shown in FIG. 33B, after a photoresist pattern 72 is formed on the oxide film 71, the oxide film 71 and the silicon substrate are formed by anisotropic etching such as RIE using the photoresist pattern 72 as a mask. 51 is patterned to form a groove 73 in the silicon substrate 51. Thereafter, the photoresist pattern 72 is ashed and peeled off.

  Next, as shown in FIG. 33C, high-temperature annealing is performed in a non-oxidizing atmosphere under reduced pressure, for example, 100% hydrogen atmosphere at 10 Torr and 1000 ° C., thereby closing the opening of the groove 73 and the silicon substrate. A cavity 74 is formed in 51.

  Next, as shown in FIG. 33D, after removing the oxide film 71 using a dilute HF solution, high-temperature annealing is performed again in a non-oxidizing atmosphere under reduced pressure, for example, in a 100% hydrogen atmosphere at 10 Torr and 1000 ° C. As a result, the surface of the silicon substrate 51 is planarized.

Next, as shown in FIG. 34E, the surface of the silicon substrate 51 is thermally oxidized to form a thermal oxide film 75, and then a silicon nitride film 76 is formed on the thermal oxide film 75 using the CVD method. As shown in FIG. 34F, after a photoresist pattern 77 is formed on the silicon nitride film 76, the silicon nitride film 76, the thermal oxide film 75, and the silicon substrate 51 are different from each other using the photoresist pattern 77 as a mask. The groove 52 is formed by isotropic etching. At this time, the end of the cavity 74 formed in the silicon substrate 51 in the channel width direction is connected to the groove 52. Thereafter, the photoresist pattern 77 is ashed and peeled off.

Next, as shown in FIG. 34 (g), 950 ℃, by thermally oxidizing the surface of the groove 52 in HCl / 0 ₂ atmosphere to form a thermal oxide film 53. At this time, the inner surface of the cavity 74 is also oxidized simultaneously, so that the second gate insulating film 53 _G is formed on the inner surface of the cavity 74.

Next, as shown in FIG. 34 (h), the polysilicon film to which impurities as the back gate electrode _54BG and the polycrystalline silicon film 54 are added by using the LPCVD method is buried in the cavity 74 and the trench 52. After the deposition on the entire surface, unnecessary polycrystalline silicon films as the back gate electrode _54BG and the polycrystalline silicon film 54 are removed. The removal of the polycrystalline silicon film is performed by, for example, etch back that combines CMP and anisotropic etching.

  Next, as shown in FIG. 35I, after a silicon oxide film 55 is deposited on the entire surface by using the CVD method, the silicon oxide film 55 is polished by using the CMP method until the surface of the silicon nitride film 76 is exposed. As a result, the inside of the trench 52 is filled with the silicon oxide film 55.

Next, as shown in FIG. 35J, the silicon nitride film 76 is removed using a heated H ₃ P0 ₃ solution. At this time, the silicon oxide film 55 and the thermal oxide film 53 on the upper portion of the groove 52 are somewhat removed, and the surface of the silicon substrate 51 on the upper edge portion of the groove 52 is exposed.

  Next, as shown in FIG. 35 (k), by oxidizing the exposed surface of the silicon substrate 51 to form a thermal oxide film 78 having a thickness of, for example, 1 nm, the threshold voltage is adjusted. Necessary p-type or n-type impurities are introduced into the silicon substrate 51 through the thermal oxide film 78 by ion implantation.

Next, as shown in FIG. 35L, after removing the thermal oxide film 78 using a dilute HF solution, the substrate surface exposed in, for example, 900 ° C. and HCl / ₂ atmosphere is thermally oxidized. A first gate insulating film 57 is formed.

  At this time, since the first gate insulating film 57 is formed not only on the MOS transistor formation region but also on the upper edge portion of the trench 52, there is no exposed silicon surface.

  Thereafter, the process is the same as that of a known MOS transistor. First, as shown in FIG. 36 (m), a polycrystalline silicon film to be a gate electrode 58 is formed on the entire surface, and then this polycrystalline silicon film is patterned. Thus, the gate electrode 58 is formed.

  Here, a polysilicon gate structure is employed as the structure of the gate electrode 58, but other structures such as a polymetal gate structure composed of a polycrystalline silicon film / metal film laminated film and a metal gate structure are employed. Also good.

  Next, as shown in FIG. 36 (n), a gate sidewall insulating film 59, an LDD structure source diffusion layer 60, and a drain diffusion layer 61 are formed.

  Finally, an interlayer insulating film 62 is deposited on the entire surface, connection holes 67 to 70 are opened in the interlayer insulating film 62 using lithography and anisotropic etching, and wirings 63 to 66 are formed, so that the MOS shown in FIG. A transistor is completed.

(Eighth embodiment)
In the present embodiment, the improvement of the method for forming the cavity of the MOS transistor described above will be described. In order to form a cavity in a silicon substrate, a high temperature and long time heat treatment is required. If the aspect ratio of the groove to be a cavity is as small as about 3, the substrate surface can be flattened by heat treatment, but it becomes difficult to form the cavity.

  In the present embodiment, a method for forming a cavity that eliminates the above-described disadvantages will be described. The cavity forming method of this embodiment can be applied to any of the MOS transistors of the first to seventh embodiments.

  First, as shown in FIG. 37A, a mask pattern 82 is formed on a silicon substrate 81, the silicon substrate 81 is patterned by anisotropic etching such as RIE using the mask pattern 82 as a mask, and grooves are formed. 83 is formed.

  Here, the mask pattern 82 is formed, for example, by patterning a silicon oxide film using a photoresist. The groove 83 has an opening diameter of 0.4 μm and a depth of 1.2 μm.

  Next, as shown in FIG. 37B, after removing the mask pattern 82 and removing the natural oxide film on the surface of the silicon substrate 81, an epitaxial SiGe film 84 having a thickness of 50 nm and a Ge content of 15% is obtained by an epitaxial growth method. Is formed on the entire surface. As a result, the inner surface of the groove 83 is formed of SiGe.

  Finally, as shown in FIG. 37C, heat treatment is performed in a 100% hydrogen atmosphere at 1000 ° C. and 10 Torr to form a cavity 85 in the silicon substrate 81. At this time, Ge in the epitaxial SiGe film 84 diffuses into the silicon substrate 81, and the epitaxial SiGe film 84 disappears. Although heat treatment at 1100 ° C. is performed here, heat treatment at 950 ° C. may be used. That is, the cavity 85 can be formed even by heat treatment at a lower temperature than in the case of a pure silicon substrate without Ge.

  Further, the present inventors tried to form the cavity 85 by the same method as that described above except that the epitaxial SiGe film 84 was not formed. However, although the surface of the silicon substrate 51 became flat, the cavity 85 Was not formed.

  From the above results, when the silicon substrate 81 having the groove 83 having the same aspect ratio is subjected to the heat treatment under the same conditions and the epitaxial SiGe film 84 is deposited on the silicon substrate 81, the cavity 85 can be formed. It has been clarified that the cavity 85 cannot be formed when the epitaxial SiGe film 84 is not deposited on 81.

  When the inner surface of the groove 83 is formed of SiGe having a melting point lower than that of silicon, the cavity 85 can be formed in the silicon substrate 81 at a lower temperature even if the groove 83 having an aspect ratio of 3 is formed in the silicon substrate 81. This is probably because migration occurs on the inner surface of the groove 83.

  FIG. 38 shows micrographs before and after the heat treatment of the trench in which the epitaxial SiGe film is not formed on the inner wall. FIG. 39 shows micrographs before and after the heat treatment of the trench in which the epitaxial SiGe film is formed on the inner wall. Each figure (a) shows before heat treatment, and each figure (b) shows after heat treatment. The film thickness of the epitaxial SiGe film is 200 nm, the heat treatment temperature is 1100 ° C., the pressure is 380 Torr, and the heat treatment time is 10 minutes. From these figures, it can be seen that when the epitaxial SiGe film is formed on the inner wall, the shape of the trench is greatly deformed by the heat treatment.

  FIG. 40 shows the dependency of the melting point of SiGe on the Si concentration. From the figure, it can be seen that the melting point of SiGe decreases as the amount of Ge increases, depending on the melting point of Si and the melting point of Ge.

  Therefore, the same effect as that obtained by using the epitaxial SiGe film 84 can be obtained by using an epitaxial SiGe film containing more Ge or an Ge epitaxial film instead of using the epitaxial SiGe film 84 having a Ge content of 15%. It is done.

  However, the Ge content is preferably 40% or less in order to reliably deform the groove to form a cavity. In order to form a cavity having a smooth inner surface by deforming the groove, it is preferably 20% or less, more preferably 10% or less.

  As described above, according to the present embodiment, by using the epitaxial SiGe film 84 having a low melting point, the groove 83 can be deformed at a lower temperature and in a shorter time, and the cavity 85 can be easily formed. . Further, the cavity 85 can be formed in the silicon substrate 81 even when the groove 83 having a small aspect ratio of 3 is used. In addition, the present inventors have confirmed that a cavity can be formed in a silicon substrate even when a groove having an aspect ratio of 1 and smaller is used.

(Ninth embodiment)
Also in this embodiment, the improvement of the method for forming the cavity of the MOS transistor described above will be described.

  The substrate surface on the cavity needs to be flat because it is a region for forming an element. As one method for flattening the element region on the cavity, it is conceivable to heat-treat the silicon substrate in a high temperature / non-oxidizing atmosphere after the cavity is formed.

  However, in this method, depending on the heat treatment conditions, the cavity may be deformed, reduced, or eliminated, and as a result, there is a possibility that the effect of suppressing the short channel effect due to the cavity cannot be obtained.

  In the present embodiment, a method for forming a cavity that eliminates the above-described disadvantages will be described. The cavity forming method of this embodiment can be applied to any of the MOS transistors of the first to seventh embodiments.

  First, as shown in FIG. 41A, as in the eighth embodiment, a mask pattern 92 is formed on a silicon substrate 91, and the silicon substrate 91 is subjected to anisotropic etching using the mask pattern 92 as a mask. Is patterned to form a groove 93.

  Next, as shown in FIG. 41B, the opening of the groove 93 is closed by performing high-temperature heat treatment for 10 minutes in a non-oxidizing atmosphere under reduced pressure, for example, 1100 ° C. and 100% hydrogen atmosphere at 10 Torr. A cavity 94 is formed. At this time, a depression 95 is formed on the surface of the silicon substrate 91 on the cavity 94, and the surface is not flat. Thereafter, the mask pattern 92 is removed using, for example, an aqueous hydrogen fluoride solution.

  Next, as shown in FIG. 41 (c), the silicon oxide film 96 is formed on the surface of the silicon substrate 91 and the inner surface of the cavity 94 by performing oxidation treatment in an oxidizing atmosphere, for example, a dry oxygen atmosphere at 1100 ° C. for 1 hour. Form. The silicon oxide film 96 formed on the inner surface of the cavity 94 has a role of preventing the deformation, reduction and disappearance of the cavity 94 in the subsequent thermal process.

  Finally, as shown in FIG. 41 (d), after the silicon oxide film 96 on the surface of the silicon substrate 91 is removed using an aqueous hydrogen fluoride solution, the cavity 94 is formed by heat treatment in a high-temperature, non-oxidizing atmosphere. The dent 95 generated at the time is eliminated, and the substrate surface is flattened. At this time, neither deformation, reduction, or disappearance of the cavity 94 occurs.

  As described above, according to the present embodiment, the cavity 94 is formed by forming the silicon oxide film 96 on the inner surface of the cavity 94 before performing the heat treatment for eliminating the depression 95 generated when the cavity 94 is formed. The substrate surface can be flattened without causing deformation, reduction and disappearance of the substrate.

(Tenth embodiment)
FIG. 42 is a process sectional view showing the method for forming the cavity of the MOS transistor according to the tenth embodiment of the invention. Note that portions corresponding to those in FIG. 37 are denoted by the same reference numerals as in FIG.

  First, as shown in FIG. 42A, a mask pattern 82 is formed on a silicon substrate 81, and, similar to the ninth embodiment, the silicon substrate 81 is formed by anisotropic etching using the mask pattern 82 as a mask. The groove 83 is formed by patterning. The groove 83 has an opening diameter of 0.4 μm and a depth of 1.2 μm.

  Next, as shown in FIG. 42B, after removing a natural oxide film (not shown) formed on the inner surface of the groove 83, an epitaxial SiGe film 84 is selectively formed on the inner surface of the groove 83 by an epitaxial growth method. To do. Thereafter, the mask pattern 82 is removed.

  Finally, as shown in FIG. 42C, the cavity 85 is formed by performing high-temperature heat treatment in a 100% hydrogen atmosphere at 1000 ° C. and 10 Torr for 10 minutes.

  As described above, according to the present embodiment, the flatness of the upper surface of the silicon substrate 81 is lost by performing epitaxial growth of SiGe with the substrate surface in a region other than the groove 85 covered with the mask pattern 82. Instead, the cavity 85 can be formed in the silicon substrate 81.

  Incidentally, after the step of FIG. 42C, an epitaxial Si film 86 may be formed on the substrate surface as shown in FIG. This epitaxial Si film 86 does not substantially contain Ge. For this reason, when the transistor is formed using the epitaxial film 86, it is not necessary to consider the influence of Ge at the channel interface, so that the transistor can be easily designed.

  Next, the flow phenomenon of the SiGe film 84 will be described with reference to FIG.

  First, as shown in FIG. 43A, a SiGe film 84 was selectively formed on the inner surface of the groove 83. The groove 85 has a diameter of 1.6 μm and a depth of 6 μm. The SiGe film 84 has a Ge content of 15% and a film thickness of 100 nm.

  Next, heat treatment was performed in a 100% hydrogen atmosphere at 1100 ° C. and 1 Torr. As a result, as shown in FIG. 43B, the SiGe film 84 having a melting point lower than that of the silicon substrate 81 flowed first. As a result, the shape of the groove 83 has changed significantly.

  Thereafter, the silicon substrate 81 and the SiGe film 84 on the side and bottom surfaces of the groove 83 are driven by the driving force that the silicon substrate 81 below the groove 83 tries to deform into a shape with a small surface energy (in this case, a sphere). As a result, the cavity 85 was formed in the silicon substrate 81 as shown in FIG.

  In FIG. 43 (c), the original groove 8 having a diameter of 1.6 μm is indicated by a dotted line. It can be seen from FIG. 43 (c) that silicon also flows greatly when the cavity 85 is formed.

  FIG. 44 is a cross-sectional view showing the shape of the groove after the heat treatment is performed on the silicon substrate 81 having the groove without forming the SiGe film. In the figure, 83 indicates a groove before heat treatment, and 83a indicates a groove after heat treatment. The dimensions of the groove 83 and the heat treatment conditions are the same as in FIG.

  From the figure, it can be seen that the groove deforms even under the same heat treatment, but no cavity is formed. This is considered to be because the easiness of silicon flow varies depending on the groove shape even under the same heat treatment.

  In the case of FIG. 43, the shape of the groove 83 changes greatly due to the flow of the SiGe film 84, but in the case of FIG. 44, the shape of the groove 83 hardly changes because there is no SiGe film 84. When the change in the shape of the groove is large, the driving force for deforming the silicon substrate also increases, and the flow of silicon easily occurs.

  Therefore, in the case of FIG. 43, a large driving force can be obtained and a cavity can be formed. In the case of FIG. 44, only a small driving force can be obtained, so that it is considered that a cavity cannot be formed. From the above, it can be said that it is preferable to increase the thickness of the SiGe film and increase the deformation of the groove in order to easily form the cavity.

  Next, the result of examining the cavity formed in the silicon substrate in detail with an atomic force microscope (AFM) will be described.

  Here, after forming a groove in the silicon substrate, a cavity was formed by heat treatment in a hydrogen atmosphere at 1100 ° C. and 10 Torr for 10 minutes. In this way, the natural oxide film on the surface of the silicon substrate is removed by the heat treatment in a high temperature / non-oxidizing atmosphere, and when silicon is exposed, the silicon atoms are exposed on the surface of the silicon substrate so that the surface energy of the silicon substrate is minimized. To diffuse. As a result, a cavity is formed in the silicon substrate.

FIG. 45 shows a photomicrograph which is the result of analyzing the cavity formed in this way by AFM. It can be seen from the figure that the inner surface of the cavity is formed of a polyhedron. Furthermore, the following was found by examining the angle formed by the plane orientation of the faces constituting the polyhedron with the (100) plane which is the main surface of the silicon substrate. That is, the faces constituting the polyhedron are composed of {100} plane group, {110} plane group, {111} plane group, {311} plane group, {531} plane group, and {541} plane group. Became clear. Since these surface groups have low surface energy, it can be said that the cavity is thermally stable. Also, when using the above cavities in the back-gate structure as in the seventh embodiment, the interface state between the back gate electrode 54 _BG and the gate insulating film 53 _G is reduced, resulting excellent electrical properties .

  The present invention is not limited to the above embodiment. For example, in the above-described embodiment, the case of a MOS transistor has been described. However, the present invention is not limited to this, and the present invention can also be applied to other field effect transistors such as MESFET. Furthermore, a MOS transistor having a double gate structure (for example, a floating gate / control gate) may be used.

  In the above embodiment, the extension of the depletion layer from the source and drain is stopped by forming a region filled with air (cavity) and a region filled with insulating film (solid) under the MOS transistor formation region. Thus, the short channel effect is suppressed, but the short channel effect may be suppressed by forming a region filled with liquid under the MOS transistor formation region.

  In addition, the extension of the depletion layer can be stopped by forming a semiconductor layer made of a semiconductor material having a band gap larger than that of the constituent material of the semiconductor substrate instead of the cavity or the insulating film.

  In this case, for example, a groove is formed on the surface of the substrate, a semiconductor layer having a large band gap is formed at the bottom of the groove, and a semiconductor layer made of a constituent element of the semiconductor substrate is formed thereon to fill the groove. . The semiconductor material to be used is selected in consideration of device specifications such as element dimensions and power supply voltage.

  The MOS transistor described in the above embodiment is used for a memory cell of a DRAM, for example. When the present invention is applied to a MOS transistor having a double gate structure, the MOS transistor is used, for example, in an EEPROM memory cell.

  The channel type of the MOS transistor described in the above embodiment may be either n-channel or p-channel. In the case of n-channel, n-type impurities such as As are ion-implanted into the silicon substrate, and the n-type source diffusion layer and An n-type drain diffusion layer is formed. In the case where the gate electrode is formed of a polycrystalline silicon film, n-type impurities are also introduced into the polycrystalline silicon film.

  Further, the MOS transistor described in the above embodiment may be formed in a well layer formed on the surface of a silicon substrate. For example, in the case of a CMOS, at least one of an n-channel and a p-channel MOS transistor is formed in the well layer.

  The substrate may be a substrate other than a silicon substrate, for example, a SiGe substrate. Further, if a partially depleted MOS transistor is formed, an SOI substrate may be used. However, in this case, problems such as cost increase due to the SOI substrate remain.

  In addition, various modifications can be made without departing from the scope of the present invention.

The top view and sectional drawing which show the MOS transistor which concerns on the 1st Embodiment of this invention Process sectional drawing which shows the first half of the formation method of the MOS transistor of FIG. Process sectional drawing which shows the middle half of the formation method of the MOS transistor of FIG. Process sectional drawing which shows the latter half of the formation method of the MOS transistor of FIG. Cross-sectional view showing differences in how cavities are created due to differences in groove aspect ratio Process cross-sectional view for explaining the control method of the shape and size of the cavity Plan view and sectional view for explaining a method of forming a rod-shaped cavity FIG. 6 is a plan view and a sectional view showing a MOS transistor using the cavity shown in FIG. FIG. 1 is a plan view and a cross-sectional view showing a modification of the MOS transistor of FIG. Process sectional drawing which shows the formation method of the MOS transistor of FIG. Cross-sectional process chart for explaining the method for aligning cavities Process sectional drawing for demonstrating the other alignment method of a cavity The top view and sectional drawing which show the MOS transistor which concerns on the 2nd Embodiment of this invention Cross-sectional process drawing showing the method of forming the MOS transistor Process sectional drawing which shows the formation method of the MOS transistor which concerns on the 3rd Embodiment of this invention The top view and sectional drawing which show the MOS transistor which concerns on the 4th Embodiment of this invention Cross-sectional process drawing showing the method of forming the MOS transistor Process sectional drawing which shows the formation method of the MOS transistor following FIG. Process sectional drawing which shows the formation method of the same MOS transistor following FIG. Process sectional drawing which shows the formation method of the same MOS transistor following FIG. The top view and sectional drawing which show the MOS transistor which concerns on the 5th Embodiment of this invention Sectional drawing for demonstrating the problem of the conventional fine MOS transistor whose gate length is 0.2 micrometer or less Vg-Id characteristic diagram for explaining the effect of the MOS transistor of FIG. Characteristic diagram showing relationship between gate length Lg and threshold voltage for MOS transistor having cavity with LDD structure Characteristic diagram showing the relationship between threshold voltage drop, gate length, and distance between cavity and gate insulating film for the MOS transistor Characteristic diagram showing the relationship between Idsat (with cavities) / Idsat (without cavities) and the distance between the cavity and the gate insulating film Characteristic diagram showing the relationship between the distance between the cavity and the gate insulating film and the threshold voltage Process sectional drawing which shows the formation method of the MOS transistor of FIG. Plan view and sectional view in the middle of formation of the MOS transistor Sectional drawing which shows the MOS transistor which concerns on the 6th Embodiment of this invention Cross-sectional process drawing showing the method of forming the MOS transistor The top view and sectional drawing which show the MOS transistor which concerns on the 7th Embodiment of this invention Cross-sectional process drawing showing the method of forming the MOS transistor Process sectional drawing which shows the formation method of the same MOS transistor following FIG. Process sectional drawing which shows the formation method of the MOS transistor following FIG. Process sectional drawing which shows the formation method of the same MOS transistor following FIG. Process sectional drawing which shows the formation method of the cavity of the MOS transistor which concerns on the 8th Embodiment of this invention Photomicrograph showing the shape of the trench without an epitaxial SiGe film on the inner wall before and after heat treatment Photomicrograph showing the shape of the trench with the epitaxial SiGe film on the inner wall before and after heat treatment The figure which shows the dependence of Si melting | fusing point of SiGe concentration Process sectional drawing which shows the formation method of the cavity of the MOS transistor based on the 9th Embodiment of this invention Process sectional drawing which shows the formation method of the cavity of the MOS transistor which concerns on the 10th Embodiment of this invention The figure for explaining the flow phenomenon of the SiGe film formed on the inner wall of the trench Sectional drawing which shows the shape of a trench at the time of performing heat processing without forming a SiGe film Photomicrograph showing the inner wall of a cavity observed with an atomic microscope

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Element isolation groove, 3, 10, 13, 16 ... Thermal oxide film, 4 ... Silicon oxide film, 5 ... Gate insulating film, 6 ... Gate electrode, 7 ... Source diffusion layer, 8 ... Drain diffusion Layer, 9 ... cavity, 9s ... space, 11 ... photoresist pattern, 12, 12a, 12 '... groove, 14 ... silicon nitride film, 15 ... photoresist pattern, 17 ... impurity ions, 18 ... MOS transistor formation region, 19 ... Insulating film mask, 19a ... Mark, 20, 22 ... Amorphous silicon film, 21 ... Insulating film (insulator), 31 ... Silicon substrate, 32 ... Element isolation trench, 33, 41 ... Thermal oxide film, 34, 42, 46 ... Silicon oxide film, 35 ... Gate insulating film, 36 ... Gate electrode, 37 ... Gate sidewall insulating film, 38 ... Source diffusion layer, 39 ... Drain layer, 40, 40a, 40b ... Cavity, 43 ... Recon nitride film, 44 ... photoresist pattern, 45, 45b, 48 ... groove, 47 ... epitaxial silicon layer, 51 ... silicon substrate, 52 ... groove,
53 ... Thermal oxide film, 54 ... Polycrystalline silicon film, _54BG ... Back gate electrode, 55 ... Silicon oxide film, 56 ... MOS transistor region, 57 ... Gate insulating film, 58 ... Gate electrode, 59 ... Gate sidewall insulating film, 60 ... Source diffusion layer, 61 ... Drain layer, 62 ... Interlayer insulating film, 63-66 ... Metal wiring, 67-70 ... Connection hole, 71 ... Oxide film, 72 ... Photoresist pattern, 73 ... Groove, 74 ... Cavity, 75 ... Thermal oxide film, 76 ... Silicon nitride film, 77 ... Photoresist pattern, 78 ... Thermal oxide film, 81 ... Silicon substrate, 82 ... Mask pattern, 83 ... Groove, 84 ... Epitaxial SiGe film, 85 ... Cavity, 91 ... Silicon substrate, 92 ... mask pattern, 93 ... groove, 94 ... cavity, 95 ... depression, 96 ... silicon oxide film

Claims (9)

A semiconductor substrate;
A field effect transistor formed on the semiconductor substrate;
A semiconductor layer formed in the semiconductor substrate under the field effect transistor formation region and different from a semiconductor element constituting the semiconductor substrate and suppressing an extension of a depletion layer under the field effect transistor formation region; A semiconductor device comprising: A semiconductor substrate;
A field effect transistor formed on a flat portion of the semiconductor substrate;
The field effect transistor is formed in the semiconductor substrate under the source region and the drain region, and the dimension of the field effect transistor in the channel width direction is larger than the dimension of the field effect transistor formation region in the channel width direction. A semiconductor device comprising: a large insulator. The semiconductor device according to claim 1, wherein the front semiconductor layer or the insulator is formed in the semiconductor substrate under a channel region of the field effect transistor. 3. The semiconductor device according to claim 1, wherein the semiconductor layer or the insulator is formed in the semiconductor substrate under a source region and a drain region of the field effect transistor. Forming a groove on the surface of the semiconductor substrate;
Forming a cavity by closing the opening of the groove by heat treatment under reduced pressure;
And a step of forming a field effect transistor on the region including the cavity. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the heat treatment under reduced pressure is performed in a non-oxidizing atmosphere. The method of manufacturing a semiconductor device according to claim 5, wherein the non-oxidizing atmosphere is a hydrogen atmosphere. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the step of forming the cavity is performed after the inner surface of the groove is covered with a film made of a semiconductor having a melting point lower than that of a constituent element of the semiconductor substrate. . Forming a groove on the surface of the semiconductor substrate;
A step of filling the inside of the groove with an insulator to a depth in the middle thereof;
Depositing an amorphous semiconductor film over the entire surface;
A step of making the amorphous semiconductor film epitaxial by heat treatment in a reducing atmosphere and embedding a remaining portion inside the groove with a single crystal semiconductor;
Forming a lateral field effect transistor over the region including the insulator. A method for manufacturing a semiconductor device, comprising:

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