JP2005166854A - Semiconductor device - Google Patents
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- JP2005166854A JP2005166854A JP2003402360A JP2003402360A JP2005166854A JP 2005166854 A JP2005166854 A JP 2005166854A JP 2003402360 A JP2003402360 A JP 2003402360A JP 2003402360 A JP2003402360 A JP 2003402360A JP 2005166854 A JP2005166854 A JP 2005166854A
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Abstract
Description
本発明は、サージ電流破壊耐量の高いダイオードを有する半導体装置に関する。 The present invention relates to a semiconductor device having a diode with high surge current breakdown resistance.
IGBT、ダイオード、GTO、トランジスタ等のパワー半導体モジュールが従来技術として知られている。これらのパワー半導体素子はその耐圧や電流容量に応じて、各種インバータ装置などに適用されている。中でもIGBTは大電流の高周波動作が可能であり、電圧制御素子であるために制御が容易であるなどの利点を有している。また安全性や実装上の簡便性から、多くの場合はモジュールのベース部分と電流通流部分とが絶縁基板によって電気的に絶縁された、内部絶縁型の構造となっている。 Power semiconductor modules such as IGBTs, diodes, GTOs, and transistors are known as conventional techniques. These power semiconductor elements are applied to various inverter devices and the like according to their withstand voltage and current capacity. Among them, the IGBT is capable of high-frequency operation with a large current and has advantages such as easy control because it is a voltage control element. In many cases, the base portion of the module is electrically insulated from the current passing portion by an insulating substrate for safety and ease of mounting.
IGBTモジュールでは、逆電圧印加防止と還流目的でダイオードが設けてある場合が多い。このダイオードに要求される特性の中に、サージ電流破壊耐量がある。これは何らかの理由により突発的に大電流がダイオードを流れても破壊しない電流を示すもので、想定される波形である正弦波電流に対して規定されることが多い。このサージ電流破壊耐量が高いほど、実使用において誤動作による半導体装置の破壊確率が下がり、使いやすいものになる。 In an IGBT module, a diode is often provided for the purpose of preventing reverse voltage application and refluxing. Among the characteristics required for this diode is surge current breakdown capability. This indicates a current that does not break even if a large current suddenly flows through the diode for some reason, and is often specified for a sine wave current that is an assumed waveform. The higher the surge current breakdown tolerance, the lower the probability of breakdown of the semiconductor device due to malfunction in actual use, making it easier to use.
このサージ電流によってダイオードが破壊する場合、ダイオード素子におけるワイヤ近傍の半導体素子表面に形成した電極(以下、表面電極と略す。)が溶解している。このことからワイヤ付近の表面電極部に大電流が集中し、温度上昇により電極が溶解したと考えられる。つまり表面電極部に局所的に電流を集中させない構造を持たせることがサージ電流破壊耐量向上に有効である。そのための手法として、ワイヤの抵抗値を等しくする方法が特許文献1に開示されている。この特許文献1では図3(a)に示すワイヤ3の抵抗値を全て等しくしてある。なお、図3(a)において、符号1は電力半導体素子、2は表面電極、3はワイヤ、4、5は外部電極、6は絶縁基板、8はワイヤと電極との接合部である。また、図3(b)は、図3(a)のC−C′での断面図であり、符号7は半田を示す。
When the diode is destroyed by this surge current, an electrode (hereinafter abbreviated as a surface electrode) formed on the surface of the semiconductor element near the wire in the diode element is dissolved. From this, it is considered that a large current was concentrated on the surface electrode near the wire, and the electrode was dissolved by the temperature rise. In other words, it is effective for improving the surge current breakdown resistance to have a structure that does not concentrate current locally on the surface electrode portion. As a technique for this purpose,
また、特許文献2では、外部電極のエリアや空間的スペースを小さくするために、1本のワイヤを表面電極上の2箇所以上で接合する手法を開示している。
前記特許文献1に記載されているようにワイヤの抵抗値を等しくしただけでは、ワイヤ接合部の表面電極が溶解することの本質的な対策にはならず、ワイヤの本数を増やすなどしてワイヤ接合部の数をできるだけ多くして、表面電極の電流密度を下げる必要がある。しかしながら、表面電極や外部電極のワイヤ接合可能エリアが狭かったり、あるいは空間的スペースが狭い場合には、ワイヤの本数を多くできない問題がある。
Just as the resistance value of the wire is equalized as described in
また、前記特許文献2に記載されているように、単に接合箇所を増やしただけでは、外部電極に最も近い接点に電流が集中するので、サージ電流破壊耐量を向上できない。
Further, as described in
本発明の目的は、表面電極上のワイヤ接合部における電流集中が小さく、サージ電流破壊耐量が高い半導体装置を提供することである。 An object of the present invention is to provide a semiconductor device having a small current concentration at a wire junction on a surface electrode and a high surge current breakdown resistance.
本発明の半導体装置は、1本のワイヤと半導体素子の表面電極とが2箇所以上で接合し、かつ前記金属ワイヤが前記各接合部の間をループを持たせずに表面電極面に沿って直線配置して、ワイヤの抵抗を小さくした。 In the semiconductor device according to the present invention, one wire and the surface electrode of the semiconductor element are bonded at two or more locations, and the metal wire does not have a loop between the bonding portions along the surface electrode surface. The resistance of the wire was reduced by arranging in a straight line.
また、本発明の半導体装置は、1本のワイヤと半導体素子の表面電極とが1箇所で接合し、該接合部の長さが金属ワイヤの直径の5倍から100倍であって、かつワイヤの接合部が表面電極面に沿って直線配置してワイヤ接合部での電流集中を回避した。 In the semiconductor device of the present invention, one wire and the surface electrode of the semiconductor element are joined at one place, and the length of the joint is 5 to 100 times the diameter of the metal wire, and the wire These junctions were arranged linearly along the surface electrode surface to avoid current concentration at the wire junction.
本発明の半導体装置は、表面電極上のワイヤ接合部における電流集中が小さく、サージ電流破壊耐量を高くできる。 In the semiconductor device of the present invention, the current concentration at the wire junction on the surface electrode is small, and the surge current breakdown resistance can be increased.
以下本発明の実施例の詳細を図面を参照しながら説明する。 Details of embodiments of the present invention will be described below with reference to the drawings.
図1(a)は、本実施例の半導体装置の平面図を示す。また、図1(b)は図1(a)のA−A′での断面図である。図1(a)、図1(b)で、符号1は電力半導体素子、2は表面電極、3はワイヤ、4、5は外部電極、6は絶縁基板、7は半田、8はワイヤ3と表面電極2との接合部、9はワイヤと外部電極5との接合部である。表面電極2は電力半導体素子1の表面に形成されていて、外部電極4は電力半導体素子1の裏面と半田7を介して電気的に接合している。以下、電力半導体素子1としてシリコン基板に形成したダイオードを例に説明する。
FIG. 1A is a plan view of the semiconductor device of this example. FIG. 1B is a cross-sectional view taken along the line AA ′ of FIG. 1A and 1B,
ワイヤ3は外部電極5から半導体素子1へ電流を流す役目をしており、半導体素子1の表面電極2によって導通している。本実施例では、ワイヤ3はアルミニウムワイヤあるいは、アルミニウムを主成分とするアルミニウム合金ワイヤであり、その直径は150μmから1mm程度である。また、表面電極2はシリコン半導体基板に直接あるいは絶縁膜を介して配置したアルミニウム膜あるいはアルミニウムを主成分とするアルミニウム合金(例えばAl−Si合金)の膜であって、1辺が3mmから15mm程度の4辺形である。表面電極2は、アルミニウムあるいはアルミニウム合金と、例えば、TiWなどとを積層した多層膜であっても良い。ワイヤ3と表面電極2や外部電極5とは、例えば超音波接合によって電気的に接合されている。なお、ワイヤ3は径が太過ぎると表面電極2への接合の際に過大な圧力を加え表面電極にダメージを与えるので、好ましくない。
The
本実施例では、1本のワイヤ3が電力半導体素子1の表面電極2の上の複数箇所(図1(a)では2箇所)の接合部8で接合されているが、ワイヤ3は、その接合部8の間でループを形成せずに、表面電極2の電極面に沿って接合部8の間を最短の長さで1本の直線で結ぶように配置してある。このように本実施例の半導体装置ではワイヤ3が最短の長さで表面電極2の上の各接合部8を結んでいるので、複数の接合部8間のワイヤ3の電気抵抗が最も小さくなり、表面電極2側の接合部8への電流集中が回避できる。なお、1本のワイヤ3を表面電極に接続する接合部8の数は、2箇所から5箇所が好ましい。
In the present embodiment, one
本実施例では、図1(a)、図1(b)に示すように、平行に配置した複数本数のワイヤ3全ての表面電極2側の端部をそれぞれ複数箇所の接合部8で接合しているが、このワイヤ3は1本であっても良い。また、複数あるワイヤ3のうちの、少なくとも1本のワイヤ3が図1(a)、図1(b)に示すような接合部8を備えていても良い。このように本実施例では、ワイヤ3の本数を大きく増やしたり、ワイヤの径を極端に大きくすることなく、表面電極2側の接合部8への電流集中を回避したので、サージ電流破壊耐量が高い半導体装置を実現できた。
In this embodiment, as shown in FIGS. 1 (a) and 1 (b), the end portions on the
図2(a)に本実施例の半導体装置の平面図を示す。また、図2(b)は、図2(a)のB−B′での断面図である。本実施例の半導体装置は、1本のワイヤ3が電力半導体素子1の表面電極2の1箇所の接合部8で接合されている。ワイヤ3の接合部8は、表面電極2の電極面に沿ってワイヤ3の直径の5倍から100倍、好ましくは10倍から50倍の長さ、より好ましくは20倍から40倍の長さに渡って、接合している点が実施例1の半導体装置と異なる。接合部8の長さがワイヤ3の直径の5倍未満では表面電極2とワイヤ3との接合部8に過大な電流が集中し好ましくない。また、接合部8の長さがワイヤ3の直径の100倍以上では、ワイヤ3を表面電極2にムラなく接合できない。
FIG. 2A is a plan view of the semiconductor device of this example. FIG. 2B is a cross-sectional view taken along the line BB ′ of FIG. In the semiconductor device of this embodiment, one
本実施例の半導体装置では、図2(a)、図2(b)に示すように、ワイヤ3は表面電極2の横方向に渡って接合されていて、接合部8の接合面積が大きいので、表面電極2の局部的な電流密度上昇を回避でき、サージ電流破壊耐量が向上する。
In the semiconductor device of the present embodiment, as shown in FIGS. 2A and 2B, the
本実施例の半導体装置は、複数本のワイヤ3のうち、1本のワイヤ3の表面電極2側の端部を複数箇所の接合部8で接合したものと、1本のワイヤ3が電力半導体素子1の表面電極2の1箇所の接合部8で接合していて、この接合部8が、表面電極2の電極面に沿ってワイヤ3の直径の5倍から100倍、好ましくは10倍から50倍の長さに渡って接合しているものとを備えていることだけが前記実施例1、実施例2と異なる。本実施例でも表面電極2側の接合部8への電流集中を回避したので、サージ電流破壊耐量が高い半導体装置が実現できた。
In the semiconductor device of the present embodiment, among the plurality of
1…電力半導体素子、2…表面電極、3…ワイヤ、4,5…外部電極、6…絶縁基板、7…半田、8,9…接合部。
DESCRIPTION OF
Claims (4)
1本の前記金属ワイヤと半導体素子の前記表面電極とが2箇所以上で接合し、かつ前記金属ワイヤが前記各接合部の間を表面電極面に沿って直線配置されていることを特徴とする半導体装置。 A semiconductor element having an electrode on the surface; an external electrode provided outside the semiconductor element; an insulating substrate on which the semiconductor element and the external electrode are mounted; and a metal wire that joins the semiconductor element and the external electrode. In a semiconductor device having
One metal wire and the surface electrode of the semiconductor element are joined at two or more places, and the metal wire is linearly arranged along the surface electrode surface between the joints. Semiconductor device.
1本の前記金属ワイヤと半導体素子の前記表面電極とが1箇所で接合し、該接合部の長さが金属ワイヤの直径の5倍から100倍であって、かつ前記金属ワイヤの接合部が表面電極面に沿って直線配置されていることを特徴とする半導体装置。 A semiconductor element having an electrode on the surface; an external electrode provided outside the semiconductor element; an insulating substrate on which the semiconductor element and the external electrode are mounted; and a metal wire that joins the semiconductor element and the external electrode. In a semiconductor device having
One metal wire and the surface electrode of the semiconductor element are joined at one place, the length of the joint is 5 to 100 times the diameter of the metal wire, and the joint of the metal wire is A semiconductor device, wherein the semiconductor device is linearly arranged along a surface electrode surface.
4. The semiconductor device according to claim 1, wherein the semiconductor element is a diode, and the surface electrode is aluminum or an aluminum alloy.
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