JP2007201247A - High withstand voltage semiconductor device - Google Patents

High withstand voltage semiconductor device Download PDF

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Publication number
JP2007201247A
JP2007201247A JP2006019036A JP2006019036A JP2007201247A JP 2007201247 A JP2007201247 A JP 2007201247A JP 2006019036 A JP2006019036 A JP 2006019036A JP 2006019036 A JP2006019036 A JP 2006019036A JP 2007201247 A JP2007201247 A JP 2007201247A
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JP
Japan
Prior art keywords
semiconductor device
power chip
active region
solder
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006019036A
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Japanese (ja)
Inventor
Yasushi Nakajima
Michiaki Takenaka
泰 中島
通暁 武中
Original Assignee
Mitsubishi Electric Corp
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by Mitsubishi Electric Corp, 三菱電機株式会社 filed Critical Mitsubishi Electric Corp
Priority to JP2006019036A priority Critical patent/JP2007201247A/en
Publication of JP2007201247A publication Critical patent/JP2007201247A/en
Application status is Pending legal-status Critical

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

<P>PROBLEM TO BE SOLVED: To fabricate a high withstand voltage semiconductor device which suppresses the local temperature rise of the surface of a power chip and is high in short-circuit resistance. <P>SOLUTION: The semiconductor device is composed of a power chip including a guard ring prepared around an active region and the perimeter of the active region. The rear side of the power chip is joined to a first electrode through a first solder; the surface of the power chip is joined to a metal plate electrode through a metal layer; and a second solder, the surface of the first electrode, the power chip, and the perimeter of the metal plate electrode are sealed by a sealing material. The high withstand voltage semiconductor device is provided in which an insulation layer is arranged over the periphery of the active region and the guard ring, the metal layer is arranged over the active region not covered by the insulation layer, and the metal layer and the metal plate electrode are joined by the solder. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a high voltage semiconductor device having a high short-circuit tolerance.

  As a high breakdown voltage semiconductor device used for motor inverter control or the like, for example, a device having a main breakdown voltage between PN electrodes of about 600V to 1200V is widely used. The high breakdown voltage semiconductor device includes a power chip such as an IGBT or a diode. The high withstand voltage semiconductor device performs a switching operation by cutting off and energizing a voltage of several hundreds to several thousand volts between the electrode on the front surface and the electrode on the rear surface of the power chip, thereby generating a driving voltage for the motor. Such a power chip needs to be capable of blocking a voltage of several hundred volts or more between the front and back surfaces of the power chip.

  In a high voltage semiconductor device mounted with a power chip as described above, since the electric field state is different between the planar portion (surface portion) and the outer peripheral portion of the power chip, the high voltage semiconductor device has an outer edge portion of the surface electrode of the power chip. In some cases, a guard ring is built in to relax the electric field, thereby ensuring a withstand voltage characteristic.

  The power chip of the high voltage semiconductor device is used by soldering the entire back surface to an electrode plate or an electrode pattern. As the surface electrode, a form in which an aluminum wire having a thickness of several hundreds μm is joined by ultrasonic wire bonding and wiring is often used. However, when wire bonding is used, current is concentrated on a local portion of the power chip surface. In other words, the use of wire bonding creates a high-temperature part directly under the wire, which increases the thermal stress at that part, or biases the current distributed over the entire surface of the power chip due to the resistance of the surface metallization layer of the power chip. Or the like, resulting in a current distribution. Further, if the power chip is not quickly turned off during the so-called short circuit in which the upper and lower arms are simultaneously turned on, thermal destruction (that is, short circuit destruction) occurs. However, in the case of a power chip using wire bonding, as described above. There is also a problem that short circuit breakdown is likely due to large current concentration.

  The short-circuit breakdown here refers to a state in which the local temperature exceeds a certain threshold value and the part of the semiconductor becomes a conductor due to a high temperature. It is said that the above-mentioned temperature threshold in a high voltage semiconductor device with a power chip mounted is generally 380 ° C.

  As one of the solutions to the problems of the above-described wire bonding utilization technique, Patent Document 1 discloses a semiconductor device having a structure in which a metal layer such as Au is coated on the surface of a power chip by, for example, vapor deposition and an electrode plate is soldered. Yes. However, in the semiconductor device disclosed in Patent Document 1, since the metal plate is soldered to avoid the guard ring portion, a portion that is not soldered to the outer edge portion of the active region occurs, and short-circuit breakdown occurs in the portion. It is likely to occur.

Patent Document 2 discloses an invention related to a semiconductor device that prevents the occurrence of cracks on the chip surface due to a solder flow and improves the reliability against thermal stress of a product. Patent Document 3 discloses an invention relating to a semiconductor device having a planar termination structure surrounding a semiconductor active region by a guard ring. Furthermore, Patent Document 4 discloses an invention relating to a pressure-contact type high voltage semiconductor device configured such that when the main electrode is pressed by a post electrode, the post electrode is not short-circuited to a circuit portion related to the control electrode. The pressure-contact type high voltage semiconductor device includes one or more guard rings surrounding a semiconductor active region.
Japanese Patent No. 3525832 Japanese Patent Laid-Open No. 5-218454 JP 2001-44414 A Japanese Patent Laid-Open No. 8-23094

  It is an object of the present invention to produce a high voltage semiconductor device having a high short circuit resistance by suppressing a local temperature rise on the surface of a power chip.

The present invention has been made to achieve the above object. The high voltage semiconductor device according to the present invention is
It is composed of a power chip including an active region and a guard ring portion provided around the active region,
The back surface of the power chip is bonded to the first electrode via the first solder, the front surface of the power chip is bonded to the metal plate electrode via the metal layer and the second solder,
A semiconductor device in which the surface of the first electrode, the power chip, and the periphery of the metal plate electrode are sealed with a sealing material,
An insulating layer is disposed to cover the outer periphery of the active region and the guard ring part,
The metal layer is disposed to cover the insulating layer and the active region not covered by the insulating layer;
The metal layer and the metal plate electrode are joined by the solder.

  By utilizing the present invention, in a high breakdown voltage semiconductor device, first, solder becomes a thermal buffer at the time of short circuit, and the short circuit tolerance of the semiconductor device is improved. Moreover, it becomes easy to ensure the solder thickness under the metal plate electrode.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments according to the present invention will be described below with reference to the drawings. In the following description, the terms “upper”, “lower”, “right”, “left”, “front”, “back” and other terms including those terms (for example, “upper surface”) indicating a specific direction. , “Bottom surface”, “right side”, “left side”, “front main surface”, “back main surface”), are used as appropriate to facilitate the understanding of the invention with reference to the drawings, The technical scope of the invention is not limited by these terms. Accordingly, embodiments of the specific invention described below are upside down or rotated 90 ° in any direction (for example, clockwise direction or counterclockwise direction) as a matter of course. It is included.

  First, FIG. 8 shows a longitudinal sectional view of a high voltage semiconductor device according to the prior art (for example, disclosed in Patent Document 1). In the semiconductor device, the power chip 2 is joined to the electrode 4 with solder 6. A metal layer having solder wettability is disposed on the active region 8 on the surface of the power chip 2, and a metal plate 18 is set on the metal layer via solder 16. A guard ring portion 10 is formed around the active region 8 of the power chip 2. In such a semiconductor device, the surface of the electrode 4, the periphery of the power chip 2 and the metal plate 18 are sealed with an insulating sealing material 20 such as a mold resin. In addition, the vertical wavy lines at the left and right ends in FIG. 8 indicate that illustration of the outside thereof is omitted (the same applies to other drawings hereinafter).

  In the high breakdown voltage semiconductor device, a metallized layer that can be soldered is formed by vapor deposition or the like in most regions of the surface electrode of the power chip 2. A metal plate 18 is soldered on the metallized layer. Therefore, compared to the case of a semiconductor device in which the active region 8 is formed so as to be bonded only to the metallized layer, the wiring resistance of the metallized layer is so small that it can be ignored. Energy loss due to the resistance of the power chip is also reduced. Moreover, it can be said that the temperature rise at the time of a short circuit is relieved by the heat capacity of the solder bonded to the surface of the power chip 2 and the electrode plate 18.

  By the way, in the high breakdown voltage semiconductor device in which the metal plate 18 is soldered to the surface of the power chip, the short-circuit breakdown tends to concentrate on a region where the solder is not joined. This is because the temperature rise in the region where the solder is not joined is larger than that in other regions. That is, since solder has a high thermal conductivity as a metal, it has an action of suppressing a temperature rise. On the other hand, a temperature rise in a region where the solder is not joined increases. In the high voltage semiconductor device according to the prior art of FIG. 8, no solder exists in the guard ring portion 10 and the vicinity thereof. Therefore, it can be said that there is a high probability that a short circuit breakage occurs in a region outside the active region 8 where the metal plate 18 is not joined.

  FIG. 3 shows the active voltage when the metal plate 18 is arranged on the surface of the active region 8 at a distance from the inner periphery of the guard ring portion 10 in the high voltage semiconductor device as shown in FIG. It is a graph which shows the relationship between the width | variety of the area | region where the metal plate 18 of area | region 8 upper part does not exist, and the short circuit tolerance of a power chip. The short-circuit tolerance is calculated by “current × voltage × time”, and a larger value indicates that the semiconductor device is less likely to be destroyed.

  FIG. 3 shows that the short-circuit resistance increases as the width of the region of the active region 8 where the metal plate 18 is not present is smaller. Since the metal plate 18 and the solder 16 joined to the metal plate suppress the temperature increase of the active region 8 covered by the metal plate 18 and the solder 16 with a sufficient heat capacity, as shown in FIG. It can be seen that short-circuit breakdown is likely to occur in a region where the metal plate 18 is not joined. When a current that could cause a short circuit was applied to the power chip 2 by an experiment, the above-mentioned effects were confirmed because the locations to be destroyed were concentrated in the area where the metal plate 18 on the outer periphery of the active area 8 was not present. did it.

  In the following embodiments of the present invention, the high-voltage semiconductor device has a higher short-circuit resistance than that shown in FIG. Therefore, in the following embodiments of the present invention, except for the guard ring portion 10 and the vicinity thereof, a structure substantially similar to the semiconductor device according to the prior art shown in FIG. 8 is provided.

[Embodiment 1]
FIG. 1 is a longitudinal sectional view of a high voltage semiconductor device according to Embodiment 1 of the present invention. As shown in the figure, the power chip 2 is joined to the electrode 4 with solder 6. The power chip 2 is provided with a back electrode (not shown), and the soldering is performed on the back electrode. The power chip 2 has a vertical and horizontal (plane direction) size of several mm × several mm and a thickness of about 50 μm to 500 μm.

  An active region 8 and a guard ring portion 10 are formed on the outer periphery of the active region 8 on the surface of the power chip 2. The guard ring portion 10 ensures a withstand voltage between the active region 8 and the back surface of the power chip 2. The guard ring portion 10 is disposed within a width of about 100 μm to several mm from the outer peripheral edge of the power chip 2.

  Furthermore, in the high voltage semiconductor device according to the first embodiment of the present invention, the insulating layer 12 is disposed so as to cover the guard ring portion 10. The insulating layer 12 covers from the outer periphery of the active region 8 to the outer periphery of the power chip 2. In the high breakdown voltage semiconductor device as shown in FIG. 1, the insulating layer 12 preferably has a thickness of several tens of μm to several mm. The insulating layer 12 is preferably made of a highly heat-resistant resin such as polyimide having a heat-resistant temperature of 300 ° C. or a ceramic material such as glass. Further, a metal layer 14 having solder wettability is disposed on the surface of the insulating layer 12 and the surface of the active region 8.

  FIG. 2 is an enlarged longitudinal sectional view of the guard ring portion 10, the insulating layer 12, and the vicinity thereof of the high voltage semiconductor device according to the first embodiment of the present invention. As shown in FIG. 2, a metallized layer 22 is disposed on the surfaces of the active region 8 and the guard ring portion 10. As the metallized layer 22, aluminum having a thickness of several μm is usually used. Aluminum is a metal with relatively poor solder wettability, and it is difficult to solder the metal plate 18 as it is. Therefore, the metal layer 14 is disposed in contact with the insulating layer 12 covering the outer peripheral portion of the active region 8 and the guard ring portion 10 and the surface of the active region 8. A metal plate 18 is fixed by solder 16 via the metal layer 14.

  The surface of the electrode 4, the periphery of the power chip 2 and the metal plate 18 are sealed with an insulating sealing material 20 such as a mold resin. The vertical wavy lines at the left and right ends in FIG. 1 indicate that the outer side is not shown.

  As described above, in the high voltage semiconductor device shown in FIGS. 1 and 2, the metal plate 18 is disposed not only on the active region 8 but also on the surface of the insulating layer 14. For this reason, the heat capacity with respect to the entire surface of the active region 8 is increased, so that the temperature rise can be suppressed to several tens of percent of the conventional semiconductor device using wire bonding. As a result, the time until it reaches a local temperature (for example, 380 ° C.) that causes a short-circuit breakdown is significantly increased. It does n’t happen. That is, it is possible to expand the allowable range of energy up to short-circuit failure.

  In the high voltage semiconductor device according to the first embodiment, the metal plate 18 has substantially the same potential as the active region 8, and the voltage between the active region 8 and the back surface of the power chip 2 is equal to the thickness of the insulating layer 12. Secured by insulation at creepage distance. Therefore, in order to reduce the thickness of the insulating layer 12, it is necessary to use a highly insulating sealing resin for the insulating layer 12.

  Furthermore, in the high breakdown voltage semiconductor device according to the first embodiment, the solder 16 is bonded to the entire surface side of the metal layer 14, but it is not always necessary to bond the entire surface. For example, the number of the insulating layers 12 at the end portion. Even if only about 10% is covered, the short-circuit resistance can be improved.

  The high breakdown voltage semiconductor device according to the present embodiment needs to be designed so that the metal layer 14 does not contact the guard ring portion 10, that is, the insulating layer 12 covers the outer peripheral edge of the active region 8. . This is because when the guard ring portion 10 and the metal layer 14 are in contact with each other, the two become the same potential, and the electric field strength becomes larger than a predetermined value. In order to avoid this, for example, the active region 8, the guard ring portion 10, and the metal layer 14 may be arranged as in the following procedure.

  First, a film is formed on the entire surface of the power chip 2. Next, an opening is provided by etching. The opening is provided in order to define the region of the insulating layer 12. That is, the insulating layer 12 is formed in a portion excluding the opening. Therefore, if the size of the opening is adjusted as appropriate, the insulating layer 12 completely covers the outer periphery of the guard ring portion 10 and the active region 8 even if a slight positional shift occurs when the opening is installed. Can do. It can be said that installing the opening in this manner is desirable because it is relatively easy as a manufacturing method and increases the ease of electric field design in a semiconductor device.

  Further, the active region 8, the metal layer 14 on the active region, or the metal plate 18 may be provided with a protrusion for maintaining the thickness of the solder 16. By this protrusion, the thickness of the solder, that is, the minimum distance between the metal plate 18 and the metal layer 14 can be defined, and the occurrence of problems such as the protrusion of the solder 16 due to the inclination of the metal plate 18 can be prevented.

[Embodiment 2]
FIG. 4 is a longitudinal sectional view of a high voltage semiconductor device according to Embodiment 2 of the present invention. The high voltage semiconductor device according to the second embodiment is substantially the same as the high voltage semiconductor device according to the first embodiment. Therefore, the same parts are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIG. 4, the metal layer 14 is disposed in contact with the active region 8 and the insulating layer 12 as in the first embodiment. However, the metal layer 14 does not extend to the outer edge portion of the insulating layer 12. Accordingly, the solder 16 and the metal plate 18 do not exist above the outer edge of the insulating layer 12. Also by arranging the metal layer 14, the solder 16, and the metal plate 18 as shown in FIG. 4, the heat capacity associated with the active region 8 can be increased, and the short-circuit tolerance can be increased.

  FIG. 5 is an enlarged longitudinal sectional view of the guard ring portion 10, the insulating layer 12, and the vicinity thereof in the high voltage semiconductor device according to the second embodiment of the present invention. As shown in FIG. 5, the distance between the metal layer 14 in contact with the active region 8 of the power chip 2 and the back electrode of the power chip 2 is the distance (L1) from the metal layer 14 to the outer periphery of the insulating layer 12 and the power chip. 2 (L1 + L2) with the thickness (L2) of 2. The distance between the metal layer 14 in contact with the active region 8 of the power chip 2 and the back electrode of the power chip 2 is the insulation distance. That is, in this embodiment, the insulation distance can be increased even if the insulating layer 12 is thin.

[Embodiment 3]
FIG. 6 is a longitudinal sectional view of a high voltage semiconductor device according to Embodiment 3 of the present invention. Further, FIG. 7 is an enlarged longitudinal sectional view of the guard ring portion 10, the insulating layer 12, and the vicinity thereof in the high voltage semiconductor device according to the third embodiment of the present invention. The high voltage semiconductor device according to the third embodiment is substantially the same as the high voltage semiconductor device according to the first embodiment described above. Therefore, the same parts are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIGS. 6 and 7, a second insulating layer 24 whose thickness increases as it approaches the outer edge is fixed to the upper portion of the insulating layer 12. At this time, even if the metal layer 14 is disposed up to the outer peripheral edge of the power chip 2, the distance between the metal layer 14 and the back electrode of the power chip 2 is ensured to be a certain value or more by the second insulating layer 24. . By doing so, it is not necessary to increase the width of the guard ring portion 10. Furthermore, the thickness of the solder 16 between the metal plate 18 and the metal layer 14 can be easily ensured by providing the second insulating layer 24.

1 is a longitudinal sectional view of a high voltage semiconductor device according to a first embodiment of the present invention. FIG. 3 is an enlarged longitudinal sectional view of a guard ring portion, an insulating layer, and the vicinity thereof of the high voltage semiconductor device according to the first embodiment of the present invention. In the high withstand voltage semiconductor device as shown in FIG. 8, there is no metal plate above the active region when the metal plate is arranged on the surface of the active region so as to be spaced from the inner periphery of the guard ring portion. It is a graph which shows the relationship between the width | variety of an area | region, and the short circuit tolerance of a power chip. It is a longitudinal cross-sectional view of the high voltage | pressure-resistant semiconductor device which concerns on Embodiment 2 of this invention. It is an enlarged longitudinal cross-sectional view of the guard ring part of the high voltage semiconductor device concerning Embodiment 2 of this invention, an insulating layer, and its vicinity. It is a longitudinal cross-sectional view of the high voltage semiconductor device concerning Embodiment 3 of this invention. It is an expanded sectional view of a guard ring part, an insulating layer, and its vicinity of a high voltage semiconductor device concerning Embodiment 3 of the present invention. It is a longitudinal cross-sectional view of the high voltage semiconductor device by a prior art.

Explanation of symbols

2 power chip, 4 electrode, 6 solder, 8 active region, 10 guard ring, 12 insulating layer, 14 metal layer, 16 solder, 18 metal plate, 20 sealing material, 22 metallized layer, 24 second insulating layer.

Claims (3)

  1. It is composed of a power chip including an active region and a guard ring portion provided around the active region,
    The back surface of the power chip is bonded to the first electrode via the first solder, the front surface of the power chip is bonded to the metal plate electrode via the metal layer and the second solder,
    A semiconductor device in which the surface of the first electrode, the power chip, and the periphery of the metal plate electrode are sealed with a sealing material,
    An insulating layer is disposed to cover the outer periphery of the active region and the guard ring part,
    The metal layer is disposed to cover the insulating layer and the active region not covered by the insulating layer;
    A high breakdown voltage semiconductor device, wherein the metal layer and the metal plate electrode are joined by the solder.
  2. It is composed of a power chip including an active region and a guard ring portion provided around the active region,
    The back surface of the power chip is bonded to the first electrode via the first solder, the front surface of the power chip is bonded to the metal plate electrode via the metal layer and the second solder,
    A semiconductor device in which the surface of the first electrode, the power chip, and the periphery of the metal plate electrode are sealed with a sealing material,
    An insulating layer is disposed to cover the outer periphery of the active region and the guard ring part,
    The metal layer is disposed to cover at least part of the insulating layer;
    A high breakdown voltage semiconductor device, wherein the metal layer and the metal plate electrode are joined by the solder.
  3. A second insulating layer is further stacked on the insulating layer on the surface of the guard ring portion;
    2. The high breakdown voltage semiconductor device according to claim 1, wherein the metal layer is disposed so as to cover the second insulating layer, the insulating layer, and the active region not covered with the insulating layer. .

JP2006019036A 2006-01-27 2006-01-27 High withstand voltage semiconductor device Pending JP2007201247A (en)

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JP2009231321A (en) * 2008-03-19 2009-10-08 Denso Corp Silicon carbide semiconductor device and its manufacturing method
JP2010034306A (en) * 2008-07-29 2010-02-12 Mitsubishi Electric Corp Semiconductor device
WO2016103434A1 (en) * 2014-12-26 2016-06-30 株式会社日立製作所 Semiconductor device, method for manufacturing same, and semiconductor module
WO2016162987A1 (en) * 2015-04-08 2016-10-13 株式会社日立製作所 Semiconductor device and semiconductor module
WO2017175426A1 (en) * 2016-04-06 2017-10-12 三菱電機株式会社 Semiconductor device for power
WO2017216991A1 (en) * 2016-06-15 2017-12-21 株式会社日立パワーデバイス Semiconductor apparatus, method for manufacturing semiconductor apparatus, semiconductor module, and power conversion apparatus

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JP2009231321A (en) * 2008-03-19 2009-10-08 Denso Corp Silicon carbide semiconductor device and its manufacturing method
JP4535151B2 (en) * 2008-03-19 2010-09-01 トヨタ自動車株式会社 Method for manufacturing silicon carbide semiconductor device
US7825017B2 (en) 2008-03-19 2010-11-02 Denso Corporation Method of making silicon carbide semiconductor device having multi-layered passivation film with uneven surfaces
JP2010034306A (en) * 2008-07-29 2010-02-12 Mitsubishi Electric Corp Semiconductor device
US8450828B2 (en) 2008-07-29 2013-05-28 Mitsubishi Electric Corporation Semiconductor device
WO2016103434A1 (en) * 2014-12-26 2016-06-30 株式会社日立製作所 Semiconductor device, method for manufacturing same, and semiconductor module
JPWO2016103434A1 (en) * 2014-12-26 2017-07-13 株式会社日立製作所 Semiconductor device, manufacturing method thereof, and semiconductor module
US10083948B2 (en) 2014-12-26 2018-09-25 Hitachi, Ltd. Semiconductor device, method for manufacturing same, and semiconductor module
JPWO2016162987A1 (en) * 2015-04-08 2017-06-29 株式会社日立製作所 Semiconductor device and semiconductor module
WO2016162987A1 (en) * 2015-04-08 2016-10-13 株式会社日立製作所 Semiconductor device and semiconductor module
WO2017175426A1 (en) * 2016-04-06 2017-10-12 三菱電機株式会社 Semiconductor device for power
JPWO2017175426A1 (en) * 2016-04-06 2018-08-09 三菱電機株式会社 Power semiconductor device
WO2017216991A1 (en) * 2016-06-15 2017-12-21 株式会社日立パワーデバイス Semiconductor apparatus, method for manufacturing semiconductor apparatus, semiconductor module, and power conversion apparatus

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