JP2005159288A - Semiconductor device housing package and its semiconductor equipment - Google Patents

Semiconductor device housing package and its semiconductor equipment Download PDF

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JP2005159288A
JP2005159288A JP2004220837A JP2004220837A JP2005159288A JP 2005159288 A JP2005159288 A JP 2005159288A JP 2004220837 A JP2004220837 A JP 2004220837A JP 2004220837 A JP2004220837 A JP 2004220837A JP 2005159288 A JP2005159288 A JP 2005159288A
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semiconductor element
convex portion
frame
base
package
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Masaki Ikuji
正樹 生地
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Kyocera Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device housing package where a temperature rise in the semiconductor device is suppressed by efficiently discharging heat generated in the semiconductor device to the outside, which allows the semiconductor device operate normally and stably for a long period of time, and causes no crack in a ceramics frame, and the semiconductor equipment thereof. <P>SOLUTION: The semiconductor device housing package has a long plate metal substrate 1 with a convex area 1a formed at the upper main area where the semiconductor device 3 is mounted and a ceramics frame 2 that has a wiring conductor 2a for conducting the inside and outside and has been brazed enclosing the convex area 1a at the upper main area of the substrate 1. Wherein, the thickness of the surrounding of the convex area 1a of the substrate 1 is 0.1 to 0.3 mm and a clearance with a length of 3/100 to 20/100 of the long side length of the convex area 1a is formed between the side of the convex area 1a and the inside of the frame 2 in the both short sides of the substrate 1. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、半導体素子を収容する半導体素子収納用パッケージおよび半導体装置に関する。   The present invention relates to a semiconductor element housing package and a semiconductor device for housing semiconductor elements.

従来の半導体素子を収容するための半導体素子収納用パッケージ（以下、単にパッケージともいう）としては、リードフレームなどに搭載した半導体素子を樹脂モールドした樹脂封止型のパッケージや、金属またはセラミックスから成る中空の容器の内部に半導体素子を気密封止した気密封止型のパッケージが知られている。その中でも、気密封止型のパッケージは、気密性に優れるため、高信頼性が要求される場合に多用されている。   As a conventional semiconductor element storage package (hereinafter also simply referred to as a package) for housing a semiconductor element, a resin-encapsulated package in which a semiconductor element mounted on a lead frame or the like is resin-molded, or a metal or ceramic is used. A hermetic package in which a semiconductor element is hermetically sealed inside a hollow container is known. Among these, hermetically sealed packages are excellent in hermeticity, and are frequently used when high reliability is required.

従来の気密封止型のパッケージの一例を示す断面図を図４に示す。同図において、21は基体、21ａは半導体素子の載置部、22は枠体、23は放熱体、24は入出力端子、25は半導体素子である。基体21は、例えば鉄（Ｆｅ）−ニッケル（Ｎｉ）−コバルト（Ｃｏ）合金等の金属から成り、基体21の上側主面の外周部には、載置部21ａを囲繞するように接合されたＦｅ−Ｎｉ−Ｃｏ合金等の金属からなる枠体22が立設されている。この枠体22は、基体21に銀（Ａｇ）ロウなどのロウ材を介してロウ付けされるか、あるいは基体21と一体成形されることにより設けられる。   FIG. 4 is a cross-sectional view showing an example of a conventional hermetically sealed package. In this figure, 21 is a base, 21a is a semiconductor element mounting portion, 22 is a frame body, 23 is a heat radiator, 24 is an input / output terminal, and 25 is a semiconductor element. The base 21 is made of a metal such as an iron (Fe) -nickel (Ni) -cobalt (Co) alloy, and is joined to the outer peripheral portion of the upper main surface of the base 21 so as to surround the mounting portion 21a. A frame 22 made of a metal such as an Fe—Ni—Co alloy is erected. The frame body 22 is provided by being brazed to the base 21 via a brazing material such as silver (Ag) braze or by being integrally formed with the base 21.

また、基体21の中央部には貫通孔が形成されており、この貫通孔に熱伝導性の高い銅（Ｃｕ）系材料からなる放熱体23がロウ材を介して接合されている。そして、この放熱体23の上面に半導体素子25が載置される載置部21ａが設けられている。   In addition, a through hole is formed in the central portion of the base 21, and a heat radiating body 23 made of a copper (Cu) -based material having high thermal conductivity is joined to the through hole via a brazing material. A mounting portion 21 a on which the semiconductor element 25 is mounted is provided on the upper surface of the heat radiating body 23.

放熱体23は上下２枚の銅板23ａからなり、この２枚の銅板23ａの間にロウ材を挟み、加熱、冷却することにより２枚の銅板23ａが互いに接合されている。そして、貫通孔の内面に２枚の銅板23ａの各側面が全周にわたってロウ材を介して接合されている。   The heat dissipating body 23 is composed of two upper and lower copper plates 23a. A brazing material is sandwiched between the two copper plates 23a, and the two copper plates 23a are joined to each other by heating and cooling. And each side surface of the two copper plates 23a is joined to the inner surface of the through-hole through the brazing material over the entire circumference.

そして、枠体22には側部に貫通孔から成る入出力端子24の取付部22ａが形成されており、この取付部22ａ内に枠体22の内外を気密に封止するアルミナ（Ａｌ２Ｏ３）質焼結体，窒化アルミニウム（ＡｌＮ）質焼結体，ムライト（３Ａｌ２Ｏ３・２ＳｉＯ２）質焼結体等のセラミックスからなる入出力端子24が嵌着されている。 An attachment portion 22a of an input / output terminal 24 having a through hole is formed on a side portion of the frame body 22. Alumina (Al 2 O) that hermetically seals the inside and outside of the frame body 22 in the attachment portion 22a. 3 ) An input / output terminal 24 made of ceramics such as a sintered body, an aluminum nitride (AlN) sintered body, a mullite (3Al 2 O 3 .2SiO 2 ) sintered body is fitted.

入出力端子24は、上面にメタライズ層からなる線路導体24ａが形成された平板部とこの上面に線路導体24ａの一部を間に挟んで接合された立壁部とからなり、枠体22の外側の露出した線路導体24ａ上には外部リード端子27が接合されている。   The input / output terminal 24 includes a flat plate portion having a line conductor 24a formed of a metallized layer on the upper surface and a standing wall portion joined to the upper surface with a part of the line conductor 24a interposed therebetween. An external lead terminal 27 is joined to the exposed line conductor 24a.

そして、このようなパッケージの載置部21ａに半導体素子25を載置固定するとともに線路導体24ａと半導体素子25の電極とをボンディングワイヤ26を介して電気的に接続し、枠体22の上面にＦｅ−Ｎｉ−Ｃｏ合金等の金属からなる蓋体28を金（Ａｕ）−錫（Ｓｎ）等のロウ材を用いたロウ付け法やシームウエルド法等の溶接法で取着することにより、主にこれら基体21、枠体22、蓋体28、入出力端子24、放熱体23から成る製品としての半導体装置が構成されている。   Then, the semiconductor element 25 is mounted and fixed on the mounting portion 21a of such a package, and the line conductor 24a and the electrode of the semiconductor element 25 are electrically connected via the bonding wire 26 to the upper surface of the frame body 22. By attaching a lid 28 made of a metal such as an Fe-Ni-Co alloy by a brazing method using a brazing material such as gold (Au) -tin (Sn) or a welding method such as a seam weld method, In addition, a semiconductor device as a product including the base body 21, the frame body 22, the lid body 28, the input / output terminal 24, and the heat radiating body 23 is configured.

この半導体装置は、外部電気回路から供給される電気信号によって半導体素子25を駆動することで無線基地局等に用いられるパワーアンプモジュール用等の半導体装置として機能する。   This semiconductor device functions as a semiconductor device for a power amplifier module used in a radio base station or the like by driving the semiconductor element 25 with an electric signal supplied from an external electric circuit.

そして、この半導体装置によれば、半導体素子25を熱伝導性のよい銅板23ａからなる放熱体23上に搭載するため、半導体素子25が発する熱を放熱体23を介して外部に効率よく放熱することができ、半導体素子25の温度上昇を抑制して半導体素子25を長期間にわたり正常かつ安定に作動させることが可能になるというものである（例えば、特許文献１参照）。
特開2001−217333号公報 According to this semiconductor device, since the semiconductor element 25 is mounted on the radiator 23 made of the copper plate 23a having good thermal conductivity, the heat generated by the semiconductor element 25 is efficiently radiated to the outside via the radiator 23. In other words, the temperature rise of the semiconductor element 25 can be suppressed and the semiconductor element 25 can be operated normally and stably over a long period of time (see, for example, Patent Document 1).
JP 2001-217333 A

しかしながら、従来の構成においては、入出力端子24を枠体22の取付部22ａにロウ付けする際に、Ａｌ２Ｏ３質焼結体（熱膨張係数７×10−６〜８×10−６／℃）等のセラミックス製の入出力端子24にクラック等の破損が生じることがないように、基体21および枠体22として入出力端子24と熱膨張係数が近い値のＦｅ−Ｎｉ−Ｃｏ合金（熱膨張係数５×10−６〜10×10−６／℃）等の金属材料を用いている。しかしながら、近年、半導体素子25の高集積化が急速に進み、半導体素子25の作動時に発生する発熱量が急激に増大してきているのに対して、例えばＦｅ−Ｎｉ−Ｃｏ合金の熱伝導率は17Ｗ／ｍ・Ｋと低い値であるために、放熱体23だけでは半導体素子25で発生する熱を外部に十分に放散できず、半導体素子25の温度が上昇して半導体素子25が正常に作動しなくなるという問題点があった。 However, in the conventional configuration, when the input / output terminal 24 is brazed to the mounting portion 22a of the frame body 22, the Al 2 O 3 sintered material (thermal expansion coefficient 7 × 10 −6 to 8 × 10 −6). Fe-Ni-Co alloy having a coefficient of thermal expansion close to that of the input / output terminal 24 as the base 21 and the frame 22 so that the ceramic input / output terminal 24 such as cracks does not break. A metal material such as (thermal expansion coefficient 5 × 10 −6 to 10 × 10 −6 / ° C.) is used. However, in recent years, the high integration of the semiconductor element 25 has progressed rapidly, and the amount of heat generated when the semiconductor element 25 is activated has increased rapidly. For example, the thermal conductivity of an Fe-Ni-Co alloy is Because it is a low value of 17 W / m · K, the heat generated by the semiconductor element 25 cannot be dissipated sufficiently by the radiator 23 alone, and the temperature of the semiconductor element 25 rises and the semiconductor element 25 operates normally. There was a problem of not going to.

このため、熱伝導率が150〜400Ｗ／ｍ・Ｋと高い値をもつ無酸素Ｃｕ等のＣｕ系材料で基体21および枠体22を形成することが考えられるが、Ｃｕ系材料の熱膨張係数は10×10−６〜20×10−６／℃であり、基体21および枠体22とセラミックス製の入出力端子24とでは、熱膨張差が大きいために枠体22の取付部22ａに入出力端子24をロウ付けすると、入出力端子24に基体21および枠体22との熱膨張差による大きな応力が加わって、入出力端子24にクラック等の破損が生じる場合があった。そしてその結果、パッケージ内部を気密に保持できなくなり。半導体素子25が正常に作動しなくなるという問題点があった。 For this reason, it is conceivable to form the base body 21 and the frame body 22 with a Cu-based material such as oxygen-free Cu having a high thermal conductivity of 150 to 400 W / m · K. Is 10 × 10 −6 to 20 × 10 −6 / ° C., and the base 21 and the frame body 22 and the ceramic input / output terminal 24 have a large difference in thermal expansion, and therefore enter the mounting portion 22a of the frame body 22. When the output terminal 24 is brazed, a large stress due to a difference in thermal expansion between the base 21 and the frame body 22 is applied to the input / output terminal 24, and the input / output terminal 24 may be damaged such as a crack. As a result, the inside of the package cannot be kept airtight. There is a problem that the semiconductor element 25 does not operate normally.

従って、本発明は上記問題点に鑑み完成されたものであり、その目的は、半導体素子から発生する熱を効率よく外部へ放散させて半導体素子の温度上昇を抑制し、半導体素子を長期にわたり正常かつ安定に作動させ得るとともに、セラミックスから成る枠体にクラック等の破損が発生しない半導体素子収納用パッケージおよび半導体装置を提供することにある。   Accordingly, the present invention has been completed in view of the above problems, and its purpose is to efficiently dissipate the heat generated from the semiconductor element to the outside to suppress the temperature rise of the semiconductor element, and to normalize the semiconductor element over a long period of time. Another object of the present invention is to provide a semiconductor element housing package and a semiconductor device that can be stably operated and that do not cause breakage such as cracks in a frame made of ceramics.

本発明の半導体素子収納用パッケージは、上側主面に半導体素子が載置される直方体状の凸部が形成された長板状の金属製の基体と、内外を導通させるための配線導体を有するとともに前記基体の前記上側主面に前記凸部を囲繞するようにロウ付けされたセラミックスから成る枠体とを具備しており、前記基体は、前記凸部の周囲の厚みが0.1〜0.3ｍｍであり、前記基体の両短辺側において前記凸部の側面と前記枠体の内面との間に、前記凸部の長辺の長さの0.03乃至0.2倍の隙間が設けられていることを特徴とする。   A package for housing a semiconductor element of the present invention has a long plate-like metal base body having a rectangular parallelepiped convex portion on which a semiconductor element is placed on the upper main surface, and a wiring conductor for conducting the inside and outside. And a frame made of ceramic brazed so as to surround the convex portion on the upper main surface of the base body, and the base body has a thickness around the convex portion of 0.1 to 0.3 mm. And a gap 0.03 to 0.2 times the length of the long side of the convex portion is provided between the side surface of the convex portion and the inner surface of the frame body on both short sides of the base body. And

本発明の半導体素子収納用パッケージにおいて、好ましくは、前記基体は、銅または銅を主成分とする合金にセラミック粉末を含有させて成ることを特徴とする。   In the package for housing a semiconductor element of the present invention, it is preferable that the base is made of copper or an alloy containing copper as a main component containing ceramic powder.

本発明の半導体装置は、上記構成の半導体素子収納用パッケージと、前記凸部に載置されるとともに前記配線導体に電気的に接続された半導体素子と、前記枠体の上面に取着された蓋体とを具備していることを特徴とする。   The semiconductor device according to the present invention is mounted on the upper surface of the frame body, the semiconductor element housing package having the above-described configuration, the semiconductor element placed on the convex portion and electrically connected to the wiring conductor. And a lid.

また、本発明の半導体装置は、上記構成の半導体素子収納用パッケージと、前記凸部に載置されるとともに前記配線導体に電気的に接続された半導体素子と、この半導体素子を覆う外装樹脂とを具備していることを特徴とする。   According to another aspect of the present invention, there is provided a semiconductor device housing package having the above structure, a semiconductor device mounted on the convex portion and electrically connected to the wiring conductor, and an exterior resin covering the semiconductor device. It is characterized by comprising.

本発明の半導体素子収納用パッケージは、上側主面に半導体素子が載置される直方体状の凸部が形成された長板状の金属製の基体と、内外を導通させるための配線導体を有するとともに基体の上側主面に凸部を囲繞するようにロウ付けされたセラミックスから成る枠体とを具備しており、基体は、凸部の周囲の厚みが0.1〜0.3ｍｍであり、基体の両短辺側において凸部の側面と枠体の内面との間に、凸部の長辺の長さの0.03〜0.2倍の隙間が設けられていることから、基体の凸部の周囲の厚みが0.1〜0.3ｍｍである部分の、凸部の側面と枠体とに挟まれた隙間領域において金属製の基体を変形させ易くすることができ、基体と枠体とがロウ付けされることによって枠体に生ずる歪みをこの隙間領域で吸収させることができる。従って、基体に熱膨張係数の高い材料を用いても、セラミックスから成る枠体にクラック等の破損が生じ難くなり、半導体素子収納用パッケージの内部を気密に保持することができるようになる。   A package for housing a semiconductor element of the present invention has a long plate-like metal base body having a rectangular parallelepiped convex portion on which a semiconductor element is placed on the upper main surface, and a wiring conductor for conducting the inside and outside. And a frame body made of ceramic brazed so as to surround the convex portion on the upper main surface of the base body, and the base body has a thickness around the convex portion of 0.1 to 0.3 mm. Since a gap of 0.03 to 0.2 times the length of the long side of the convex portion is provided between the side surface of the convex portion and the inner surface of the frame body on the short side, the thickness around the convex portion of the base is The base made of metal can be easily deformed in the gap region between the side surface of the convex portion and the frame, which is 0.1 to 0.3 mm, and the frame is formed by brazing the base and the frame. The strain generated in the body can be absorbed in this gap region. Therefore, even if a material having a high thermal expansion coefficient is used for the substrate, breakage such as cracks hardly occurs in the frame body made of ceramics, and the inside of the semiconductor element housing package can be held airtight.

また、高熱伝導率であって熱膨張率が大きい材料でも基体に使用することができるので、半導体素子から発生する熱を効率よく外部へ放散させて半導体素子の温度上昇を抑制し、半導体素子を長期にわたり正常かつ安定に作動させ得る半導体素子収納用パッケージとすることができる。   In addition, since a material having a high thermal conductivity and a high thermal expansion coefficient can be used for the substrate, the heat generated from the semiconductor element is efficiently dissipated to the outside, and the temperature rise of the semiconductor element is suppressed. A package for housing a semiconductor element that can be operated normally and stably over a long period of time can be obtained.

本発明の半導体素子収納用パッケージにおいて、好ましくは、基体は、銅または銅を主成分とする合金にセラミック粉末を含有させて成ることから、基体の熱伝導率が高く、半導体素子の発した熱を外部や大気中に良好に放散させることができ、さらに、基体がセラミック粉末を含有させて成ることにより基体の剛性が増すとともに、基体の熱膨張係数が枠体の熱膨張係数に近づき、枠体に作用する基体との熱膨張差による応力を小さくすることができ、枠体にクラック等の破損が生ずるのを有効に防止することができる。また、基体に生ずる歪みを少なくして、基体の凸部の上側主面を平坦に保つことができる。その結果、半導体素子の発した熱を外部や大気中に良好に放散させることができるとともに、内部を気密に保持することができて半導体素子を長期間にわたり正常かつ安定に作動させることができる半導体素子収納用パッケージとすることができる。   In the package for housing a semiconductor element of the present invention, preferably, the base body is made of copper or an alloy containing copper as a main component, and ceramic powder is contained therein, so that the base body has high thermal conductivity and the heat generated by the semiconductor element. Can be satisfactorily diffused to the outside and the atmosphere. Further, the substrate is made of ceramic powder, so that the rigidity of the substrate is increased and the coefficient of thermal expansion of the substrate approaches the coefficient of thermal expansion of the frame. The stress due to the difference in thermal expansion with the substrate acting on the body can be reduced, and breakage such as cracks can be effectively prevented from occurring in the frame. Further, the distortion generated in the base can be reduced, and the upper main surface of the convex portion of the base can be kept flat. As a result, the semiconductor element can dissipate the heat generated by the semiconductor element to the outside or the atmosphere, and the inside can be kept airtight so that the semiconductor element can operate normally and stably over a long period of time. An element storage package can be obtained.

本発明の半導体装置は、上記構成の半導体素子収納用パッケージと、凸部に載置されるとともに配線導体に電気的に接続された半導体素子と、枠体の上面に取着された蓋体とを具備していることにより、上記本発明の半導体素子収納用パッケージによって放熱性に優れ、半導体素子の動作信頼性の高いものとなる。   A semiconductor device according to the present invention includes a semiconductor element storage package having the above-described configuration, a semiconductor element placed on the convex portion and electrically connected to the wiring conductor, and a lid attached to the upper surface of the frame. By providing the semiconductor element housing package of the present invention, the heat dissipation is excellent and the operation reliability of the semiconductor element is high.

本発明の半導体装置は、上記構成の半導体素子収納用パッケージと、凸部に載置されるとともに配線導体に電気的に接続された半導体素子と、半導体素子を覆う外装樹脂とを具備していることにより、外層樹脂によって半導体素子が外気から保護され、上記本発明の半導体素子収納用パッケージによって放熱性に優れる、半導体素子の動作信頼性の高いものとなる。   A semiconductor device of the present invention includes a semiconductor element housing package having the above-described configuration, a semiconductor element placed on a convex portion and electrically connected to a wiring conductor, and an exterior resin covering the semiconductor element. As a result, the semiconductor element is protected from the outside air by the outer layer resin, and the semiconductor element storage package of the present invention has excellent heat dissipation and high operation reliability of the semiconductor element.

本発明の半導体素子収納用パッケージについて以下に詳細に説明する。図１は本発明のパッケージの実施の形態の一例を示す平面図、図２は図１のパッケージの断面図である。これらの図において、１は基体、２は枠体を示し、これら基体１、枠体２で、内部空間に半導体素子３を収容する容器が基本的に構成される。   The semiconductor element storage package of the present invention will be described in detail below. FIG. 1 is a plan view showing an example of an embodiment of the package of the present invention, and FIG. 2 is a cross-sectional view of the package of FIG. In these drawings, reference numeral 1 denotes a base body, and 2 denotes a frame body. The base body 1 and the frame body 2 basically constitute a container for housing the semiconductor element 3 in the internal space.

本発明のパッケージは、図１および図２に示すように、上側主面に半導体素子３が載置される直方体状の凸部１ａが形成された長板状の金属製の基体１と、内外を導通させるための配線導体２ａを有するとともに基体１の上側主面に凸部１ａを囲繞するようにロウ付けされたセラミックスから成る枠体２とを具備しており、基体１は、凸部の周囲の厚みＡが0.1〜0.3ｍｍであり、基体１の両短辺側において凸部１ａの側面と枠体２の内面との間に、凸部１ａの長辺の長さＣの0.03〜0.2倍の長さ（幅）Ｂの隙間が設けられている。   As shown in FIGS. 1 and 2, the package of the present invention includes a long plate-shaped metal base 1 having a rectangular parallelepiped convex portion 1a on which the semiconductor element 3 is placed on the upper main surface, and an inner and outer surfaces. And a frame body 2 made of ceramics brazed so as to surround the convex portion 1a on the upper main surface of the base body 1, and the base body 1 has a convex portion. The surrounding thickness A is 0.1 to 0.3 mm, and the length C of the long side of the convex portion 1a is 0.03 to 0.2 between the side surface of the convex portion 1a and the inner surface of the frame 2 on both short sides of the base body 1. A gap of double length (width) B is provided.

本発明の基体１は、無酸素Ｃｕ，Ｃｕ−モリブデン（Ｍｏ）合金，ＣｕまたはＣｕを主成分とする合金にセラミック粉末を含有させて成る材料等のＣｕ系材料やＦｅ−Ｎｉ−Ｃｏ合金、Ｆｅ−Ｎｉ合金等の金属から成る。特に、基体１の熱伝導性をよくして内部に収容する半導体素子３から発生した熱を効率よく外部へ放散させるという観点からは、高熱伝導性のＣｕ系材料（ＣｕまたはＣｕを主成分とする合金）が好ましい。   The substrate 1 of the present invention includes an oxygen-free Cu, Cu-molybdenum (Mo) alloy, Cu-based material such as Cu or a material containing a ceramic powder in an alloy containing Cu as a main component, an Fe-Ni-Co alloy, It consists of metals, such as a Fe-Ni alloy. In particular, from the viewpoint of improving the thermal conductivity of the substrate 1 and efficiently dissipating the heat generated from the semiconductor element 3 accommodated therein, the Cu-based material having high thermal conductivity (Cu or Cu as a main component). Alloy).

さらに好ましくは、基体１は、ＣｕまたはＣｕを主成分とする合金にセラミック粉末を含有させて成るものがよい。この構成により、基体１の熱伝導率が高く、半導体素子３の発した熱を外部や大気中に良好に放散させることができ、さらに、基体１がセラミック粉末を含有させて成ることにより基体１の剛性が増すとともに、基体１の熱膨張係数が枠体２の熱膨張係数に近づき、基体１との熱膨張差により枠体２に作用する応力が低減されるので、枠体２にクラック等の破損が生じ難くなる。   More preferably, the substrate 1 is made of a ceramic powder contained in Cu or an alloy containing Cu as a main component. With this configuration, the heat conductivity of the substrate 1 is high, the heat generated by the semiconductor element 3 can be dissipated well to the outside or the atmosphere, and the substrate 1 is made of ceramic powder by containing the ceramic powder. Since the thermal expansion coefficient of the base body 1 approaches the thermal expansion coefficient of the frame body 2 and the stress acting on the frame body 2 due to the difference in thermal expansion from the base body 1 is reduced, the frame body 2 is cracked. Is less likely to break.

また、基体１と枠体２との熱膨張差が小さくなることにより基体１に生じる歪みも小さくなるので、基体１の凸部１ａの上側主面を平坦に保つことができる。その結果、パッケージは、半導体素子３が基体１に強固に接合され、半導体素子３の発した熱を外部や大気中に良好に放散することができ、内部の気密信頼性が高くて半導体素子３を長期間にわたり正常かつ安定に作動させることができる。   In addition, since the difference in thermal expansion between the base body 1 and the frame body 2 is reduced, distortion generated in the base body 1 is also reduced, so that the upper main surface of the convex portion 1a of the base body 1 can be kept flat. As a result, the semiconductor element 3 is firmly bonded to the base 1 in the package, the heat generated by the semiconductor element 3 can be dissipated well to the outside or the atmosphere, the internal airtight reliability is high, and the semiconductor element 3 Can be operated normally and stably over a long period of time.

このような基体１は、金属や合金から成る場合、金属のインゴットに圧延加工や打ち抜き加工等の従来周知の金属加工法を施すことによって所定形状に製作される。   When the base 1 is made of a metal or an alloy, the base 1 is manufactured in a predetermined shape by applying a conventionally known metal processing method such as rolling or punching to a metal ingot.

また基体１がＣｕまたはＣｕの含有率が70％質量％以上のＣｕを主成分とする合金にセラミック粉末を含有させて成る場合、基体１には、ＣｕまたはＣｕを主成分とする合金にＡｌ２Ｏ３質焼結体，ＡｌＮ質焼結体，炭化珪素（ＳｉＣ）質焼結体，窒化珪素（Ｓｉ３Ｎ４）質焼結体等のセラミック粉末が含有されている。ＣｕまたはＣｕを主成分とする合金にセラミック粉末を含有させることにより、高熱伝導性であるとともに熱膨張係数は含有されるセラミックスに近いものとすることができ、例えば、銅に0.1〜２質量％のＡｌ２Ｏ３質焼結体を含有させて成る場合は、熱伝導率が350Ｗ／ｍ・Ｋ〜360Ｗ／ｍ・Ｋ，熱膨張係数が16×10-6〜17×10-6の基体１が得られる。Ａｌ２Ｏ３質焼結体の含有量を増やせば、さらに熱膨張係数の低い基体１が得られ、例えば10質量％含有させることによって熱膨張係数が14×10-6程度の銅にＡｌ２Ｏ３質焼結体を含有させた基体１が得られる。 Further, when the substrate 1 is made of a ceramic powder containing Cu or an alloy containing Cu as a main component with a Cu content of 70% by mass or more, the substrate 1 contains Al or an alloy containing Cu or Cu as the main component. Ceramic powders such as a 2 O 3 sintered body, an AlN sintered body, a silicon carbide (SiC) sintered body, a silicon nitride (Si 3 N 4 ) sintered body are contained. By including ceramic powder in Cu or an alloy containing Cu as a main component, it is possible to make the thermal expansion coefficient close to that of the contained ceramics with high thermal conductivity, for example, 0.1 to 2 mass% in copper. In the case of containing an Al 2 O 3 sintered body, a base having a thermal conductivity of 350 W / m · K to 360 W / m · K and a thermal expansion coefficient of 16 × 10 −6 to 17 × 10 −6 1 is obtained. If the content of the Al 2 O 3 sintered material is increased, the base 1 having a lower thermal expansion coefficient can be obtained. For example, by containing 10% by mass, copper having a thermal expansion coefficient of about 14 × 10 −6 is added to Al 2. A substrate 1 containing an O 3 -based sintered body is obtained.

ＣｕまたはＣｕ合金にセラミック粉末を含有させるには、例えば、Ａｌ２Ｏ３質焼結体を含有して成る場合は、Ａｌ２Ｏ３，酸化珪素（ＳｉＯ２），酸化マグネシウム（ＭｇＯ），酸化カルシウム（ＣａＯ）等の原料粉末に適当な有機バインダ，溶剤，可塑剤，分散剤等を混合添加して顆粒状の混合物と成し、約1600℃で焼成して得られたセラミックス粉末の表面に金属層を被着させた後に、これを加圧成形して基体１の所定形状にしたセラミックス多孔体を得、しかる後に、このセラミックス多孔体に非酸化雰囲気下において約1100℃で銅または銅を主成分とする合金を含浸させることによって、基体１の銅または銅を主成分とする合金が５〜70質量％の基体１を得ることができる。 In order to contain ceramic powder in Cu or Cu alloy, for example, in the case of containing an Al 2 O 3 sintered body, Al 2 O 3 , silicon oxide (SiO 2 ), magnesium oxide (MgO), oxidation An appropriate organic binder, solvent, plasticizer, dispersant, etc. are mixed and added to raw powder such as calcium (CaO) to form a granular mixture, which is then fired at about 1600 ° C on the surface of the ceramic powder. After depositing the metal layer, this is pressure-molded to obtain a ceramic porous body having a predetermined shape of the substrate 1, and then copper or copper is applied to the ceramic porous body at about 1100 ° C. in a non-oxidizing atmosphere. By impregnating the alloy having the main component, the base 1 having 5 to 70% by mass of the copper of the base 1 or the alloy containing copper as the main component can be obtained.

または、約1600℃で焼成して得られたセラミックス粉末と、銅または銅を主成分とする合金の金属粉末と、有機バインダおよび溶剤とを混練させ、これを加圧成形して基体１の所定形状にしたものを得、しかる後に、非酸化雰囲気下において約800℃で有機バインダおよび溶剤とを熱分解させて除去し、その後に、非酸化雰囲気下において約1100℃で銅または銅を主成分とする合金を溶融させて有機バインダおよび溶剤を除去することによって形成された空孔を埋めこむことで、基体１の銅または銅を主成分とする合金の質量比が70〜99.9質量％の基体１を得ることができる。   Alternatively, ceramic powder obtained by firing at about 1600 ° C., metal powder of copper or an alloy containing copper as a main component, an organic binder and a solvent are kneaded, and this is pressure-molded to form a predetermined substrate 1. After obtaining the shape, the organic binder and solvent are thermally decomposed and removed at about 800 ° C. in a non-oxidizing atmosphere, and then copper or copper as a main component at about 1100 ° C. in a non-oxidizing atmosphere By filling the voids formed by melting the alloy to be removed and removing the organic binder and solvent, the base body has a mass ratio of 70 to 99.9% by mass of copper or copper-based alloy as a main component 1 can be obtained.

基体１がその他のセラミック粉末を含有して成る場合も同様にして得ることができる。   When the substrate 1 contains other ceramic powder, it can be obtained in the same manner.

ここで、基体１は、凸部１ａが厚み0.5〜２ｍｍ、長辺８〜20ｍｍ、短辺１〜３ｍｍ程度とされ、凸部１ａの周囲に厚さ0.1〜0.3ｍｍの鍔状の部分（厚さＡの部分）が設けられている。   Here, the base 1 has a convex portion 1a having a thickness of 0.5 to 2 mm, a long side of 8 to 20 mm, and a short side of about 1 to 3 mm, and has a bowl-shaped portion (thickness of 0.1 to 0.3 mm) around the convex portion 1a. A portion) is provided.

基体１の上側主面の中央部には、半導体素子３を載置する凸部１ａが設けられている。この基体１は、半導体素子３が作動時に発する熱を外部に放熱させる放熱板の役割をも果たす。基体１の表面には、酸化腐食の防止や半導体素子３のロウ付け等による載置固定を良好にするために、厚さ0.5〜９μｍのＮｉ層や厚さ0.5〜５μｍの金（Ａｕ）層から成る金属層をめっき法等により被着させておくとよい。また、半導体素子３の熱を効率よく外部へ放熱させるために、半導体素子３がペルチェ素子等の熱電冷却素子（図示せず）に搭載された状態で凸部１ａに載置固定されていてもよい。   A convex portion 1 a on which the semiconductor element 3 is placed is provided at the central portion of the upper main surface of the base 1. The base body 1 also serves as a heat radiating plate for radiating heat generated when the semiconductor element 3 is operated to the outside. On the surface of the base 1, a Ni layer having a thickness of 0.5 to 9 μm or a gold (Au) layer having a thickness of 0.5 to 5 μm is used to prevent oxidative corrosion and to improve the mounting and fixing by brazing the semiconductor element 3. It is good to deposit the metal layer which consists of these by the plating method etc. Further, in order to efficiently dissipate the heat of the semiconductor element 3 to the outside, even if the semiconductor element 3 is mounted and fixed on the convex portion 1a while being mounted on a thermoelectric cooling element (not shown) such as a Peltier element. Good.

また、基体１の上側主面の凸部１ａの周囲には、凸部１ａを囲繞するようにしてＡｇロウやＡｇ−Ｃｕロウ等のロウ材を介して接合されるとともに、上方の所定部に線路導体２ａを有するセラミックスから成る枠体２が立設されており、枠体２は基体１とともにその内側に半導体素子３を収容する空所を形成する役割を果たす。   In addition, the periphery of the convex portion 1a on the upper main surface of the base body 1 is joined via a brazing material such as Ag brazing or Ag-Cu brazing so as to surround the convex portion 1a, and at a predetermined upper portion. A frame body 2 made of ceramics having a line conductor 2a is erected, and the frame body 2 plays a role of forming a space for accommodating the semiconductor element 3 inside thereof together with the base body 1.

枠体２は、Ａｌ２Ｏ３質焼結体，ＡｌＮ質焼結体，３Ａｌ２Ｏ３・２ＳｉＯ２質焼結体等のセラミックスから成り、例えばＡｌ２Ｏ３質焼結体から成る場合以下のようにして作製される。すなわち、アルミナ（Ａｌ２Ｏ３），酸化珪素（ＳｉＯ２），酸化マグネシウム（ＭｇＯ），酸化カルシウム（ＣａＯ）等の原料粉末に適当な有機バインダ，有機溶剤，可塑剤，分散剤等を添加混合してスラリー状となし、これを従来周知のドクターブレード法によってシート状となすことにより、複数枚のセラミックグリーンシートを得る。 Frame 2, Al 2 O 3 sintered material, AlN sintered material consists 3Al 2 O 3 · 2SiO 2 Quality sintered body or the like of the ceramics, for example, the following case of Al 2 O 3 quality sintered body It is produced as follows. That is, an appropriate organic binder, organic solvent, plasticizer, dispersant, etc. are added to and mixed with raw material powders such as alumina (Al 2 O 3 ), silicon oxide (SiO 2 ), magnesium oxide (MgO), and calcium oxide (CaO). Then, a plurality of ceramic green sheets are obtained by forming a slurry and forming this into a sheet by a conventionally known doctor blade method.

次に、このセラミックグリーンシートに枠体２の内側面や外側面となる適当な打抜き加工を施すとともに、Ｗ，Ｍｏ，マンガン（Ｍｎ）等の金属粉末に適当なバインダ，溶剤を混合してなる導体ペーストを、セラミックグリーンシートにスクリーン印刷法等により所定パターンに印刷塗布することによって、半導体素子３の電極と電気的に接続される線路導体２ａ等となる導体層を形成する。また、枠体２の上面および底面となるセラミッククリーンシートにはロウ付け用の導体層が形成される。その後、これらのセラミックグリーンシートを所定の順序で積層した後、所定の寸法に切断し、最後に約1600℃の温度で焼成することによって、線路導体２ａ等の導体層を有した枠体２となる焼結体を作製することができる。   Next, the ceramic green sheet is subjected to an appropriate punching process for forming the inner surface and the outer surface of the frame 2, and an appropriate binder and solvent are mixed with metal powder such as W, Mo, manganese (Mn). The conductor paste is printed and applied in a predetermined pattern to the ceramic green sheet by a screen printing method or the like, thereby forming a conductor layer that becomes the line conductor 2a or the like electrically connected to the electrode of the semiconductor element 3. In addition, a brazing conductor layer is formed on the ceramic clean sheet serving as the top and bottom surfaces of the frame 2. Thereafter, these ceramic green sheets are laminated in a predetermined order, cut into predetermined dimensions, and finally fired at a temperature of about 1600 ° C., whereby the frame 2 having a conductor layer such as the line conductor 2a and the like A sintered body can be produced.

線路導体２ａは、枠体２の内側となる部分で、ボンディングワイヤ６を介して半導体素子３の電極と電気的に接続され、枠体２の外側となる部分で、ＡｇロウやＡｇ−Ｃｕロウ等のロウ材を介して接合されたＦｅ−Ｎｉ−Ｃｏ合金等の金属から成るリード端子７を介して外部電気回路に電気的に接続される。そして、リード端子７は、外部電気回路（図示せず）から供給される電気信号を半導体素子３に伝えて半導体素子３を駆動させるとともに、半導体素子３と外部電気回路との信号の入出力を行なう。線路導体２ａの表面は、酸化腐食を防止するためやボンディングワイヤ６およびリード端子７との接合強度を高めるため、表面に厚さ0.5〜９μｍのＮｉ層や厚さ0.5〜５μｍのＡｕ層等の金属層がめっき法によって被着されているのがよい。   The line conductor 2 a is a portion inside the frame body 2 and is electrically connected to the electrodes of the semiconductor element 3 via the bonding wires 6, and is a portion outside the frame body 2 where Ag solder or Ag—Cu solder is used. It is electrically connected to an external electric circuit through a lead terminal 7 made of a metal such as Fe—Ni—Co alloy joined through a brazing material such as. The lead terminal 7 transmits an electric signal supplied from an external electric circuit (not shown) to the semiconductor element 3 to drive the semiconductor element 3 and input / output signals between the semiconductor element 3 and the external electric circuit. Do. The surface of the line conductor 2a is made of a Ni layer having a thickness of 0.5 to 9 μm, an Au layer having a thickness of 0.5 to 5 μm, or the like on the surface in order to prevent oxidative corrosion or to increase the bonding strength between the bonding wire 6 and the lead terminal 7. The metal layer is preferably deposited by a plating method.

また、基体１の枠体２とのロウ付けされる部分の厚みＡが0.1〜0.3ｍｍであり、基体１の両短辺側において凸部１ａの側面と枠体２の内面との間に、凸部１ａの長辺の長さＣの0.03〜0.2倍の長さＢの隙間が設けられている。基体１の凸部１ａの周囲の厚みが0.1〜0.3ｍｍである部分の、凸部１ａの側面と枠体２とに挟まれた隙間領域において金属製の基体１を変形させ易くすることができ、基体１と枠体２とがロウ付けされることによって、枠体２に生ずる歪みをこの隙間領域で吸収させることができる。従って、基体１に無酸素Ｃｕ，Ｃｕ−Ｍｏ合金等の熱膨張係数が高く熱伝導性のよい材料を用いても、セラミックスから成る枠体２にクラック等の破損が生じ難くなり、パッケージの内部を気密に保持することができるようになる。   Further, the thickness A of the portion to be brazed with the frame body 2 of the base body 1 is 0.1 to 0.3 mm, and between the side surface of the convex portion 1a and the inner surface of the frame body 2 on both short sides of the base body 1, A gap having a length B that is 0.03 to 0.2 times the length C of the long side of the convex portion 1a is provided. The metal base 1 can be easily deformed in a gap region sandwiched between the side surface of the convex portion 1a and the frame body 2 at a portion where the thickness around the convex portion 1a of the base 1 is 0.1 to 0.3 mm. Since the base body 1 and the frame body 2 are brazed, distortion generated in the frame body 2 can be absorbed in this gap region. Therefore, even if a material having a high thermal expansion coefficient, such as oxygen-free Cu, Cu—Mo alloy, and the like having a good thermal conductivity is used for the base body 1, the frame body 2 made of ceramic is less likely to be damaged such as cracks. Can be kept airtight.

Ａ＜0.1ｍｍとなると、基体１の厚みが薄くなりすぎて、枠体２が基体１に接合されるときに基体１が反り等の変形を起こし易くなり、その結果、基体１の下側主面を外部電気回路基板に密着できなくなり、半導体素子３から発熱する熱を基体１を介して外部に良好に放散できなくなる。Ａ＞0.3ｍｍとなると、基体１が変形し難くなり、基体１と枠体２とをロウ付けする際に基体１で歪みを十分に吸収できず枠体２にクラック等の破損を生じさせてしまう場合がある。   When A <0.1 mm, the thickness of the substrate 1 becomes too thin, and the substrate 1 is likely to be deformed such as warping when the frame body 2 is joined to the substrate 1. The surface cannot be brought into close contact with the external electric circuit board, and the heat generated from the semiconductor element 3 cannot be dissipated well through the base 1. When A> 0.3 mm, the base body 1 becomes difficult to deform, and when the base body 1 and the frame body 2 are brazed, the base body 1 cannot sufficiently absorb the distortion, and the frame body 2 is damaged such as cracks. May end up.

また、Ｂ＜0.03Ｃとなると、凸部１ａの側面と枠体２の内面との間の寸法が小さくなりすぎて、基体１と枠体２とがロウ付けされることによって枠体２に生ずる歪みを吸収できなくなり、枠体２にクラック等の破損を生じさせてしまう場合がある。すなわち、基体１と枠体２との熱膨張係数差によって、枠体２の下面の内周側に基体１の大きな収縮により引張応力が加わり、枠体２の下面の内周側にクラックが発生し易くなる。Ｂ＞0.2Ｃとなると、基体１全体に占める凸部１ａの周囲の厚みＡの部分が多くなり、枠体２が基体１に接合されるときに基体１が反り等の変形を起こし易くなり、その結果、基体１の下側主面を外部電気回路基板に密着できなくなり、半導体素子３から発熱する熱を基体１を介して外部に良好に放散できなくなる。   Further, when B <0.03C, the dimension between the side surface of the convex portion 1a and the inner surface of the frame body 2 becomes too small, and the base body 1 and the frame body 2 are brazed to be generated in the frame body 2. The strain cannot be absorbed, and the frame 2 may be damaged such as a crack. That is, due to the difference in thermal expansion coefficient between the base body 1 and the frame body 2, tensile stress is applied to the inner peripheral side of the lower surface of the frame body 2 due to the large shrinkage of the base body 1, and cracks are generated on the inner peripheral side of the lower surface of the frame body 2. It becomes easy to do. When B> 0.2C, the portion of the thickness A around the convex portion 1a occupying the entire base body 1 is increased, and the base body 1 is likely to be deformed such as warping when the frame 2 is joined to the base body 1, As a result, the lower main surface of the base body 1 cannot be adhered to the external electric circuit board, and the heat generated from the semiconductor element 3 cannot be dissipated well through the base body 1.

そして、図２に示すように、上記構成のパッケージの凸部１ａに半導体素子３を載置固定した後、半導体素子３の電極と線路導体２ａの枠体２の内側の部位とをボンディングワイヤ６で電気的に接続し、枠体２の上面にＦｅ−Ｎｉ−Ｃｏ合金等の金属や枠体２と同じセラミックスから成る蓋体４を半田付け法や溶接法等により取着し、半導体素子３を気密に封止することで製品としての半導体装置となる。なおこの場合、図２に示すように、枠体２の線路導体２ａの上部に、線路導体２ａの一部を挟み込むようにして凸部２ｂを形成する。これにより、線路導体２ａの枠体２内側の部位にボンディングワイヤ６を接続するための空間を確保するとともに、線路導体２と蓋体４とが電気的に短絡するのを防止できる。   Then, as shown in FIG. 2, after the semiconductor element 3 is placed and fixed on the projecting portion 1a of the package having the above-described configuration, the bonding wire 6 connects the electrode of the semiconductor element 3 and the portion inside the frame 2 of the line conductor 2a. The lid 4 made of a metal such as an Fe—Ni—Co alloy or the same ceramic as the frame 2 is attached to the upper surface of the frame 2 by a soldering method, a welding method, or the like. By sealing hermetically, a semiconductor device as a product is obtained. In this case, as shown in FIG. 2, a convex portion 2b is formed on the upper portion of the line conductor 2a of the frame 2 so as to sandwich a part of the line conductor 2a. Thereby, while ensuring the space for connecting the bonding wire 6 to the site | part inside the frame 2 of the line conductor 2a, it can prevent that the line conductor 2 and the cover body 4 electrically short-circuit.

または、図３に示すように、半導体素子３をエポキシ樹脂系の外装樹脂５によって覆い、半導体素子３を気密に封止することにより、製品としての本発明の半導体装置となる。なお、基体１と枠体２との隙間に外装樹脂５を充填させることによって、パッケージと外装樹脂５との密着強度を向上させることができる。   Alternatively, as shown in FIG. 3, the semiconductor element 3 is covered with an epoxy resin-based exterior resin 5 and the semiconductor element 3 is hermetically sealed, whereby the semiconductor device of the present invention as a product is obtained. In addition, the adhesion strength between the package and the exterior resin 5 can be improved by filling the exterior resin 5 in the gap between the base body 1 and the frame body 2.

本発明の半導体装置によれば、上記構成のパッケージを用いることによって放熱性に優れ、半導体素子３の動作信頼性の高い半導体装置とすることができる。   According to the semiconductor device of the present invention, by using the package having the above-described configuration, a semiconductor device having excellent heat dissipation and high operation reliability of the semiconductor element 3 can be obtained.

本発明の半導体素子収納用パッケージの実施例を以下に説明する。   Embodiments of the semiconductor element storage package of the present invention will be described below.

図１の本発明のパッケージのサンプルを以下のようにして作製した。無酸素Ｃｕから成り縦9.1ｍｍ×横1.55ｍｍで厚さが 0.7mmの凸部１ａの周囲に厚さ0.15ｍｍの鍔状部分が形成された外形が縦10.6ｍｍ×横2.25ｍｍの長板状の金属製の基体１を用意し、この上面に平面視での外側寸法が縦11.7ｍｍ×横3ｍｍで厚さが１mmのＡｌ２Ｏ３質焼結体から成り、平面視での内側寸法が縦9.3ｍｍ×横1.75ｍｍ、縦10.1ｍｍ×横1.75ｍｍの２種類の枠体２、すなわち隙間Ｂの長さが0.1および0.5ｍｍとなる２種類の枠体２を用意した。 A sample of the package of the present invention shown in FIG. 1 was produced as follows. A long plate shape of 10.6 mm in length × 2.25 mm in width, which is made of oxygen-free Cu and has a ridge of 9.1 mm in length, 1.55 mm in width, and 0.7 mm in thickness around the convex part 1a. A metal base 1 is prepared, and the upper surface is made of an Al 2 O 3 sintered body having an outer dimension in a plan view of 11.7 mm × a width of 3 mm and a thickness of 1 mm in a plan view, and an inner dimension in a plan view. Two types of frames 2 of 9.3 mm in length × 1.75 mm in width and 10.1 mm in length × 1.75 mm in width, that is, two types of frames 2 in which the length of the gap B is 0.1 and 0.5 mm were prepared.

基体１と内側面の寸法が縦9.3ｍｍ×横1.75ｍｍ、縦10.1ｍｍ×横1.75ｍｍの２種類の枠体２をそれぞれＡｇ−Ｃｕロウ（融点780℃）で接合し、これらを常温（25℃）まで均一に冷却することによりパッケージのサンプルを作製した。ここで、枠体２の内側面の寸法が縦9.3ｍｍ×横1.75ｍｍのパッケージのサンプルをＰ１（比較例）、枠体２の内側面の寸法が縦10.1ｍｍ×横1.75ｍｍのサンプルをＰ２（本発明の実施例）とする。   Two types of frame bodies 2 having dimensions of 9.3 mm in length × 1.75 mm in width and 10.1 mm in length × 1.75 mm in width are bonded to each of the base body 1 with Ag—Cu solder (melting point 780 ° C.), and these are joined at room temperature (25 The sample of the package was produced by uniformly cooling to (° C.). Here, P1 (a comparative example) is a package sample having an inner side dimension of 9.3 mm in length × 1.75 mm in width of the frame 2 and P2 is a sample in which the dimension of the inner side of frame 2 is 10.1 mm in length × 1.75 mm in width. (Example of the present invention).

これらのサンプルＰ１、Ｐ２について、常温まで均一に冷却した後、基体１および枠体２の表面を10倍の光学顕微鏡を用いて観察したところ、サンプルＰ１では枠体２にクラックの発生が確認されたが、サンプルＰ２では一切クラックの発生が確認されなかった。   About these samples P1 and P2, after uniformly cooling to normal temperature, when the surface of the base | substrate 1 and the frame 2 was observed using the 10 times optical microscope, generation | occurrence | production of a crack was confirmed in the frame 2 in the sample P1. However, no cracks were observed in sample P2.

さらに、これらのサンプルＰ１、Ｐ２について、常温まで均一に冷却した際の枠体２に発生する最大主応力を有限要素法解析によって求めたところ、サンプルＰ１では577ＭＰａとなり、サンプルＰ２では348ＭＰａとなった。   Furthermore, when the maximum principal stress generated in the frame 2 when these samples P1 and P2 were uniformly cooled to room temperature was obtained by finite element analysis, it was 577 MPa for sample P1 and 348 MPa for sample P2. .

従って、本発明のパッケージであるサンプルＰ２が枠体２のクラックの抑制に有効であることが判った。   Therefore, it was found that the sample P2 which is the package of the present invention is effective in suppressing cracks in the frame 2.

さらに、上記のサンプルＰ２において基体１の凸部１ａの周囲の厚さＡだけを0.08ｍｍ，0.1ｍｍ，0.2ｍｍ，0.25ｍｍ，0.3ｍｍ，0.32ｍｍと変えたものを作製した。基体１の厚さが0.08ｍｍのものをサンプルＰ21、0.1ｍｍのものをサンプルＰ22、0.2ｍｍのものをサンプルＰ23、0.25ｍｍのものをサンプルＰ24、0.3ｍｍのものをサンプルＰ25、0.32ｍｍのものをサンプルＰ26とした。これらのサンプルＰ21〜Ｐ26について、サンプルＰ２と同様にして、基体１と枠体２の表面を観察し、クラックの発生の有無を評価した。その評価結果を表１に示す。

Figure 2005159288
Further, the sample P2 was prepared by changing only the thickness A around the convex portion 1a of the base body 1 to 0.08 mm, 0.1 mm, 0.2 mm, 0.25 mm, 0.3 mm, and 0.32 mm. The substrate 1 having a thickness of 0.08 mm is sample P21, the sample having a thickness of 0.1 mm is sample P22, the sample having a thickness of 0.2 mm is sample P23, the sample having a thickness of 0.25 mm is sample P24, the sample having a thickness of 0.3 mm is a sample P25, and sample having a thickness of 0.32 mm Was designated as Sample P26. About these samples P21-P26, the surface of the base | substrate 1 and the frame 2 was observed similarly to sample P2, and the presence or absence of the generation | occurrence | production of a crack was evaluated. The evaluation results are shown in Table 1.
Figure 2005159288

表1より、サンプルＰ22〜Ｐ25ではクラックの発生が見られなかった。サンプルP21では基体１にクラックが発生し、サンプルＰ26では枠体２にクラックが発生し、パッケージ内部を気密に保持できない状態であった。従って、サンプルＰ22〜Ｐ25がパッケージとして機能し得るものとなることが判った。即ち、基体１の凸部１ａの周囲の厚さＡが0.1〜0.3ｍｍであればよいことが判った。   From Table 1, generation | occurrence | production of the crack was not seen by sample P22-P25. In sample P21, a crack occurred in the substrate 1, and in sample P26, a crack occurred in the frame 2 and the inside of the package could not be kept airtight. Therefore, it was found that the samples P22 to P25 can function as a package. That is, it was found that the thickness A around the convex portion 1a of the base body 1 should be 0.1 to 0.3 mm.

次に、無酸素Ｃｕから成り縦9.1ｍｍ×横1.55ｍｍで厚さが 0.7mmの凸部１ａの周囲に厚さ0.15ｍｍの鍔状部分が形成された外形が縦10.6ｍｍ×横2.25ｍｍの長板状の金属製の基体１を用意し、この上面に平面視での外側寸法が縦15ｍｍ×横３ｍｍで厚さが１mmのＡｌ２Ｏ３質焼結体から成り、平面視での内側寸法が縦9.6ｍｍ×横1.75ｍｍ，縦9.7ｍｍ×横1.75ｍｍ，縦11ｍｍ×横1.75ｍｍ，縦12ｍｍ×横1.75ｍｍ，縦12.7ｍｍ×横1.75ｍｍ，縦12.8ｍｍ×横1.75ｍｍの６種類の枠体２、すなわち隙間の長さＢおよび凸部の長辺の長さＣに対する隙間の長さＢの比率（括弧内に示す）が0.25ｍｍ（0.027），0.3ｍｍ（0.033），0.95（0.104），1.45ｍｍ（0.159），1.8ｍｍ（0.198），1.85ｍｍ（0.203）となる６種類の枠体２を用意した。これら６種類の枠体２をそれぞれＡｇ−Ｃｕロウ（融点780℃）で接合し、これらを常温（25℃）まで均一に冷却することによりパッケージのサンプルを作製した。 Next, the outer shape in which a hook-shaped portion having a thickness of 0.15 mm is formed around the convex portion 1a made of oxygen-free Cu and having a height of 9.1 mm × width of 1.55 mm and a thickness of 0.7 mm is 10.6 mm long × 2.25 mm wide. A long plate-like metal base 1 is prepared, and the upper surface thereof is made of an Al 2 O 3 sintered body having an outer dimension of 15 mm in length, 3 mm in width, and 1 mm in thickness in plan view. Dimensions are 9.6mm x 1.75mm x 9.7mm x 1.75mm x 11mm x 1.75mm x 12mm x 1.75mm x 12.7mm x 1.75mm x 12.8mm x 1.75mm x 6 The ratio of the gap length B to the frame body 2, that is, the gap length B and the long side length C of the convex portion (shown in parentheses) is 0.25 mm (0.027), 0.3 mm (0.033), 0.95 ( 0.104), 1.45 mm (0.159), 1.8 mm (0.198), and 1.85 mm (0.203) 6 types of frame bodies 2 were prepared. These six types of frame bodies 2 were joined with Ag-Cu solder (melting point 780 ° C.), respectively, and these were uniformly cooled to room temperature (25 ° C.) to prepare package samples.

ここで、枠体２の内側面の縦の寸法が9.6ｍｍのものをサンプルＰ201、縦9.7ｍｍのものをサンプルＰ202、縦11ｍｍのものをサンプルＰ203、縦12ｍｍのものをサンプルＰ204、縦12.7ｍｍのものをサンプルＰ205、縦12.8ｍｍのものをサンプルＰ206とした。   Here, sample P201 has a vertical dimension of 9.6 mm on the inner surface of frame 2, sample P202 has a length of 9.7 mm, sample P203 has a length of 11 mm, sample P204 has a length of 12 mm, sample P204 has a length of 12.7 mm The sample was designated as sample P205, and the sample having a length of 12.8 mm was designated as sample P206.

これらのサンプルＰ201〜Ｐ206について、常温まで均一に冷却した後、基体１と枠体２の表面を10倍の光学顕微鏡を用いて観察しクラックの発生の有無を評価するとともに、基体１下面の反り寸法を測定した。その評価結果を表２に示す。

Figure 2005159288
About these samples P201-P206, after cooling uniformly to normal temperature, while observing the surface of the base | substrate 1 and the frame 2 using a 10 time optical microscope, the presence or absence of the generation | occurrence | production of a crack was evaluated, and the curvature of the base | substrate 1 lower surface was carried out. Dimensions were measured. The evaluation results are shown in Table 2.
Figure 2005159288

表２より、サンプルＰ202〜Ｐ206ではクラックの発生が見られなかった。サンプルP201では枠体２にクラックが発生し、パッケージ内部を気密に保持できない状態であった。また、サンプルＰ206では、基体１の下面の反り寸法が0.05ｍｍを上回るものとなり、基体１の下面を外部電気回路基板等に密着させることができず、半導体素子３から発生する熱を外部に良好に放散できないものとなることが判った。即ち、基体１の下面の反り寸法が0.05ｍｍを上回るものとなると、半導体素子３が作動した際に基体１の温度が上昇し易く、基体１の温度上昇によって、半導体素子３が誤作動を起こしてしまう場合がある。一方、基体1の反り寸法が0.05ｍｍ以下のP205では半導体素子３が作動しても基体１の温度上昇が抑制され、半導体素子３の誤作動を確実に防止できるものとなった。従って、サンプルＰ202〜Ｐ205がパッケージとして機能し得るものとなることが判った。即ち、枠体２の内面と凸部１ａとの間に凸部１ａの長辺の長さCの0.03乃至0.2倍の隙間Bが設けられると有効であることが判った。   From Table 2, generation of cracks was not observed in samples P202 to P206. In sample P201, the frame 2 was cracked, and the inside of the package could not be kept airtight. Further, in sample P206, the warpage dimension of the lower surface of the substrate 1 exceeds 0.05 mm, and the lower surface of the substrate 1 cannot be brought into close contact with an external electric circuit board or the like, and the heat generated from the semiconductor element 3 is excellent outside. It was found that it would be impossible to dissipate. That is, if the warpage dimension of the lower surface of the substrate 1 exceeds 0.05 mm, the temperature of the substrate 1 tends to rise when the semiconductor element 3 operates, and the semiconductor element 3 malfunctions due to the temperature increase of the substrate 1. May end up. On the other hand, in P205 where the warp dimension of the substrate 1 is 0.05 mm or less, even if the semiconductor element 3 is operated, the temperature rise of the substrate 1 is suppressed, and the malfunction of the semiconductor element 3 can be surely prevented. Therefore, it was found that the samples P202 to P205 can function as a package. In other words, it has been found effective if a gap B of 0.03 to 0.2 times the length C of the long side of the convex portion 1a is provided between the inner surface of the frame 2 and the convex portion 1a.

なお、本発明は上記実施の形態および実施例に限定されるものではなく、本発明の要旨を逸脱しない範囲内で種々の変更を施すことは何等支障ない。   It should be noted that the present invention is not limited to the above-described embodiments and examples, and various modifications can be made without departing from the scope of the present invention.

本発明の半導体素子収納用パッケージの実施の形態の一例を示す平面図である。It is a top view which shows an example of embodiment of the package for semiconductor element accommodation of this invention. 本発明の半導体素子収納用パッケージおよび半導体装置の実施の形態の一例を示す断面図である。It is sectional drawing which shows an example of embodiment of the package for semiconductor element accommodation of this invention, and a semiconductor device. 本発明の半導体装置の実施の形態の他の例を示す断面図である。It is sectional drawing which shows the other example of embodiment of the semiconductor device of this invention. 従来の半導体素子収納用パッケージの例を示す断面図である。It is sectional drawing which shows the example of the conventional package for semiconductor element accommodation.

符号の説明Explanation of symbols

１：基体
１ａ：凸部
２：枠体
２ａ：配線導体
３：半導体素子
４：蓋体
５：外装樹脂 1: Base 1a: Projection 2: Frame 2a: Wiring conductor 3: Semiconductor element 4: Lid 5: Exterior resin

Claims (4)

上側主面に半導体素子が載置される直方体状の凸部が形成された長板状の金属製の基体と、内外を導通させるための配線導体を有するとともに前記基体の前記上側主面に前記凸部を囲繞するようにロウ付けされたセラミックスから成る枠体とを具備しており、前記基体は、前記凸部の周囲の厚みが０．１〜０．３ｍｍであり、前記基体の両短辺側において前記凸部の側面と前記枠体の内面との間に、前記凸部の長辺の長さの０．０３乃至０．２倍の隙間が設けられていることを特徴とする半導体素子収納用パッケージ。 A long plate-shaped metal base on which a rectangular parallelepiped convex portion on which a semiconductor element is placed is formed on the upper main surface, a wiring conductor for conducting inside and outside, and the upper main surface of the base on the upper main surface A frame made of ceramic brazed so as to surround the convex portion, and the base has a thickness of 0.1 to 0.3 mm around the convex portion, A semiconductor having a gap 0.03 to 0.2 times the length of the long side of the convex portion between the side surface of the convex portion and the inner surface of the frame body on the side side Package for element storage. 前記基体は、銅または銅を主成分とする合金にセラミック粉末を含有させて成ることを特徴とする請求項１記載の半導体素子収納用パッケージ。 2. The package for housing a semiconductor element according to claim 1, wherein the base is made of copper or an alloy containing copper as a main component containing ceramic powder. 請求項１または請求項２記載の半導体素子収納用パッケージと、前記凸部に載置されるとともに前記配線導体に電気的に接続された半導体素子と、前記枠体の上面に取着された蓋体とを具備していることを特徴とする半導体装置。 3. A package for housing a semiconductor element according to claim 1; a semiconductor element placed on the convex portion and electrically connected to the wiring conductor; and a lid attached to the upper surface of the frame body. A semiconductor device comprising: a body. 請求項１または請求項２記載の半導体素子収納用パッケージと、前記凸部に載置されるとともに前記配線導体に電気的に接続された半導体素子と、該半導体素子を覆う外装樹脂とを具備していることを特徴とする半導体装置。 A package for housing a semiconductor element according to claim 1, a semiconductor element mounted on the convex portion and electrically connected to the wiring conductor, and an exterior resin covering the semiconductor element. A semiconductor device characterized by that.
JP2004220837A 2003-10-30 2004-07-28 Semiconductor device housing package and its semiconductor equipment Pending JP2005159288A (en)

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JP2004220837A JP2005159288A (en) 2003-10-30 2004-07-28 Semiconductor device housing package and its semiconductor equipment

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