JP2005159238A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2005159238A
JP2005159238A JP2003399196A JP2003399196A JP2005159238A JP 2005159238 A JP2005159238 A JP 2005159238A JP 2003399196 A JP2003399196 A JP 2003399196A JP 2003399196 A JP2003399196 A JP 2003399196A JP 2005159238 A JP2005159238 A JP 2005159238A
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sealing body
semiconductor device
electrode plate
semiconductor chip
drain electrode
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Yukihiro Sato
幸弘 佐藤
Toshiyuki Namita
俊幸 波多
Kazuo Shimizu
一男 清水
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Renesas Technology Corp
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Renesas Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a small semiconductor device of a surface mounting structure wherein an electrode plate is exposed to an upper surface of a sealing member. <P>SOLUTION: The semiconductor device comprises a sealing member having upper, lower and side surfaces; a semiconductor chip positioned in the sealing member and having source and gate electrodes on its first main surface and having a drain electrode on its second main surface; a drain electrode plate having the drain electrode of the semiconductor chip connected to its one surface and having the other surface exposed to the upper surface of the sealing member; source and gate electrode plates of a terminal structure, part of which is positioned in the interior of the sealing member to be connected to the gate and source electrodes of the semiconductor chip respectively and another part of which is projected from the side surface of the sealing member to be surface mounted on the second surface side of the sealing member; and a wiring terminal projected from one edge of the drain electrode plate and extended and bent along the side surface of the sealing member to be surface mounted on the lower surface side of the sealing member. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は半導体装置に係わり、例えば、サーバのＤＣ−ＤＣコンバータに使用されるパワートランジスタ等に適用して有効な技術に関する。   The present invention relates to a semiconductor device, for example, a technique effective when applied to a power transistor used in a DC-DC converter of a server.

パワートランジスタとして、絶縁性樹脂からなる封止体内にパワーＭＯＳＦＥＴチップを組み込んだ構造が知られている。パワートランジスタとして、絶縁性樹脂からなる封止体の下面にドレイン端子となる金属部材を露出させ，封止体の側面にソース用リード端子及びゲート用リード端子を配置した構造が知られている。封止体から突出するソース用リード端子及びゲート用リード端子は一部で屈曲し、その先端は表面実装が可能な構造になっている。封止体内に延在するソース用リード端子及びゲート用リード端子は、前記金属部材上に固定された半導体チップの上面のソース電極及びゲート電極にそれぞれ電気的に接続されている。これらリードは、ソース電極及びゲート電極上にワイヤのボールボンディング法によって均等に配置されたＡｕバンプに超音波圧着されている（例えば、特許文献１）。また、特許文献１には、ソース用リード端子及びゲート用リード端子の一部が封止体の上面に露出する構造も開示されている。   As a power transistor, a structure in which a power MOSFET chip is incorporated in a sealed body made of an insulating resin is known. As a power transistor, a structure in which a metal member serving as a drain terminal is exposed on the lower surface of a sealing body made of an insulating resin and a source lead terminal and a gate lead terminal are arranged on the side surface of the sealing body is known. The source lead terminal and the gate lead terminal protruding from the sealing body are partially bent, and the tips thereof are structured to be surface-mounted. The source lead terminal and the gate lead terminal extending into the sealing body are electrically connected to the source electrode and the gate electrode on the upper surface of the semiconductor chip fixed on the metal member, respectively. These leads are ultrasonically bonded to Au bumps that are evenly arranged on the source electrode and the gate electrode by a wire ball bonding method (for example, Patent Document 1). Patent Document 1 also discloses a structure in which part of the source lead terminal and the gate lead terminal are exposed on the upper surface of the sealing body.

一方、同様の構造のパワートランジスタの製造方法において、半導体ウエハの段階で金バンプを形成し、その後半導体ウエハをダイシングして金バンプを有する半導体チップを形成する技術も知られている（例えば、特許文献２）。   On the other hand, in a manufacturing method of a power transistor having a similar structure, a technique for forming a gold bump at the stage of a semiconductor wafer and then dicing the semiconductor wafer to form a semiconductor chip having the gold bump is also known (for example, patents). Reference 2).

特開２０００−２２３６３４号公報JP 2000-223634 A 特開２００３−８６７８７号公報JP 2003-86787 A

前記パワートランジスタは、封止体の下面にドレイン端子になる電極板（ドレイン電極板）が露出し、封止体の側面から突出するソース端子（ソース電極板）及びゲート端子（ゲート電極板）は一段屈曲し、先端の実装部分が前記ドレイン電極板と略同じ高さに位置して表面実装可能な構造になっている。   In the power transistor, an electrode plate (drain electrode plate) serving as a drain terminal is exposed on the lower surface of the sealing body, and a source terminal (source electrode plate) and a gate terminal (gate electrode plate) protruding from the side surface of the sealing body are It is bent one step, and the mounting portion at the tip is positioned at substantially the same height as the drain electrode plate so that it can be surface mounted.

一方、ドレイン電極板を封止体の上面に露出させ、この露出させたドレイン電極板に放熱フィンを取り付けて使用する実装形態が要請されている。   On the other hand, there is a demand for a mounting form in which the drain electrode plate is exposed on the upper surface of the sealing body, and a radiation fin is attached to the exposed drain electrode plate.

本発明の一つの目的は、封止体の上面に電極板を露出する表面実装構造の半導体装置を提供することにある。   One object of the present invention is to provide a semiconductor device having a surface mounting structure in which an electrode plate is exposed on an upper surface of a sealing body.

本発明の一つの目的は、封止体の上面に電極板を露出する表面実装構造の小型の半導体装置を提供することにある。   One object of the present invention is to provide a small-sized semiconductor device having a surface mounting structure in which an electrode plate is exposed on an upper surface of a sealing body.

本発明の前記ならびにそのほかの目的と新規な特徴は、本明細書の記述および添付図面からあきらかになるであろう。   The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち代表的なものの概要を簡単に説明すれば、下記のとおりである。   The following is a brief description of an outline of typical inventions disclosed in the present application.

（１）本発明の半導体装置は、
第１の面（上面）、前記第１の面の反対の面となる第２の面（下面）及び前記第１の面と前記第２の面を接続する側面を有する絶縁性樹脂からなる封止体と、
前記封止体内に位置し第１の主面に複数の電極（ソース電極及びゲート電極）を有し、前記第１の主面の反対の第２の主面に電極（ドレイン電極）を有する半導体チップと、
一面に前記半導体チップの第２の主面を接続し、前記一面の反対面となる他の一面を前記封止体の前記第１の面に露出させる電極板（ドレイン電極板）と、
一部が前記封止体の内部に位置して前記半導体チップの所定の前記電極に接続され、他の一部が前記封止体の側面から突出して前記封止体の第２の面側で表面実装可能を端子構造となる複数の電極板（ソース電極板及びゲート電極板）と、
前記封止体の前記第１の面に一面を露出させる前記電極板の一縁から突出し、前記封止体の側面に沿って延在し、かつ屈曲して前記封止体の第２の面側で表面実装可能となる引き回し端子（ドレイン電極板）とを有することを特徴とする。 (1) The semiconductor device of the present invention
A seal made of an insulating resin having a first surface (upper surface), a second surface (lower surface) that is opposite to the first surface, and a side surface that connects the first surface and the second surface. A stationary body,
A semiconductor having a plurality of electrodes (source electrode and gate electrode) on a first main surface and having an electrode (drain electrode) on a second main surface opposite to the first main surface, located in the sealing body. Chips,
An electrode plate (drain electrode plate) for connecting the second main surface of the semiconductor chip to one surface and exposing the other surface opposite to the one surface to the first surface of the sealing body;
A part is located inside the sealing body and connected to the predetermined electrode of the semiconductor chip, and the other part protrudes from the side surface of the sealing body on the second surface side of the sealing body. A plurality of electrode plates (source electrode plate and gate electrode plate) that are surface-mountable and have a terminal structure;
A second surface of the sealing body that protrudes from one edge of the electrode plate that exposes one surface on the first surface of the sealing body, extends along a side surface of the sealing body, and is bent. It has a routing terminal (drain electrode plate) that can be surface-mounted on the side.

また、前記引き回し端子の表面実装部分は前記封止体の側面から突出する電極板（ソース電極板及びゲート電極板）の表面実装部分よりも長くなっていることを特徴とする。   Further, the surface mounting portion of the routing terminal is longer than the surface mounting portion of the electrode plate (source electrode plate and gate electrode plate) protruding from the side surface of the sealing body.

本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば、下記のとおりである。   The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

前記（１）の手段によれば、（ａ）封止体の上面にドレイン電極板が露出するとともに、このドレイン電極板から引き回し端子が封止体の下面側に引き回されて表面実装構造の端子となっている。この引き回し端子は、封止体の１辺に沿って延在する構造になることから、封止体の側方に長く突出しなくなり、半導体装置全体の大きさを小さくすることができる。   According to the means (1), (a) the drain electrode plate is exposed on the upper surface of the sealing body, and the lead-out terminal is routed from the drain electrode plate to the lower surface side of the sealing body so that the surface mounting structure is provided. It is a terminal. Since the lead terminal has a structure extending along one side of the sealing body, the lead terminal does not protrude long to the side of the sealing body, and the size of the entire semiconductor device can be reduced.

（ｂ）封止体の上面に平坦なドレイン電極板の１面が露出することから、この露出面に放熱フィンを取り付けることができ、熱放散性の良好な半導体装置になる。   (B) Since one surface of the flat drain electrode plate is exposed on the upper surface of the sealing body, a heat radiating fin can be attached to the exposed surface, and the semiconductor device has a good heat dissipation.

（ｃ）前記引き回し端子の表面実装部分は前記封止体の側面から突出する電極板（ソース電極板及びゲート電極板）の表面実装部分よりも長くなっていることから、接続強度が大きくなり、実装の信頼性が高くなる。   (C) Since the surface mounting portion of the routing terminal is longer than the surface mounting portion of the electrode plate (source electrode plate and gate electrode plate) protruding from the side surface of the sealing body, the connection strength is increased, Increased mounting reliability.

以下、図面を参照して本発明の実施の形態を詳細に説明する。なお、発明の実施の形態を説明するための全図において、同一機能を有するものは同一符号を付け、その繰り返しの説明は省略する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment of the invention, and the repetitive description thereof is omitted.

図１乃至図１７は本発明の実施例１である半導体装置に係わる図である。図１〜９は半導体装置の構造に係わる図であり、図１０〜図１４は半導体装置の製造に係わる図である。図１５〜図１７は放熱フィンを取り付けた状態の半導体装置を示す図である。   1 to 17 are diagrams relating to a semiconductor device which is Embodiment 1 of the present invention. 1 to 9 are diagrams related to the structure of the semiconductor device, and FIGS. 10 to 14 are diagrams related to the manufacture of the semiconductor device. 15 to 17 are views showing the semiconductor device with the radiation fins attached.

本実施例１の半導体装置は、パワートランジスタを構成し、封止体の内部に縦型のパワーＭＯＳＦＥＴを形成した半導体チップが組み込まれている。半導体チップの第１の主面には、第１電極であるソース（Ｓ）電極と、制御電極であるゲート（Ｇ）電極が設けられ、前記第１の主面の反対面となる第２の主面には第２電極となるドレイン（Ｄ）電極が設けられる構造になっている。   The semiconductor device of the first embodiment constitutes a power transistor, and a semiconductor chip in which a vertical power MOSFET is formed inside a sealing body is incorporated. A source (S) electrode that is a first electrode and a gate (G) electrode that is a control electrode are provided on the first main surface of the semiconductor chip, and a second surface that is opposite to the first main surface. The main surface has a structure in which a drain (D) electrode serving as a second electrode is provided.

半導体装置１は、図２乃至図６及び図８に示すように、外観的には偏平四角形状の絶縁性樹脂からなる封止体（パッケージ）２を有する。封止体２は第１の面（上面）と、第１の面の反対面となる第２の面（下面）と、第１の面第２の面を接続する側面とを有する構造になっている。   As shown in FIGS. 2 to 6 and 8, the semiconductor device 1 has a sealing body (package) 2 made of an insulating resin having a flat rectangular shape in appearance. The sealing body 2 has a structure having a first surface (upper surface), a second surface (lower surface) opposite to the first surface, and a side surface connecting the first surface and the second surface. ing.

封止体２にはその内外に亘って延在する銅合金からなる３本の電極板４，５，６を有する。第１の電極板（電極板４）はドレイン電極板４であり、第２の電極板（電極板５）はゲート電極板５であり、第３の電極板（電極板６）はソース電極板６である。   The sealing body 2 has three electrode plates 4, 5 and 6 made of a copper alloy extending over the inside and outside. The first electrode plate (electrode plate 4) is the drain electrode plate 4, the second electrode plate (electrode plate 5) is the gate electrode plate 5, and the third electrode plate (electrode plate 6) is the source electrode plate. 6.

また、図８及び図３に示すように、封止体２内には半導体チップ７が位置している。この半導体チップ７の第１の主面にはゲート電極８及びソース電極９が設けられている。また、第１の主面の反対の第２の主面にはドレイン電極（特に符号は付さず）が設けられている。ドレイン電極は半導体チップ７の第２の主面の略全域に亘って設けられている。ゲート電極８上には突起電極（バンプ電極）８ａが設けられている。また、ソース電極９上には複数の突起電極（バンプ電極）９ａが設けられている。ゲート電極８は狭い領域であることから、例えば、１個のバンプ電極８ａを設けているが、余裕があれば複数のバンプ電極としてもよい。ソース電極９は広い面積であることから、給電状態を一様にするために所定箇所に点在してある。図では５個としてあるがこれに限定されるものではない。   Further, as shown in FIGS. 8 and 3, the semiconductor chip 7 is located in the sealing body 2. A gate electrode 8 and a source electrode 9 are provided on the first main surface of the semiconductor chip 7. Further, a drain electrode (in particular, no reference numeral) is provided on the second main surface opposite to the first main surface. The drain electrode is provided over substantially the entire area of the second main surface of the semiconductor chip 7. A protruding electrode (bump electrode) 8 a is provided on the gate electrode 8. A plurality of protruding electrodes (bump electrodes) 9 a are provided on the source electrode 9. Since the gate electrode 8 is a narrow region, for example, one bump electrode 8a is provided, but a plurality of bump electrodes may be provided if there is a margin. Since the source electrode 9 has a large area, it is scattered at predetermined locations in order to make the power supply state uniform. Although the number is five in the figure, it is not limited to this.

ドレイン電極板４はその一面に接続材１１を介して半導体チップ７の第２の主面側を接続（固定）する構造になっている（図１参照）。これにより、半導体チップ７の第２の主面に設けられたドレイン電極はドレイン電極板４に電気的に接続されることになる。   The drain electrode plate 4 has a structure in which the second main surface side of the semiconductor chip 7 is connected (fixed) to one surface thereof via a connecting material 11 (see FIG. 1). As a result, the drain electrode provided on the second main surface of the semiconductor chip 7 is electrically connected to the drain electrode plate 4.

ドレイン電極板４の前記一面の反対面となる他の一面は封止体２の上面に露出している。ドレイン電極板４の一部は四角形状の封止体２の１辺側に幅広状態で突出するとともに、この幅広突出部分４ａの一縁、即ち、幅広突出部分４ａの中間寄りの部分から引き回し端子４ｂが突出している。引き回し端子４ｂは、突出部分から突出する突出部分４ｃと、この突出部分４ｃに連なり封止体２の側面（１辺）に沿って延在する延在部分４ｄとからなっている。また、延在部分４ｄは途中で封止体２の下面側に一段階段状に屈曲している。屈曲した先端部分は半導体装置１の表面実装時、実装（接続）される部分（実装部分４ｅ）となる（図９参照）。ドレイン電極板４の幅広突出部分４ａ以外の縁部分は封止体２によって覆われている（図２参照）。   The other surface of the drain electrode plate 4 opposite to the one surface is exposed on the upper surface of the sealing body 2. A part of the drain electrode plate 4 projects in a wide state on one side of the rectangular sealing body 2 and leads out from one edge of the wide projecting portion 4a, that is, a portion closer to the middle of the wide projecting portion 4a. 4b protrudes. The routing terminal 4b includes a projecting portion 4c projecting from the projecting portion and an extending portion 4d extending along the side surface (one side) of the sealing body 2 connected to the projecting portion 4c. In addition, the extended portion 4d is bent in a stepped manner on the lower surface side of the sealing body 2 in the middle. The bent tip portion becomes a portion (mounting portion 4e) to be mounted (connected) when the semiconductor device 1 is surface-mounted (see FIG. 9). Edge portions of the drain electrode plate 4 other than the wide protruding portions 4a are covered with the sealing body 2 (see FIG. 2).

半導体装置１の小型化のため、幅広突出部分４ａ及び突出部分４ｃは、その突出長さができるだけ短くなるように設計されている。即ち、ドレイン電極板４は、板材をプレス加工やエッチング加工によって形成するが、この加工時、幅広突出部分４ａと、この幅広突出部分４ａに平行に延在する延在部分４ｄとの間隔が最も短くできるような寸法あるいはこれに近似した寸法が選ばれる。   In order to reduce the size of the semiconductor device 1, the wide protruding portion 4a and the protruding portion 4c are designed so that the protruding length is as short as possible. That is, the drain electrode plate 4 is formed by pressing or etching a plate material. At this time, the distance between the wide protruding portion 4a and the extending portion 4d extending in parallel to the wide protruding portion 4a is the largest. A dimension that can be shortened or a dimension that approximates this is selected.

また、封止体２内に位置するドレイン電極板４の側面は、図１に示すように、斜面４ｇが設けられて庇状になり、ドレイン電極板４が封止体２から抜け難くなっている。封止体２が形成されるドレイン電極板領域には四角形状の開口部４ｆが設けられている。この開口部４ｆには封止体２を形成する樹脂が入り込むことから、ドレイン電極板４と樹脂との接触面積を増大させ、封止体２からドレイン電極板４が剥離し難くなっている。   Further, as shown in FIG. 1, the side surface of the drain electrode plate 4 located in the sealing body 2 is provided with a slope 4 g and has a bowl shape, so that the drain electrode plate 4 is difficult to be removed from the sealing body 2. Yes. In the drain electrode plate region where the sealing body 2 is formed, a rectangular opening 4f is provided. Since the resin forming the sealing body 2 enters the opening 4f, the contact area between the drain electrode plate 4 and the resin is increased, and the drain electrode plate 4 is difficult to peel from the sealing body 2.

一方、一部が封止体２の内部に位置して半導体チップ７の第１の主面の所定の電極に接続され、他の一部が封止体２の側面から突出して封止体２の第２の面側で表面実装可能な端子構造となるゲート電極板５及びソース電極板６が設けられている。   On the other hand, a part is located inside the sealing body 2 and connected to a predetermined electrode on the first main surface of the semiconductor chip 7, and the other part protrudes from the side surface of the sealing body 2 to seal the sealing body 2. A gate electrode plate 5 and a source electrode plate 6 are provided to be a terminal structure that can be surface-mounted on the second surface side.

ゲート電極板５は、例えば、０．５ｍｍ程度の細い１本構造となり、一部（内端）は屈曲（屈曲部５ａ）して半導体チップ７のゲート電極８上に形成されたバンプ電極８ａに電気的に接続されている。封止体２から突出する他の一部（外端）は表面実装が可能な構造になっている。即ち、封止体２の側面から突出するゲート電極板５は途中で封止体２の下面側に一段階段状に屈曲し、屈曲した先端部分は半導体装置１の表面実装時、実装される部分（実装部分５ｅ）となる（図３、図８参照）。   The gate electrode plate 5 has a thin single structure of about 0.5 mm, for example, and a part (inner end) is bent (bent portion 5 a) to form a bump electrode 8 a formed on the gate electrode 8 of the semiconductor chip 7. Electrically connected. The other part (outer end) protruding from the sealing body 2 has a structure capable of surface mounting. That is, the gate electrode plate 5 protruding from the side surface of the sealing body 2 is bent in one step on the lower surface side of the sealing body 2, and the bent tip portion is a portion to be mounted when the semiconductor device 1 is surface-mounted. (Mounting portion 5e) (see FIGS. 3 and 8).

ソース電極板６の一部（内端）は半導体チップ７のソース電極９に対面するように幅広の板材（幅広部６ａ）となり、図１、図３及び図８に示すように、半導体チップ７のソース電極９上に設けられた複数のバンプ電極９ａに電気的に接続されている。図８に示すように、幅広部６ａからは３本の端子部６ｂが突出し、これら３本の端子部６ｂが封止体２の側面から外部に平行に突出している。この端子部６ｂ、換言するならば、ソース電極板６の他の一部（外端）は表面実装が可能な構造になっている。即ち、封止体２の側面から突出する端子部６ｂは途中で封止体２の下面側に一段階段状に屈曲し、屈曲した先端部分は半導体装置１の表面実装時、実装される部分（実装部分６ｅ）となる（図４、図５参照）。ドレイン電極板４の実装部分４ｅの下面高さ、ゲート電極板５の実装部分５ｅの下面高さ及びソース電極板６の実装部分６ｅの下面高さは同じ高さとなり、半導体装置１の表面実装が可能になっている。   A part (inner end) of the source electrode plate 6 becomes a wide plate material (wide portion 6a) so as to face the source electrode 9 of the semiconductor chip 7, and as shown in FIGS. 1, 3, and 8, the semiconductor chip 7 Are electrically connected to a plurality of bump electrodes 9 a provided on the source electrode 9. As shown in FIG. 8, three terminal portions 6 b protrude from the wide portion 6 a, and these three terminal portions 6 b protrude from the side surface of the sealing body 2 in parallel to the outside. This terminal portion 6b, in other words, the other part (outer end) of the source electrode plate 6 has a structure that can be surface-mounted. That is, the terminal portion 6 b protruding from the side surface of the sealing body 2 is bent in one step to the lower surface side of the sealing body 2, and the bent tip portion is a portion to be mounted when the semiconductor device 1 is mounted on the surface ( The mounting portion 6e) (see FIGS. 4 and 5). The bottom surface height of the mounting portion 4 e of the drain electrode plate 4, the bottom surface height of the mounting portion 5 e of the gate electrode plate 5, and the bottom surface height of the mounting portion 6 e of the source electrode plate 6 are the same height. Is possible.

なお、ソース電極板６において、封止体２の側面から３本の端子部６ｂを突出させる構造にすることによって、半導体装置１を実装基板に半田等の接合材料で接合する際、面積が広いと半田が集まりすぎて盛り上がるのを防止し、半田が所定量ずつ分散するようにするためである。   The source electrode plate 6 has a structure in which the three terminal portions 6b protrude from the side surface of the sealing body 2 so that the area of the semiconductor device 1 is large when the semiconductor device 1 is bonded to the mounting substrate with a bonding material such as solder. This is to prevent the solder from gathering too much and rising, and to disperse the solder by a predetermined amount.

また、図７に示すように、封止体２の表面に円形窪２０が偏って設けられている。この円形窪２０によって、半導体装置１の方向性（極性）を認識することができる。   In addition, as shown in FIG. 7, circular recesses 20 are provided on the surface of the sealing body 2 in a biased manner. With this circular recess 20, the directionality (polarity) of the semiconductor device 1 can be recognized.

図１０は本実施例の変形例である。図１０に示す半導体装置１は、実施例１において、ドレイン電極板４の引き回し端子４ｂを長くし、実装部分４ｅの長さを、ゲート電極板５及びソース電極板６の実装部分５ｅ，６ｅの長さよりも長くし、実装強度向上を図るものである。図１０の半導体装置１のドレイン電極板４の実装部分４ｅの長さは、図５及び図６に示すゲート電極板５及びソース電極板６の実装部分５ｅ，６ｅの長さよりも３倍程度長くなっている。   FIG. 10 shows a modification of this embodiment. In the semiconductor device 1 shown in FIG. 10, in the first embodiment, the routing terminal 4 b of the drain electrode plate 4 is lengthened, the length of the mounting portion 4 e is set to the length of the mounting portions 5 e and 6 e of the gate electrode plate 5 and the source electrode plate 6. The length is longer than the length to improve the mounting strength. The length of the mounting portion 4e of the drain electrode plate 4 of the semiconductor device 1 of FIG. 10 is about three times longer than the length of the mounting portions 5e and 6e of the gate electrode plate 5 and the source electrode plate 6 shown in FIGS. It has become.

つぎに、このような半導体装置１の製造方法について説明する。半導体装置１の製造においては、図１１及び図１２に示すドレイン電極板４を形成するリードフレーム２５と、図１４に示すゲート電極板５及びソース電極板６を形成するリードフレーム４５が使用される。いずれのリードフレームも一対の外枠と、これら外枠を一定の間隔で連結する内枠とからなり、外枠と内枠で形成される四角形状の領域に所定のリードパターンを形成したパターンになっている。いずれのリードフレームも一部を示すものである。リードフレームは銅合金板を所望のパターンに形成したものである。   Next, a method for manufacturing such a semiconductor device 1 will be described. In manufacturing the semiconductor device 1, a lead frame 25 for forming the drain electrode plate 4 shown in FIGS. 11 and 12 and a lead frame 45 for forming the gate electrode plate 5 and the source electrode plate 6 shown in FIG. 14 are used. . Each lead frame is composed of a pair of outer frames and an inner frame that connects the outer frames at regular intervals, and has a pattern in which a predetermined lead pattern is formed in a rectangular area formed by the outer frame and the inner frame. It has become. Each lead frame shows a part. The lead frame is a copper alloy plate formed in a desired pattern.

図１１及び図１２に示すドレイン電極板４を形成するリードフレーム２５は、それぞれ両端が内枠に連結される連結部２６を有している。この連結部２６の両側にはそれぞれ突出したドレイン用突片２７が形成されている。このドレイン用突片２７は半導体チップ７を搭載する部分を有するとともに、連結部２６との境界部分に１辺を近接させた前述の開口部４ｆが形成されている。ドレイン用突片２７の露出側面の周縁には前述の斜面４ｇが形成されている。また、連結部２６には角張ったＳ字状のスリット２８が直列に２本設けられている。各スリット２８は各ドレイン用突片２７に対応している。このスリット２８によって囲まれた部分が前述のドレイン電極板４の幅広突出部分４ａ及び引き回し端子４ｂを形成する部分になる。   The lead frame 25 forming the drain electrode plate 4 shown in FIG. 11 and FIG. 12 has a connecting portion 26 whose both ends are connected to the inner frame. On both sides of the connecting portion 26, a protruding protrusion 27 for drain is formed. The drain protrusion 27 has a portion on which the semiconductor chip 7 is mounted, and is formed with the opening 4 f described above having one side close to the boundary with the connecting portion 26. The aforementioned slope 4g is formed on the periphery of the exposed side surface of the drain protrusion 27. Further, the connecting portion 26 is provided with two square S-shaped slits 28 in series. Each slit 28 corresponds to each drain protrusion 27. A portion surrounded by the slits 28 is a portion for forming the wide protruding portion 4a and the routing terminal 4b of the drain electrode plate 4 described above.

従って、外枠と横枠で形成される四角形状領域には４個の半導体装置１を製造できるリードパターンが形成されていることになる。このため、図１４に示すゲート電極板５及びソース電極板６を形成するリードフレーム４５もリードフレーム２５に対応した構造になっている。   Therefore, a lead pattern capable of manufacturing four semiconductor devices 1 is formed in a rectangular region formed by the outer frame and the horizontal frame. Therefore, the lead frame 45 forming the gate electrode plate 5 and the source electrode plate 6 shown in FIG. 14 has a structure corresponding to the lead frame 25.

リードフレーム４５においては、一対の外枠４６の内側の２箇所で４本のリードが平行に内側に延在している。隣り合う３本のリード４７は四角形状の幅広部６ａに連なっている。幅広部６ａから突出する３本のリード４７を封止体２を形成した後、途中で切断することによって半導体装置１のソース電極板６の端子部６ｂが形成される。３本のリード４７に隣接する残りの１本のリード４８はその先端が幅広部６ａ側に屈曲して屈曲部５ａを形成している。リード４８を封止体２を形成した後、途中で切断することによって半導体装置１のゲート電極板５が形成される。幅広部６ａ及び屈曲部５ａはリードフレーム２５のドレイン用突片２７上に重なるようになっている。   In the lead frame 45, four leads extend inward in parallel at two locations inside the pair of outer frames 46. Three adjacent leads 47 are connected to the rectangular wide portion 6a. After forming the sealing body 2 with the three leads 47 protruding from the wide portion 6a, the terminal portion 6b of the source electrode plate 6 of the semiconductor device 1 is formed by cutting in the middle. The remaining one lead 48 adjacent to the three leads 47 has its tip bent toward the wide portion 6a to form a bent portion 5a. After forming the sealing body 2 in the lead 48, the gate electrode plate 5 of the semiconductor device 1 is formed by cutting in the middle. The wide portion 6 a and the bent portion 5 a overlap with the drain protrusion 27 of the lead frame 25.

半導体装置１の製造においては、図１３に示すように、各ドレイン用突片２７のチップ固定側面に導電性の接続材１１を介して半導体チップ７を固定する。半導体チップ７これにより、半導体チップ７の第２の主面に設けられたドレイン電極はドレイン用突片２７に電気的に接続されることになる。半導体チップ７の第１の主面にはゲート電極８及びソース電極９が設けられている。ゲート電極８上にはバンプ電極８ａが接続され、ソース電極９上には複数のバンプ電極９ａが接続されている。   In the manufacture of the semiconductor device 1, as shown in FIG. 13, the semiconductor chip 7 is fixed to the chip fixing side surface of each drain projection piece 27 via the conductive connecting material 11. Thus, the drain electrode provided on the second main surface of the semiconductor chip 7 is electrically connected to the drain protrusion 27. A gate electrode 8 and a source electrode 9 are provided on the first main surface of the semiconductor chip 7. A bump electrode 8 a is connected on the gate electrode 8, and a plurality of bump electrodes 9 a are connected on the source electrode 9.

つぎに、図１４に示すように、リードフレーム４５をリードフレーム２５上に位置決めして重ね合わせ、各半導体チップ７のゲート電極８のバンプ電極８ａにリード４８の屈曲部５ａを接続し、かつソース電極９の各バンプ電極９ａに幅広部６ａを接続させる。この接続は、半田等からなるバンプ電極８ａ，９ａのリフローによって行う。   Next, as shown in FIG. 14, the lead frame 45 is positioned and superimposed on the lead frame 25, the bent portion 5a of the lead 48 is connected to the bump electrode 8a of the gate electrode 8 of each semiconductor chip 7, and the source The wide portion 6 a is connected to each bump electrode 9 a of the electrode 9. This connection is performed by reflow of bump electrodes 8a and 9a made of solder or the like.

つぎに、常用のトランスファモールディングによって絶縁性樹脂（例えば、エポキシ樹脂）からなる封止体２を形成し、ついでリード４７，４８及び連結部２６を所定箇所で切断し、かつ成型して図１乃至図９に示す表面実装型の半導体装置１を製造する。   Next, the sealing body 2 made of an insulating resin (for example, an epoxy resin) is formed by ordinary transfer molding, and then the leads 47 and 48 and the connecting portion 26 are cut at predetermined positions and molded, and then FIG. The surface mount type semiconductor device 1 shown in FIG. 9 is manufactured.

図１６は実施例１の半導体装置１に放熱フィン５０を取り付けた状態を示す模式的断面図であり、図１に示す半導体装置１のドレイン電極板４上に接合材５１を介して放熱フィン５０を固定した状態を示す図である。放熱フィン５０は台座部５２と、この台座部５２の上面側に複数平行に設けられる突条のフィン５３とからなっている。接合材５１は、熱伝導性が良好である材質であれば何でもよい。このように放熱フィン５０を取り付けることによって放熱性の良好な半導体装置を提供することができる。   FIG. 16 is a schematic cross-sectional view showing a state in which the radiating fins 50 are attached to the semiconductor device 1 of the first embodiment. The radiating fins 50 are disposed on the drain electrode plate 4 of the semiconductor device 1 shown in FIG. It is a figure which shows the state which fixed. The heat radiating fin 50 includes a pedestal portion 52 and a plurality of fins 53 provided in parallel on the upper surface side of the pedestal portion 52. The bonding material 51 may be anything as long as it has a good thermal conductivity. Thus, by attaching the radiation fins 50, a semiconductor device with good heat dissipation can be provided.

図１７及び図１８は実施例１の半導体装置１を実装基板５５に複数実装し、かつ各半導体装置１に共通の放熱フィン５６を取り付けた状態を示すものである。図１７は模式的断面図であり、図１８は模式的平面図である。   FIGS. 17 and 18 show a state in which a plurality of semiconductor devices 1 according to the first embodiment are mounted on the mounting substrate 55 and a common radiating fin 56 is attached to each semiconductor device 1. FIG. 17 is a schematic cross-sectional view, and FIG. 18 is a schematic plan view.

図では４個の半導体装置１を一列に実装した状態を示すが、実装の数はこれに限定されるものではない。放熱フィン５６はフィン５７を有するフィン部５８と、このフィン部５８の両端に延在するフィン５７を有しない平坦な取付部５９からなっている。取付部５９は実装基板５５に固定された支柱６０上にビス６１によってネジ止めされている。各半導体装置１の上面と放熱フィン５６との間にはバッファ６２が介在されている。このバッファ６２は、例えば、高熱電導性ゴム体で形成されている。従って、バッファ６２はビス６１の締め付けによって弾力的に変形しながらそれぞれ半導体装置１のドレイン電極板に接触するため、半導体装置１の高さばらつきがあっても半導体装置１を締め付けで損傷させることがない。バッファ６２は放熱フィン５６や半導体装置１に接着させるものであっても、あるいは単に介在させるだけのものでもよい。   Although the figure shows a state where four semiconductor devices 1 are mounted in a row, the number of mounting is not limited to this. The heat radiating fin 56 includes a fin portion 58 having a fin 57 and a flat mounting portion 59 having no fin 57 extending at both ends of the fin portion 58. The attachment portion 59 is screwed with a screw 61 on a support 60 fixed to the mounting substrate 55. A buffer 62 is interposed between the upper surface of each semiconductor device 1 and the heat radiating fins 56. The buffer 62 is made of, for example, a high thermal conductive rubber body. Accordingly, since the buffer 62 comes into contact with the drain electrode plate of the semiconductor device 1 while being elastically deformed by tightening the screws 61, the semiconductor device 1 may be damaged by tightening even if the height of the semiconductor device 1 varies. Absent. The buffer 62 may be bonded to the heat radiating fins 56 and the semiconductor device 1 or may simply be interposed.

このような構造では、フィン部５８の１側に突出する延在部分４ｄの封止体２からの突出長さが短くできることから複数の半導体装置の実装面積の縮小化が図れる。   In such a structure, since the protruding length from the sealing body 2 of the extended portion 4d protruding to the one side of the fin portion 58 can be shortened, the mounting area of a plurality of semiconductor devices can be reduced.

実施例１によれば以下の効果を有する。
（１）封止体２の上面にドレイン電極板４が露出するとともに、このドレイン電極板４から引き回し端子４ｂが封止体２の下面側に引き回されて表面実装構造の端子となっている。この引き回し端子４ｂは、封止体２の１辺に沿って延在する構造になることから、封止体２の側方に長く突出しなくなり、半導体装置全体の大きさを小さくすることができる。 Example 1 has the following effects.
(1) The drain electrode plate 4 is exposed on the upper surface of the sealing body 2, and the routing terminal 4 b is routed from the drain electrode plate 4 to the lower surface side of the sealing body 2 to form a surface mounting structure terminal. . Since the lead terminal 4b has a structure extending along one side of the sealing body 2, it does not protrude long to the side of the sealing body 2, and the size of the entire semiconductor device can be reduced.

（２）封止体２の上面に平坦なドレイン電極板４の１面が露出することから、この露出面に放熱フィン５０を取り付けることができ、熱放散性の良好な半導体装置１になる。   (2) Since one surface of the flat drain electrode plate 4 is exposed on the upper surface of the sealing body 2, the radiating fins 50 can be attached to the exposed surface, and the semiconductor device 1 with good heat dissipation is obtained.

（３）引き回し端子４ｂの表面実装部分は封止体２の側面から突出するゲート電極板５及びソース電極板６の表面実装部分よりも長くなる構造では、接続強度が大きくなり、実装の信頼性が高くなる。   (3) In the structure in which the surface mounting portion of the lead terminal 4b is longer than the surface mounting portions of the gate electrode plate 5 and the source electrode plate 6 protruding from the side surface of the sealing body 2, the connection strength is increased and the mounting reliability is increased. Becomes higher.

（４）実装基板５５上に一列に半導体装置１を実装し、これら半導体装置１上に１本の放熱フィン５６を延在させる実装構造では、半導体装置１の小型化から実装面積の縮小化が可能になる。また、各半導体装置１の上面と放熱フィン５６との間には弾力的に作用するバッファ６２が介在されていることから、バッファ６２をビス６１の締め付けによって実装基板５５に取り付ける際締め付けによって半導体装置１を損傷させることもない。   (4) In the mounting structure in which the semiconductor devices 1 are mounted in a row on the mounting substrate 55 and one radiating fin 56 is extended on the semiconductor device 1, the mounting area can be reduced from the downsizing of the semiconductor device 1. It becomes possible. Further, since the buffer 62 acting elastically is interposed between the upper surface of each semiconductor device 1 and the radiation fin 56, the semiconductor device is tightened when the buffer 62 is attached to the mounting substrate 55 by tightening the screw 61. 1 is not damaged.

図１９乃至図２３は本発明の実施例２である半導体装置に係わる図である。図１９は半導体装置１の模式的平面図、図２０は半導体装置の左側面図、図２１は半導体装置の右側面図、図２２は半導体装置の底面図、図２３は半導体装置の背面図である。   19 to 23 are diagrams relating to a semiconductor device which is Embodiment 2 of the present invention. 19 is a schematic plan view of the semiconductor device 1, FIG. 20 is a left side view of the semiconductor device, FIG. 21 is a right side view of the semiconductor device, FIG. 22 is a bottom view of the semiconductor device, and FIG. is there.

本実施例２の半導体装置１は、実施例１の半導体装置１において、封止体２の１辺から突出する幅広突出部分４ａの両端を細く延長させ、これら延長端部４ｈを表面実装構造としたものである。即ち、幅広突出部分４ａから延長される延長端部４ｈを途中で一段封止体２の下面側に屈曲させて先端を実装部分４ｅとしたものである。   The semiconductor device 1 of the second embodiment is the same as the semiconductor device 1 of the first embodiment except that both ends of the wide protruding portion 4a protruding from one side of the sealing body 2 are thinly extended, and these extended end portions 4h are formed as a surface mounting structure. It is a thing. That is, the extended end 4h extended from the wide protruding portion 4a is bent to the lower surface side of the one-stage sealing body 2 in the middle, and the tip is the mounting portion 4e.

本実施例２の半導体装置１は幅広突出部分４ａの一縁から引き回し端子４ｂを形成することなく、幅広突出部分４ａの両端を延長させて実装部分４ｅを形成することから、半導体装置１の小型化を図ることができる。図１９では、実装部分４ｅが封止体２の両端から外側に突出した構造になっているが、実装部分４ｅの先端を封止体２の両端から突出しないようにすることによってさらに小型化、即ち、実装面積の縮小化が可能になる。   The semiconductor device 1 according to the second embodiment forms the mounting portion 4e by extending both ends of the wide protruding portion 4a without forming the lead terminal 4b from one edge of the wide protruding portion 4a. Can be achieved. In FIG. 19, the mounting portion 4 e has a structure that protrudes outward from both ends of the sealing body 2, but the mounting portion 4 e is further reduced in size by not protruding from both ends of the sealing body 2. That is, the mounting area can be reduced.

以上本発明者によってなされた発明を実施例に基づき具体的に説明したが、本発明は上記実施例に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。実施例では、パワーＭＯＳＦＥＴを半導体チップに組み込んだ例を示したが、組み込む素子としてはＭＩＳＦＥＴ，パワーバイポーラトランジスタ，ＩＧＢＴ等のトランジスタ、あるいはトランジスタを含むＩＣでもよい。   The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor. In the embodiment, an example in which a power MOSFET is incorporated in a semiconductor chip is shown. However, as an element to be incorporated, a transistor such as a MISFET, a power bipolar transistor, or an IGBT, or an IC including a transistor may be used.

本発明の実施例１である半導体装置の模式的断面図である。It is typical sectional drawing of the semiconductor device which is Example 1 of this invention. 実施例１の半導体装置の模式的平面図である。1 is a schematic plan view of a semiconductor device of Example 1. FIG. 実施例１の半導体装置の平面側からみた封止体内部の各部の配置状態を示す模式図である。FIG. 6 is a schematic diagram showing an arrangement state of each part inside the sealing body as viewed from the plane side of the semiconductor device of Example 1; 実施例１の半導体装置の正面図である。1 is a front view of a semiconductor device of Example 1. FIG. 実施例１の半導体装置の右側面図である。1 is a right side view of a semiconductor device according to Example 1; 実施例１の半導体装置の左側面図である。1 is a left side view of a semiconductor device according to Example 1; 実施例１の半導体装置の底面図である。2 is a bottom view of the semiconductor device of Example 1. FIG. 実施例１の半導体装置の底面側からみた封止体内部の各部の配置状態を示す模式図である。6 is a schematic diagram illustrating an arrangement state of each part inside the sealing body as viewed from the bottom surface side of the semiconductor device of Example 1. FIG. 実施例１の半導体装置の背面図である。1 is a rear view of a semiconductor device of Example 1. FIG. 実施例１の変形例である半導体装置の背面図である。FIG. 6 is a rear view of a semiconductor device that is a modification of the first embodiment. 実施例１の半導体装置の製造に使用するリードフレームの露出側面を示す一部拡大平面図である。3 is a partially enlarged plan view showing an exposed side surface of a lead frame used for manufacturing the semiconductor device of Example 1. FIG. 前記リードフレームのチップ固定側面を示す一部拡大底面図である。FIG. 3 is a partially enlarged bottom view showing a chip fixing side surface of the lead frame. 前記リードフレームに半導体チップを固定した状態を示す模式的拡大平面図である。FIG. 3 is a schematic enlarged plan view showing a state in which a semiconductor chip is fixed to the lead frame. 前記リードフレーム上の半導体チップにゲート電極板及びソース電極板となるリードフレーム部分を接続した状態を示す模式的拡大平面図である。FIG. 3 is a schematic enlarged plan view showing a state in which a lead frame portion serving as a gate electrode plate and a source electrode plate is connected to a semiconductor chip on the lead frame. 実装例１の半導体装置の製造において、封止体を形成した状態を示す模式的拡大平面図である。FIG. 10 is a schematic enlarged plan view showing a state where a sealing body is formed in the manufacture of the semiconductor device of mounting example 1; 実施例１の半導体装置に放熱フィンを取り付けた状態を示す模式的断面図である。FIG. 3 is a schematic cross-sectional view illustrating a state in which heat dissipation fins are attached to the semiconductor device of Example 1. 実施例１の半導体装置を実装基板に複数実装し、かつ各半導体装置に共通の放熱フィンを取り付けた状態を示す模式的断面図である。It is typical sectional drawing which shows the state which mounted the semiconductor device of Example 1 in multiple numbers on the mounting substrate, and attached the common radiation fin to each semiconductor device. 実施例１の半導体装置を実装基板に複数実装し、かつ各半導体装置に共通の放熱フィンを取り付けた状態を示す模式的平面図である。FIG. 3 is a schematic plan view showing a state in which a plurality of semiconductor devices of Example 1 are mounted on a mounting substrate and a common radiating fin is attached to each semiconductor device. 本発明の実施例２である半導体装置の模式的平面図である。It is a typical top view of the semiconductor device which is Example 2 of this invention. 実施例２の半導体装置の左側面図である。6 is a left side view of a semiconductor device according to Example 2. FIG. 実施例２の半導体装置の右側面図である。6 is a right side view of a semiconductor device according to Example 2. FIG. 実施例２の半導体装置の底面図である。6 is a bottom view of a semiconductor device according to Example 2. FIG. 実施例２の半導体装置の背面図である。6 is a rear view of a semiconductor device according to Example 2. FIG.

符号の説明Explanation of symbols

１…半導体装置、２…封止体（パッケージ）、４…ドレイン電極板、４ａ…幅広突出部分、４ｂ…引き回し端子、４ｃ…突出部分、４ｄ…延在部分、４ｅ…実装部分、４ｆ…開口部、４ｇ…斜面、４ｈ…延長端部、５…ゲート電極板、５ａ…屈曲部、５ｅ…実装部分、６…ソース電極板、６ａ…幅広部、６ｂ…端子部、６ｅ…実装部分、７…半導体チップ、８…ゲート電極、８ａ…突起電極（バンプ電極）、９…ソース電極、９ａ…突起電極（バンプ電極）、１１…接続材、２０…円形窪、２５…リードフレーム、２６…連結部、２７…ドレイン用突片、２８…スリット、４５…リードフレーム、４６…外枠、４７，４８…リード、５０…放熱フィン、５１…接合材、５２…台座部、５３…フィン、５５…実装基板、５６…放熱フィン、５７…フィン、５８…フィン部、５９…取付部、６０…支柱、６１…ビス、６２…バッファ   DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Sealing body (package), 4 ... Drain electrode plate, 4a ... Wide protrusion part, 4b ... Lead-out terminal, 4c ... Projection part, 4d ... Extension part, 4e ... Mounting part, 4f ... Opening Part, 4g ... slope, 4h ... extension end part, 5 ... gate electrode plate, 5a ... bent part, 5e ... mounting part, 6 ... source electrode plate, 6a ... wide part, 6b ... terminal part, 6e ... mounting part, 7 ... Semiconductor chip, 8 ... Gate electrode, 8a ... Projection electrode (bump electrode), 9 ... Source electrode, 9a ... Projection electrode (bump electrode), 11 ... Connection material, 20 ... Circular recess, 25 ... Lead frame, 26 ... Connection 27: Drain protrusion, 28 ... Slit, 45 ... Lead frame, 46 ... Outer frame, 47, 48 ... Lead, 50 ... Radiation fin, 51 ... Bonding material, 52 ... Base part, 53 ... Fin, 55 ... Mounting board, 56 ... radiating fin, 57 Fins, 58 ... fin portion, 59 ... mounting portion 60 ... post, 61 ... screw, 62 ... buffer

Claims (5)

第１の面、前記第１の面の反対の面となる第２の面及び前記第１の面と前記第２の面を接続する側面を有する絶縁性樹脂からなる封止体と、
前記封止体内に位置し第１の主面に複数の電極を有し、前記第１の主面の反対の第２の主面に電極を有する半導体チップと、
一面に前記半導体チップの第２の主面を接続し、前記一面の反対面となる他の一面を前記封止体の前記第１の面に露出させる電極板と、
一部が前記封止体の内部に位置して前記半導体チップの所定の前記電極に接続され、他の一部が前記封止体の側面から突出して前記封止体の第２の面側で表面実装可能な端子構造となる複数の電極板と、
前記封止体の前記第１の面に一面を露出させる前記電極板の一縁から突出し、前記封止体の側面に沿って延在し、かつ屈曲して前記封止体の第２の面側で表面実装可能となる引き回し端子とを有することを特徴とする半導体装置。 A sealing body made of an insulating resin having a first surface, a second surface opposite to the first surface, and a side surface connecting the first surface and the second surface;
A semiconductor chip located in the sealing body, having a plurality of electrodes on a first main surface, and having an electrode on a second main surface opposite to the first main surface;
An electrode plate for connecting the second main surface of the semiconductor chip to one surface and exposing the other surface opposite to the one surface to the first surface of the sealing body;
A part is located inside the sealing body and connected to the predetermined electrode of the semiconductor chip, and the other part protrudes from the side surface of the sealing body on the second surface side of the sealing body. A plurality of electrode plates having a surface-mountable terminal structure;
A second surface of the sealing body that protrudes from one edge of the electrode plate that exposes one surface on the first surface of the sealing body, extends along a side surface of the sealing body, and is bent. A semiconductor device having a routing terminal that can be surface-mounted on the side. 前記引き回し端子の表面実装部分は前記封止体の側面から突出する前記電極板の表面実装部分よりも長くなっていることを特徴とする請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein a surface mounting portion of the routing terminal is longer than a surface mounting portion of the electrode plate protruding from a side surface of the sealing body. 前記引き回し端子は前記電極板の両端側から突出し、かつ前記封止体の１辺に沿って延在していることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the lead terminal protrudes from both end sides of the electrode plate and extends along one side of the sealing body. 前記封止体の前記第１の面に一面を露出させる前記電極板上には熱伝導性の良好な弾性体を介して放熱フィンが固定されていることを特徴とする請求項１に記載の半導体装置。   The heat radiation fin is fixed to the electrode plate that exposes one surface on the first surface of the sealing body through an elastic body having good thermal conductivity. Semiconductor device. 前記半導体チップにはトランジスタが形成され、前記半導体チップの前記第２の主面には第２の電極が設けられ、
前記半導体チップの前記第１の主面には第１の電極と制御電極が設けられていることを特徴とする請求項１に記載の半導体装置。 A transistor is formed on the semiconductor chip, and a second electrode is provided on the second main surface of the semiconductor chip,
The semiconductor device according to claim 1, wherein a first electrode and a control electrode are provided on the first main surface of the semiconductor chip.
JP2003399196A 2003-11-28 2003-11-28 Semiconductor device Pending JP2005159238A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009278103A (en) * 2008-05-15 2009-11-26 Gem Services Inc Semiconductor package featuring flip-chip die sandwiched between metal layers
JP2011023463A (en) * 2009-07-14 2011-02-03 Denso Corp Semiconductor module
JP2021177516A (en) * 2020-05-08 2021-11-11 アオイ電子株式会社 Semiconductor device
EP4401131A1 (en) * 2023-01-12 2024-07-17 Infineon Technologies Austria AG A semiconductor package in a source-down configuration by use of vertical connectors

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009278103A (en) * 2008-05-15 2009-11-26 Gem Services Inc Semiconductor package featuring flip-chip die sandwiched between metal layers
JP2011023463A (en) * 2009-07-14 2011-02-03 Denso Corp Semiconductor module
US9449893B2 (en) 2009-07-14 2016-09-20 Denso Corporation Semiconductor module
JP2021177516A (en) * 2020-05-08 2021-11-11 アオイ電子株式会社 Semiconductor device
EP4401131A1 (en) * 2023-01-12 2024-07-17 Infineon Technologies Austria AG A semiconductor package in a source-down configuration by use of vertical connectors

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