JPH08250625A - Plastic molded type semiconductor device - Google Patents
Plastic molded type semiconductor deviceInfo
- Publication number
- JPH08250625A JPH08250625A JP4946895A JP4946895A JPH08250625A JP H08250625 A JPH08250625 A JP H08250625A JP 4946895 A JP4946895 A JP 4946895A JP 4946895 A JP4946895 A JP 4946895A JP H08250625 A JPH08250625 A JP H08250625A
- Authority
- JP
- Japan
- Prior art keywords
- surface side
- solder bumps
- chip
- resin
- heat dissipation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、放熱特性を改善した樹
脂封止型半導体装置及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device having improved heat dissipation characteristics and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】近年、樹脂基板の上面側に設けたＩＣチ
ップの接続電極と、下面側に設けた外部接続用のパッド
電極とをスル−ホ−ルを介して接続し、前記パッド電極
には半田パンプを設けると共に前記樹脂基板の上面を樹
脂封止してなる樹脂封止型半導体装置が開発され、これ
らの半導体装置はプラスチック・ボ−ルグリッドアレイ
（以後ＰＢＧＡと略記する）の名称にて商品化されてい
る。然るに、上記ＰＢＧＡは従来のセラミックＢＧＡに
比較して低価格にて製造出来るというメリットがある反
面、放熱特性が悪い為、端子数が少なく放熱特性が問題
にならない小型のＰＢＧＡにその用途が限定されるとい
う欠点があった。2. Description of the Related Art In recent years, a connecting electrode of an IC chip provided on the upper surface side of a resin substrate and a pad electrode for external connection provided on the lower surface side are connected via a through hole, and the pad electrode is connected to the pad electrode. Has developed a resin-sealed semiconductor device in which a solder bump is provided and the upper surface of the resin substrate is resin-sealed. These semiconductor devices are named plastic ball grid arrays (hereinafter abbreviated as PBGA). Have been commercialized. However, while the PBGA has the merit that it can be manufactured at a lower price than the conventional ceramic BGA, it has poor heat dissipation characteristics, so its application is limited to a small PBGA with a small number of terminals and heat dissipation characteristics are not a problem. There was a drawback that
【０００３】上記の欠点を解決する方法としては従来よ
り各種の提案があるが、特に回路基板の下面側に放熱す
る方式としては米国特許５、２８５、３５２号に開示が
ありその構成を図３により説明する。Various proposals have been made in the past as a method for solving the above-mentioned drawbacks. In particular, a method for radiating heat to the lower surface of a circuit board is disclosed in US Pat. No. 5,285,352, and its configuration is shown in FIG. Will be described.
【０００４】図３は回路基板の下面側に放熱機構を設け
たＰＢＧＡの断面図で、１は樹脂基板であり該樹脂基板
１の上面には接続電極２が、又下面側には外部接続用の
パッド電極３が形成され、前記樹脂基板１の上面側の接
続電極２と下面側のパッド電極３とはスル−ホ−ル４を
介して接続されている。更に樹脂基板１のＩＣチップ搭
載部には貫通穴５が形成され、該貫通穴５には熱伝導の
良い金属よりなる放熱ブロック６が埋設される事により
回路基板７が構成されている。FIG. 3 is a cross-sectional view of a PBGA in which a heat dissipation mechanism is provided on the lower surface side of a circuit board. Reference numeral 1 is a resin substrate, on the upper surface of which a connecting electrode 2 is provided, and on the lower surface side, for external connection. Pad electrode 3 is formed, and the connection electrode 2 on the upper surface side of the resin substrate 1 and the pad electrode 3 on the lower surface side are connected via a through hole 4. Further, a through hole 5 is formed in the IC chip mounting portion of the resin substrate 1, and a heat radiating block 6 made of a metal having good thermal conductivity is embedded in the through hole 5 to form a circuit board 7.
【０００５】そして前記回路基板１の上面側のＩＣチッ
プ搭載部にはＩＣチップ９が熱伝導の良い接着材１０に
より固着されると共に前記ＩＣチップ９の各電極はボン
ディング・ワイヤ−１１によって前記接続電極２に接続
されている。更に回路基板７の上面側を封止樹脂１２に
より封止した後、回路基板７の下面側のパッド電極３と
前記放熱ブロック６の下面とに半田バンプ１３を形成す
る事によりＰＢＧＡ１５が完成する。An IC chip 9 is fixed to an IC chip mounting portion on the upper surface side of the circuit board 1 by an adhesive 10 having good heat conductivity, and each electrode of the IC chip 9 is connected by a bonding wire-11. It is connected to the electrode 2. Further, after sealing the upper surface side of the circuit board 7 with the sealing resin 12, the PBGA 15 is completed by forming the solder bumps 13 on the pad electrodes 3 on the lower surface side of the circuit board 7 and on the lower surface of the heat dissipation block 6.
【０００６】上記構成を有するＰＢＧＡ１５は、図示し
ないマザ−ボ−ドに前記半田ボ−ル１３を溶融して実装
される事により、前記ＩＣチップ９に発生した発熱は熱
伝導の良い接着剤１０、放熱ブロック６、半田ボ−ル１
３を介してマザ−ボ−ド側に放出される。The PBGA 15 having the above-mentioned structure is mounted by melting the solder ball 13 on a mother board (not shown), so that the heat generated in the IC chip 9 has good thermal conductivity. , Heat dissipation block 6, solder ball 1
It is discharged to the mother board side via the No. 3.
【０００７】[0007]
【発明が解決しようとする課題】前記ＰＢＧＡ１５の構
成はＩＣチップの発熱を回路基板側に放出できる、とい
う点に於いて優れているが構成的には樹脂基板１の貫通
穴５に放熱ブロック６を整合して位置決めする方式であ
る為、樹脂基板１の厚さのバラツキや貫通穴５の加工制
度のバラツキの影響を受けやすく回路基板７の上面側及
び下面側の位置制度が安定せず、ＩＣチップ９の接着位
置や半田バンプ１３の形成高さが安定しないという問題
がある。The structure of the PBGA 15 is excellent in that the heat generated by the IC chip can be radiated to the circuit board side, but the heat dissipation block 6 is formed in the through hole 5 of the resin substrate 1 structurally. Since it is a method of aligning and aligning, the position accuracy of the upper surface side and the lower surface side of the circuit board 7 is not stable because it is easily affected by the variation in the thickness of the resin substrate 1 and the variation in the processing accuracy of the through hole 5. There is a problem that the bonding position of the IC chip 9 and the formation height of the solder bump 13 are not stable.
【０００８】[0008]
【課題を解決するための手段】本願の目的は上記従来の
問題を解決したＰＢＧＡを提供する事であり、上記目的
を達成するための本発明の要旨は下記の通りである。両
面銅張りした樹脂基板の上面側に設けたＩＣチップの接
続電極と、下面側に設けた外部接続用のパッド電極とを
スル−ホ−ルを介して接続し、前記パッド電極には半田
パンプを設けると共に前記樹脂基板の上面を樹脂封止し
てなる半導体装置に於いて、前記樹脂基板のＩＣチップ
搭載部に設けた貫通穴の下面側に放熱板を固定し、該放
熱板の上面側にＩＣチップを接着すると共に前記放熱板
の下面側に放熱用の半田バンプを設けた事を特徴とす
る。The object of the present application is to provide a PBGA which solves the above-mentioned conventional problems, and the gist of the present invention for achieving the above objects is as follows. An IC chip connection electrode provided on the upper surface side of a resin board with copper on both sides and a pad electrode for external connection provided on the lower surface side are connected via a through hole, and a solder bump is connected to the pad electrode. In a semiconductor device in which the upper surface of the resin substrate is sealed with resin, a heat sink is fixed to the lower surface side of the through hole provided in the IC chip mounting portion of the resin board, and the upper surface side of the heat sink plate is fixed. It is characterized in that an IC chip is adhered to and a solder bump for heat dissipation is provided on the lower surface side of the heat dissipation plate.
【０００９】又、前記パッド電極に形成された半田パン
プと前記放熱板の下面側に形成された放熱用の半田バン
プとは半田バンプの高さが異なることを特徴とする。Also, the solder bumps formed on the pad electrodes and the heat-dissipating solder bumps formed on the lower surface of the heat dissipation plate have different solder bump heights.
【００１０】[0010]
【実施例】図１は本発明の樹脂封止型半導体装置の実施
例であるＰＢＧＡの断面図であり図３に示すＰＢＧＡと
同一部材には同一番号を付し説明を省略する。図１に示
すＰＢＧＡ１５０に於いて図３にしめすＰＢＧＡ１５と
の違いは樹脂基板１の貫通穴５０をＩＣチップ９の径よ
りも大きく形成し、その貫通穴５０の下面側に放熱板２
０を固定し、該放熱板２０の上面側にＩＣチップ９を接
着すると共に前記放熱板２０の下面側に放熱用の半田バ
ンプ２３を設けたことである。1 is a sectional view of a PBGA which is an embodiment of a resin-sealed semiconductor device of the present invention. The same members as those of the PBGA shown in FIG. The difference between the PBGA 150 shown in FIG. 1 and the PBGA 15 shown in FIG. 3 is that the through hole 50 of the resin substrate 1 is formed larger than the diameter of the IC chip 9, and the heat sink 2 is formed on the lower surface side of the through hole 50.
0 is fixed, the IC chip 9 is bonded to the upper surface side of the heat dissipation plate 20, and solder bumps 23 for heat dissipation are provided on the lower surface side of the heat dissipation plate 20.
【００１１】次に図１に示すＰＢＧＡ５０の製造方法及
び各部の寸法に付いて説明する。前記放熱板２０として
は厚さ０．２ｍｍの金属板に表面処理として銀メッキを
施した構成が望ましい。上記構成の放熱板２０は熱伝導
度が良い上、上面側に接着されるＩＣチップのダイボン
ド材との密着力と封止樹脂との密着力がよく、又下面側
に形成される半田バンプとの濡れ性も良いためである。
前記放熱板２０を高温に耐える接着剤によって樹脂基板
１に強固に固定した後、ＩＣチップ９のダイボンデン
グ、ワイヤ−ボンデング、射出成形による封止樹脂の形
成を行う。Next, a method of manufacturing the PBGA 50 shown in FIG. 1 and dimensions of each part will be described. As the heat dissipation plate 20, it is preferable that a metal plate having a thickness of 0.2 mm is surface-treated with silver plating. The heat dissipation plate 20 having the above structure has good thermal conductivity, good adhesion to the die bonding material of the IC chip adhered to the upper surface and good adhesion to the sealing resin, and solder bumps formed on the lower surface. This is because the wettability of is good.
After the heat sink 20 is firmly fixed to the resin substrate 1 with an adhesive that withstands high temperatures, the IC chip 9 is die-bonded, wire-bonded, and injection-molded to form a sealing resin.
【００１２】次に半田バンプ１３及び２３の形成方法に
付き図１及び図２により説明する。図２は図１に示すＰ
ＢＧＡ１５０の下面図であり、樹脂基板１の下面には半
田バンプ１３が整列配置され、また放熱板２０の下面に
は放熱用半田バンプ２３が整列配置されている。ここで
半田バンプ１３は半田バンプ２３に比較して平面形状が
小さく、図１に示す如く高さが大きく形成されており、
この結果半田バンプ１３と半田バンプ２３とは放熱板２
０の厚みを補正して底面の位置（マザ−ボ−ドと接する
位置）が等しくなっている。Next, a method of forming the solder bumps 13 and 23 will be described with reference to FIGS. FIG. 2 shows P shown in FIG.
FIG. 3 is a bottom view of the BGA 150, in which solder bumps 13 are aligned on the lower surface of the resin substrate 1, and heat-dissipating solder bumps 23 are aligned on the lower surface of the heat dissipation plate 20. Here, the solder bump 13 has a smaller planar shape than the solder bump 23 and is formed to have a large height as shown in FIG.
As a result, the solder bumps 13 and the solder bumps 23 are separated from each other by the heat sink 2.
By correcting the thickness of 0, the positions of the bottom surface (positions in contact with the mother board) are made equal.
【００１３】一般に半田バンプの形成方法としてはパッ
ド電極上に半田バンプの外径を規制する丸窓を設けたレ
ジスト膜をラミネ−トし、前記各丸窓部に半田ボ−ルを
各々供給した後加熱処理を行って半田バンプを形成する
が、この時前記丸窓の径を変化させる事によって半田バ
ンプの高さを任意に変化させる事ができる。本実施例で
は、半田バンプ１３を形成する為の丸窓に対して半田バ
ンプ２３を形成する為の丸窓を少し大きく形成し、同じ
形状の半田ボ−ルを用いて加熱処理を行った結果、半田
バンプ１３の高さが０．７ｍｍに対し半田バンプ２３の
高さを０．５ｍｍに形成する事により、放熱板２０の高
さを補正して両半田バンプの高さを略等しくしている。Generally, as a method of forming a solder bump, a resist film having a round window for controlling the outer diameter of the solder bump is laminated on the pad electrode, and a solder ball is supplied to each round window. Although the post-heat treatment is performed to form the solder bumps, the height of the solder bumps can be arbitrarily changed by changing the diameter of the round window at this time. In this embodiment, the round window for forming the solder bumps 23 is formed slightly larger than the round window for forming the solder bumps 13, and the heat treatment is performed using the same shape solder balls. By forming the solder bumps 23 to have a height of 0.7 mm and the solder bumps 23 to have a height of 0.5 mm, the height of the heat dissipation plate 20 is corrected so that the heights of the two solder bumps are substantially equal. There is.
【００１４】尚、前記各実施例ではモ−ルド工程として
射出成形による樹脂封止を示したが本願はこれに限定さ
れる物ではなく、例えば熱可塑性樹脂によるポッティン
グ等の技術によって封止樹脂を形成する事も本願の範囲
に含まれるものである。In each of the above-mentioned embodiments, resin molding by injection molding is shown as the molding process, but the present invention is not limited to this. For example, a technique such as potting with a thermoplastic resin is used to mold the sealing resin. Forming is also included in the scope of the present application.
【００１５】[0015]
【発明の効果】上記のごとく本発明によれば、ＩＣチッ
プが発生する発熱を回路基板の下面側より放出する方式
に於いて、従来の様な放熱ブロック埋設するという面倒
な構成を取ることなく、単に放熱板を接着し、その下面
に設ける半田バンプの高さを制御すると言う簡単な構成
によって十分な放熱効果を達成する事が出来る為、放熱
特性を改善すると共に比較的コストアップを抑えた樹脂
封止型半導体装置を提供する事ができる。As described above, according to the present invention, in the system in which the heat generated by the IC chip is radiated from the lower surface side of the circuit board, it is possible to eliminate the troublesome construction of embedding the heat radiation block as in the conventional case. , A simple structure of simply adhering a heat dissipation plate and controlling the height of the solder bumps provided on the lower surface can achieve a sufficient heat dissipation effect, thus improving the heat dissipation characteristics and suppressing the cost increase relatively. A resin-sealed semiconductor device can be provided.
【図１】本発明の樹脂封止型半導体装置を示す断面図で
ある。FIG. 1 is a cross-sectional view showing a resin-encapsulated semiconductor device of the present invention.
【図２】本発明の樹脂封止型半導体装置の下面図であ
る。FIG. 2 is a bottom view of the resin-sealed semiconductor device of the present invention.
【図３】従来の樹脂封止型半導体装置を示す断面図であ
る。FIG. 3 is a cross-sectional view showing a conventional resin-sealed semiconductor device.
１ 樹脂基板 ３ パッド電極 ５、５０ 貫通穴 ７ 回路基板 ９ ＩＣチップ １２ 封止樹脂 １３ 半田バンプ ２３ 放熱用半田バンプ １５、１５０ 樹脂封止型半導体装置 ２０ 放熱板 1 Resin Substrate 3 Pad Electrodes 5 and 50 Through Holes 7 Circuit Board 9 IC Chip 12 Sealing Resin 13 Solder Bump 23 Heat Dissipating Solder Bumps 15 and 150 Resin Sealed Semiconductor Device 20 Heat Sink
Claims (2)
たＩＣチップの接続電極と、下面側に設けた外部接続用
のパッド電極とをスル−ホ−ルを介して接続し、前記パ
ッド電極には半田パンプを設けると共に前記樹脂基板の
上面を樹脂封止してなる半導体装置に於いて、前記樹脂
基板のＩＣチップ搭載部に設けた貫通穴の下面側に放熱
板を固定し、該放熱板の上面側にＩＣチップを接着する
と共に前記放熱板の下面側に放熱用の半田バンプを設け
た事を特徴とする樹脂封止型半導体装置。1. A pad for connecting an IC chip provided on the upper surface side of a double-sided copper-clad resin substrate and a pad electrode for external connection provided on the lower surface side are connected through a through hole to form the pad. In a semiconductor device in which a solder bump is provided on an electrode and the upper surface of the resin substrate is resin-sealed, a heat sink is fixed to the lower surface side of a through hole provided in an IC chip mounting portion of the resin substrate, A resin-encapsulated semiconductor device characterized in that an IC chip is adhered to the upper surface side of a heat dissipation plate and a solder bump for heat dissipation is provided on the lower surface side of the heat dissipation plate.
と前記放熱板の下面側に形成された放熱用の半田バンプ
とは半田バンプの高さが異なる請求項１記載の樹脂封止
型半導体装置。2. The resin-encapsulated semiconductor device according to claim 1, wherein the solder bumps formed on the pad electrodes and the heat-dissipating solder bumps formed on the lower surface of the heat dissipation plate have different solder bump heights. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04946895A JP3628058B2 (en) | 1995-03-09 | 1995-03-09 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04946895A JP3628058B2 (en) | 1995-03-09 | 1995-03-09 | Resin-sealed semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08250625A true JPH08250625A (en) | 1996-09-27 |
| JP3628058B2 JP3628058B2 (en) | 2005-03-09 |
Family
ID=12831981
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP04946895A Expired - Fee Related JP3628058B2 (en) | 1995-03-09 | 1995-03-09 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3628058B2 (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10341040A (en) * | 1997-06-09 | 1998-12-22 | Nec Corp | Optical semiconductor module and fabrication thereof |
| KR20000073182A (en) * | 1999-05-07 | 2000-12-05 | 마이클 디. 오브라이언 | semi-conductor package and manufacturing method thereof |
| KR20000074351A (en) * | 1999-05-20 | 2000-12-15 | 마이클 디. 오브라이언 | semi-conductor package and manufacturing method thereof |
| US6528882B2 (en) * | 2000-10-04 | 2003-03-04 | Advanced Semiconductor Engineering, Inc. | Thermal enhanced ball grid array package |
| US6664617B2 (en) | 2000-12-19 | 2003-12-16 | Convergence Technologies, Ltd. | Semiconductor package |
| US6787389B1 (en) | 1997-10-09 | 2004-09-07 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having pads for connecting a semiconducting element to a mother board |
| US7554194B2 (en) | 2006-11-08 | 2009-06-30 | Amkor Technology, Inc. | Thermally enhanced semiconductor package |
| WO2017047373A1 (en) * | 2015-09-15 | 2017-03-23 | 株式会社オートネットワーク技術研究所 | Circuit structure and electrical connection box |
-
1995
- 1995-03-09 JP JP04946895A patent/JP3628058B2/en not_active Expired - Fee Related
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10341040A (en) * | 1997-06-09 | 1998-12-22 | Nec Corp | Optical semiconductor module and fabrication thereof |
| US6787389B1 (en) | 1997-10-09 | 2004-09-07 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having pads for connecting a semiconducting element to a mother board |
| KR20000073182A (en) * | 1999-05-07 | 2000-12-05 | 마이클 디. 오브라이언 | semi-conductor package and manufacturing method thereof |
| KR20000074351A (en) * | 1999-05-20 | 2000-12-15 | 마이클 디. 오브라이언 | semi-conductor package and manufacturing method thereof |
| US6528882B2 (en) * | 2000-10-04 | 2003-03-04 | Advanced Semiconductor Engineering, Inc. | Thermal enhanced ball grid array package |
| US6664617B2 (en) | 2000-12-19 | 2003-12-16 | Convergence Technologies, Ltd. | Semiconductor package |
| US7554194B2 (en) | 2006-11-08 | 2009-06-30 | Amkor Technology, Inc. | Thermally enhanced semiconductor package |
| WO2017047373A1 (en) * | 2015-09-15 | 2017-03-23 | 株式会社オートネットワーク技術研究所 | Circuit structure and electrical connection box |
| JP2017060256A (en) * | 2015-09-15 | 2017-03-23 | 株式会社オートネットワーク技術研究所 | Circuit structure and electric connection box |
| US10334734B2 (en) | 2015-09-15 | 2019-06-25 | Autonetworks Technologies, Ltd. | Circuit assembly and electrical junction box |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3628058B2 (en) | 2005-03-09 |
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