JPH08250529A - Plastic molded type semiconductor device and manufacture thereof - Google Patents
Plastic molded type semiconductor device and manufacture thereofInfo
- Publication number
- JPH08250529A JPH08250529A JP7049467A JP4946795A JPH08250529A JP H08250529 A JPH08250529 A JP H08250529A JP 7049467 A JP7049467 A JP 7049467A JP 4946795 A JP4946795 A JP 4946795A JP H08250529 A JPH08250529 A JP H08250529A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- chip
- resin
- heat dissipation
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置のパッケージ
に関するもので、更に詳しくはボールグリッドアレイ型
の樹脂封止型半導体装置及びその製造方法に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device package, and more particularly to a ball grid array type resin-sealed semiconductor device and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】近年、ＩＣチップの高密度実装に伴い、
多数の電極を有する樹脂封止型半導体装置が開発されて
いる。その代表的なものとしては、ＰＧＡ（ピングリッ
ドアレイ）がある。ＰＧＡは回路基板の一方の面にＩＣ
チップを搭載して樹脂で封止し、他方の面にはＩＣチッ
プと接続した複数のピンを配置した構造をしている。Ｐ
ＧＡはマザーボードに対して着脱可能であるという利点
があるものの、ピンがあるので大型となり小型化が難し
い。2. Description of the Related Art In recent years, with the high-density mounting of IC chips,
A resin-sealed semiconductor device having a large number of electrodes has been developed. A typical example thereof is PGA (pin grid array). PGA is an IC on one side of the circuit board
The chip is mounted and sealed with resin, and a plurality of pins connected to the IC chip are arranged on the other surface. P
The GA has the advantage that it can be attached to and detached from the mother board, but since it has pins, it is large and difficult to miniaturize.
【０００３】そこで、このＰＧＡに代わる小型の樹脂封
止半導体装置として、ＢＧＡ（ボールグリッドアレイ）
が開発されている。一般的なＢＧＡの構造は、プリント
樹脂基板の上面側にＩＣチップのダイパターン、ワイヤ
ーボンディング用の接続電極及び全ての回路パターンと
接続する共通電極を形成し、下面側には半田バンプと接
続するパッド電極を形成する。なお前記接続電極とパッ
ド電極とを電気的に接続するするためのリード電極とは
スルーホールを介して接続されている両面回路基板で、
前記両面回路基板の上面側にＩＣチップを搭載し、ワイ
ヤーボンディングされたＩＣチップを熱硬化性の封止樹
脂でトランスファーモールドする。下面側のパッド電極
には半田バンプが形成され、マザーボード基板のパター
ンと導通する。所謂キャビティアップ型のＢＧＡは、Ｉ
Ｃチップ内部より発生する熱の放散が悪いと言う問題が
あった。Therefore, as a small resin-sealed semiconductor device replacing the PGA, a BGA (ball grid array) is used.
Is being developed. In a general BGA structure, a die pattern of an IC chip, a connection electrode for wire bonding, and a common electrode connected to all circuit patterns are formed on the upper surface side of a printed resin substrate, and solder bumps are connected on the lower surface side. A pad electrode is formed. The lead electrode for electrically connecting the connection electrode and the pad electrode is a double-sided circuit board connected through a through hole,
An IC chip is mounted on the upper surface of the double-sided circuit board, and the wire-bonded IC chip is transfer-molded with a thermosetting sealing resin. Solder bumps are formed on the pad electrodes on the lower surface and are electrically connected to the pattern on the motherboard substrate. The so-called cavity-up type BGA is
There is a problem that the heat generated from the inside of the C chip is poorly dissipated.
【０００４】上記の熱の放散を効果的にするために、従
来技術として、貫通穴を有する回路基板に放熱板を固着
して形成された凹部にＩＣチップを収納し、放熱板に直
接ＩＣチップを固着した、所謂キャビティダウン型のＢ
ＧＡがある。図７に於いて、２０は略四角形で板厚が
０．３mm程度のガラスエポキシ樹脂基板２枚で形成され
た多層基板であり、リード電極２１と、内層パターン２
２と、パッド電極２８と、内層パターン２２とパッド電
極２８とをつなぐスルーホール３０とからなる導電パタ
ーンを有し、又、多層基板２０の略中央部にはＩＣチッ
プ収納用の貫通穴２０ａ、２０ｂが形成さている。In order to effectively dissipate the above heat, as a conventional technique, an IC chip is housed in a recess formed by fixing a heat sink to a circuit board having a through hole, and the IC chip is directly mounted on the heat sink. So-called cavity down type B
There is a GA. In FIG. 7, reference numeral 20 denotes a multilayer substrate formed of two glass epoxy resin substrates each having a substantially square shape and a plate thickness of about 0.3 mm. The lead electrode 21 and the inner layer pattern 2 are provided.
2, a pad electrode 28, and a conductive pattern composed of a through hole 30 that connects the inner layer pattern 22 and the pad electrode 28, and a through hole 20a for accommodating an IC chip is provided at a substantially central portion of the multilayer substrate 20. 20b is formed.
【０００５】又、多層基板２０のパッド電極２８側の面
と反対側の面には、０．１mm程度の金属板よりなる放熱
板２３が接着シート２４で固着され、貫通穴２０ａと放
熱板２３とによりＩＣチップ収納凹部が形成されてい
る。更にパット電極側には該パット電極を露呈する開口
部を有するレジスト膜２９が形成されている。尚、貫通
穴２０ｂの厚さは、後述するボンディングワイヤーの高
さよりも厚く形成されている。Further, a heat dissipation plate 23 made of a metal plate having a thickness of about 0.1 mm is fixed to the surface of the multilayer substrate 20 opposite to the surface on the pad electrode 28 side with an adhesive sheet 24, and the through hole 20a and the heat dissipation plate 23 are provided. The IC chip storing recess is formed by the above. Further, a resist film 29 having an opening exposing the pad electrode is formed on the pad electrode side. The through hole 20b is formed to be thicker than the height of the bonding wire described later.
【０００６】次に、前記多層基板２０の貫通穴２０ａと
前記放熱板２３とにより形成された凹部にＩＣチップ２
５を搭載し、前記放熱板２３に直接接するように接着剤
２６にて固着する。前記ＩＣチップ２５の電極と前記リ
ード電極２１とをボンディングワイヤー３１で接続した
後、ＩＣチップ２５及びボンディングワイヤ３１を熱硬
化性の封止樹脂でトランスファーモールドにより樹脂封
止部３２を形成することにより、前記ＩＣチップ２５の
遮光と保護を行う。また多層基板２０に形成されている
複数のパッド電極２８に半田ボール３３を供給し、加熱
炉中で加熱することにより、半田バンプが形成される。
この半田バンプにより、図示しないマザーボード基板の
パターンと導通される。以上によりキャビティダウン型
のＢＧＡ３５が完成される。Next, the IC chip 2 is placed in the recess formed by the through hole 20a of the multilayer substrate 20 and the heat dissipation plate 23.
5 is mounted and fixed by an adhesive 26 so as to directly contact the heat dissipation plate 23. After the electrodes of the IC chip 25 and the lead electrodes 21 are connected by the bonding wires 31, the IC chips 25 and the bonding wires 31 are formed by transfer molding with a thermosetting sealing resin to form the resin sealing portion 32. Shields and protects the IC chip 25. Further, by supplying the solder balls 33 to the plurality of pad electrodes 28 formed on the multilayer substrate 20 and heating them in a heating furnace, solder bumps are formed.
The solder bumps are electrically connected to a pattern on the motherboard substrate (not shown). Through the above steps, the cavity-down type BGA 35 is completed.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、前述し
たキャビティダウン型のＢＧＡ３５ではＩＣチップ２５
が直接放熱板２３に固着されているので、ＩＣチップ２
５の放熱特性については良好であるが、次のような問題
点がある。即ち、前記ＢＧＡ３５は、多層の基板、即ち
ボンディングワイヤー３１の高さを考慮してトランスフ
ァーモールドを行うために、多層回路基板が必要とな
り、工程が複雑となって製作期間が長くなってコストア
ップになっていた。更に回路基板のサイドが露出してい
るため、吸湿性が高く回路基板の劣化及びＩＣ特性に悪
影響を及ぼす等の樹脂封止型半導体装置の信頼性を損な
う致命的な問題があった。However, in the above-mentioned cavity-down type BGA 35, the IC chip 25 is used.
Is directly fixed to the heat sink 23, the IC chip 2
Although the heat dissipation characteristics of No. 5 are good, there are the following problems. That is, the BGA 35 requires a multi-layer circuit board, that is, a multi-layer circuit board is required in order to perform the transfer molding in consideration of the height of the bonding wire 31, which complicates the process, prolongs the manufacturing period, and increases the cost. Was becoming. Furthermore, since the side of the circuit board is exposed, there is a fatal problem that the hygroscopicity is high and the reliability of the resin-sealed semiconductor device is impaired, such as deterioration of the circuit board and adversely affecting IC characteristics.
【０００８】本発明は上記従来の課題に鑑みなされたも
のであり、その目的は、放熱特性が優れ、小型で安価
な、信頼性の高い樹脂封止型半導体装置及びその製造方
法を提供するものである。The present invention has been made in view of the above conventional problems, and an object thereof is to provide a highly reliable resin-encapsulated semiconductor device which is excellent in heat dissipation characteristics, small in size, and inexpensive, and a manufacturing method thereof. Is.
【０００９】[0009]
【課題を解決するための手段】上記目的を達成するため
に、本発明における樹脂封止型半導体装置は、樹脂基板
の略中央部にＩＣチップを収納する貫通穴を有し、且つ
樹脂基板上にリード電極及びパッド電極を形成した回路
基板と、該回路基板の貫通穴を覆う如く回路基板に固着
した放熱板と、前記回路基板の貫通穴と前記放熱板とに
より形成された凹部に固着され、且つ前記リード電極と
ワイヤーボンディングされたＩＣチップと、該ＩＣチッ
プを封止する樹脂封止部と、前記パッド電極に半田バン
プを設けてなる樹脂封止型半導体装置において、前記回
路基板の一方の面のみ前記リード電極及びパッド電極を
形成し、他方の面に前記放熱板を固着すると共に、前記
樹脂封止部は前記パッド電極のみを露呈する開口部を設
ける如く、且つ前記回路基板の一方の面と側面及び前記
放熱板の側面を覆う如く形成し、前記半田バンプは前記
樹脂封止部の開口部に形成されていることを特徴とする
ものである。In order to achieve the above object, a resin-encapsulated semiconductor device according to the present invention has a through hole for accommodating an IC chip in a substantially central portion of a resin substrate, and the resin substrate has a through hole. A circuit board on which lead electrodes and pad electrodes are formed, a heat dissipation plate fixed to the circuit board so as to cover the through hole of the circuit board, and fixed to a recess formed by the through hole of the circuit board and the heat dissipation plate. An IC chip wire-bonded to the lead electrode, a resin encapsulating part for encapsulating the IC chip, and a solder bump on the pad electrode, wherein one of the circuit boards is provided. The lead electrode and the pad electrode are formed only on the surface, the heat sink is fixed to the other surface, and the resin sealing portion is provided with an opening exposing only the pad electrode. And as formed to cover the one surface and the side surface and the side surface of the heat radiating plate of the circuit board, the solder bump is characterized in that it is formed in the opening of the resin sealing portion.
【００１０】また、前記半田バンプは前記樹脂封止部の
開口部内に充填された半田ペーストと、該半田ペースト
上に搭載された半田ボールとからなることを特徴とする
ものである。Further, the solder bump is composed of a solder paste filled in an opening of the resin sealing portion and a solder ball mounted on the solder paste.
【００１１】また、本発明における樹脂封止型半導体装
置の製造方法は、前記放熱板を複数個取りする短冊状の
金属板に、個々の放熱板を区分するスリット形成工程
と、前記個々の放熱板に、一方の面にのみリード電極及
びパッド電極を有し、略中央部にＩＣチップを収納する
貫通穴を有し、前記貫通穴を覆う如く回路基板の他方の
面を固着する回路基板固着工程と、前記回路基板の貫通
穴と前記放熱板とにより形成された凹部にＩＣチップを
固着するダイボンディング工程と、前記ＩＣチップの電
極と前記回路基板のリード電極とをワイヤーで接続する
ワイヤーボンディング工程と、前記ワイヤーボンディン
グされたＩＣチップを覆い前記パッド電極を除く回路基
板の一方の面及び側面と、前記スリットによって露出さ
れた放熱板側面と、前記パッド電極上に開口部を形成す
る如く樹脂封止部を形成するトランスファーモールド工
程と、前記パッド電極上の開口部に半田ペーストを塗布
した後半田ボールを搭載し、加熱して半田バンプを形成
する半田バンプ形成工程と、前記スリットの連結部を切
り離す製品分離工程とからなることを特徴とするもので
ある。Further, in the method for manufacturing a resin-sealed semiconductor device according to the present invention, a slit forming step for dividing each heat sink into a strip-shaped metal plate having a plurality of heat sinks, and each heat sink. The plate has a lead electrode and a pad electrode on only one surface, a through hole for accommodating an IC chip in a substantially central portion, and the other surface of the circuit board is fixed so as to cover the through hole. Steps, a die bonding step of fixing an IC chip in a recess formed by the through hole of the circuit board and the heat dissipation plate, and wire bonding for connecting an electrode of the IC chip and a lead electrode of the circuit board with a wire. A step, one surface and a side surface of the circuit board that covers the wire-bonded IC chip and excludes the pad electrode, and a heat dissipation plate side surface exposed by the slit, The transfer molding step of forming a resin sealing portion so as to form an opening on the pad electrode, and applying solder paste to the opening on the pad electrode, mounting a solder ball, and heating to form a solder bump. And a product separation step of separating the connecting portions of the slits.
【００１２】[0012]
【作用】従って、本発明により得られる樹脂封止型半導
体装置の構造において、前述したように、回路基板は一
方の面のみリード電極とパッド電極を形成した片面の回
路基板で、その他方の面に放熱板を固着して形成された
凹部にＩＣチップを搭載し、樹脂封止部は複数のパッド
電極を露呈する開口部を形成するようにしたことによっ
て、回路基板の導電パターン面と封止上面との段差に関
係なく半田パッドと半田ボールの接続が取れることによ
り、多層回路基板が不要となり、片面回路基板でその機
能を満足することができ、その製造コストを低減でき
る。また厚みは薄くなり、回路基板は外気と接すること
なく耐吸湿性を有し、放熱板の固着強度は増すことにな
る。Therefore, in the structure of the resin-encapsulated semiconductor device obtained by the present invention, as described above, the circuit board is a single-sided circuit board on which the lead electrode and the pad electrode are formed on only one surface and the other surface. By mounting the IC chip in the recess formed by fixing the heat sink to the resin and forming the opening for exposing the plurality of pad electrodes in the resin sealing portion, the conductive pattern surface of the circuit board and the sealing are formed. Since the solder pad and the solder ball can be connected regardless of the step between the upper surface and the upper surface, the multi-layer circuit board becomes unnecessary, the function can be satisfied by the single-sided circuit board, and the manufacturing cost can be reduced. Further, the thickness becomes thin, the circuit board has moisture absorption resistance without coming into contact with the outside air, and the fixing strength of the heat dissipation plate is increased.
【００１３】また、本発明により得られる樹脂封止型半
導体装置の製造方法において、前述したように、前記放
熱板を複数個取りする短冊状の金属板は、回路基板固着
工程、ＩＣチップを固着するダイボンディング工程、ワ
イヤーボンディング工程、トランスファーモールド工
程、半田バンプ形成工程の治具の機能を有し、個々の放
熱板を区分するスリットは、トランスファーモールド工
程において封止樹脂部が回路基板及び放熱板の側面まで
覆う作用を行う。複数のパッド電極上の開口部は半田ペ
ーストを塗布した後半田ボールを搭載し、加熱して半田
バンプを形成することが可能である。Further, in the method for manufacturing a resin-sealed semiconductor device obtained by the present invention, as described above, the strip-shaped metal plate from which a plurality of the heat dissipation plates are taken is fixed on the circuit board and the IC chip. It has the function of a jig in the die bonding process, wire bonding process, transfer molding process, and solder bump forming process, and the slit that separates the individual heat sinks is the sealing resin part in the transfer mold process. It acts to cover the sides of the. It is possible to form solder bumps by applying solder paste to the openings on the plurality of pad electrodes and then mounting solder balls and heating the solder balls.
【００１４】[0014]
【実施例】以下図面に基づいて本発明における樹脂封止
型半導体装置とその製造方法を説明する。図１〜図６は
本発明の実施例で、図１は完成されたＢＧＡの断面図、
図２は図１に示す回路基板の平面図、図３〜図６は工程
説明図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS A resin-sealed semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings. 1 to 6 are embodiments of the present invention, FIG. 1 is a sectional view of a completed BGA,
2 is a plan view of the circuit board shown in FIG. 1, and FIGS. 3 to 6 are process diagrams.
【００１５】先ず図３において、前記放熱板４を複数個
（例えば、３個）取りする板厚０．１ｍｍ程度の短冊状
の熱伝導性の良い金属、例えばＣｕ−Ｗ系よりなる金属
板４ａに、３個の放熱板４を区分するように一部に連結
部４ｂを残してスリット４ｃと、四隅に作業用のガイド
穴４ｄを形成するスリット形成工程行う。First, referring to FIG. 3, a strip-shaped metal having a thickness of about 0.1 mm and having a good thermal conductivity, for example, a metal plate 4a made of a Cu--W system, for taking a plurality (for example, three) of the heat dissipation plates 4 is used. Then, a slit forming step is performed in which a slit 4c and a work guide hole 4d are formed at four corners, leaving a connecting portion 4b in a part so as to divide the three heat sinks 4.
【００１６】次に、図１及び図２で示す回路基板１は、
略四角形で板厚が０．３ｍｍ程度のガラスエポキシ樹脂
等よりなる樹脂基板で、略中央部にはＩＣチップを収納
する貫通穴１ａを有し、一方の面のみにリード電極２及
びパッド電極３が形成されている。Next, the circuit board 1 shown in FIG. 1 and FIG.
A resin substrate made of glass epoxy resin or the like having a substantially square shape and a plate thickness of about 0.3 mm, having a through hole 1a for accommodating an IC chip in a substantially central portion, and the lead electrode 2 and the pad electrode 3 only on one surface Are formed.
【００１７】図１及び図４に示すように、前記３個分の
放熱板４に、それぞれ前記回路基板１のＩＣチップを収
納する貫通穴１ａを覆う如く、回路基板１の他方の面を
接着シート５等の接着手段により固着する回路基板固着
工程を行う。As shown in FIGS. 1 and 4, the other surface of the circuit board 1 is bonded to the three heat dissipation plates 4 so as to cover the through holes 1a for accommodating the IC chips of the circuit board 1, respectively. A circuit board fixing step of fixing the sheet 5 or the like by an adhesive means is performed.
【００１８】図１及び図５に示すように、前記回路基板
１の貫通穴１ａと前記放熱板４とにより形成された凹部
にＩＣチップ６を搭載し、前記ＩＣチップ６を接着剤７
等にて固着するダイボンディング工程を行い、更に前記
ＩＣチップ６の電極と前記回路基板１のリード電極２と
をボンディングワイヤー８で接続するワイヤーボンディ
ング工程を行う。As shown in FIGS. 1 and 5, an IC chip 6 is mounted in a concave portion formed by the through hole 1a of the circuit board 1 and the heat dissipation plate 4, and the IC chip 6 is bonded with an adhesive 7.
Then, a die bonding step of fixing the IC chip 6 and the lead electrode 2 of the circuit board 1 with a bonding wire 8 is performed.
【００１９】図１及び図６（ａ）及び（ｂ）で示すよう
に、前記ワイヤーボンディングされたＩＣチップ６を覆
い前記パッド電極３を除く回路基板１の一方の面及び側
面と、前記スリット４ｃによって露出された放熱板４の
側面と、前記パッド電極３上に図示しない金型のピンで
押さえて開口部９ａを配設する如く、樹脂封止部９を形
成するトランスファーモールド工程を行う。従って回路
基板１は前記パッド電極３を除き樹脂封止部９で覆われ
て露出されることはない。また前記回路基板１と放熱板
４の側面は前記樹脂封止部９で共に覆われるので両者の
接着強度を増すことになる。As shown in FIGS. 1 and 6A and 6B, one side and side of the circuit board 1 covering the wire-bonded IC chip 6 and excluding the pad electrode 3 and the slit 4c. A transfer molding step is performed in which the resin sealing portion 9 is formed so as to dispose the opening 9a on the side surface of the heat dissipation plate 4 exposed by the above and the pad electrode 3 by pressing it with a pin of a mold (not shown). Therefore, the circuit board 1 is covered with the resin sealing portion 9 except the pad electrode 3 and is not exposed. Further, since the side surfaces of the circuit board 1 and the heat dissipation plate 4 are both covered with the resin sealing portion 9, the adhesive strength between them is increased.
【００２０】図１に示すように、前記パッド電極３上の
開口部９ａに半田ペースト１０を塗布した後、半田ボー
ル１１を供給し、例えば２２０〜２３０°Ｃで２０〜３
０秒の条件で加熱炉中で加熱することにより、図示しな
いマザーボード基板との接続用の半田バンプ１２を形成
する半田バンプ形成工程を行う。その後、前記スリット
４ｃの連結部４ｂを切り離す製品分離工程を行うことに
より３個のＢＧＡ１３が完成される。As shown in FIG. 1, after the solder paste 10 is applied to the opening 9a on the pad electrode 3, the solder ball 11 is supplied, for example, 20 to 3 at 220 to 230 ° C.
A solder bump forming step of forming solder bumps 12 for connection with a mother board (not shown) is performed by heating in a heating furnace under the condition of 0 second. After that, a product separating step of separating the connecting portion 4b of the slit 4c is performed, so that three BGAs 13 are completed.
【００２１】上述の如く、本実施例の特徴とするところ
は、前述したように、キャビティダウン型ＢＧＡで、リ
ード電極及びパッド電極を一方の面にのみ形成された片
面の回路基板の他方の面を、スリットで区分された多数
個取りする金属板の放熱板に固着し、ＩＣチップ搭載後
ワイヤーボンディングし、トランスファーモールドはパ
ッド電極のみを露呈する開口部を形成し回路基板の全面
及びスリットにより露出された放熱板の側面まで覆うよ
うに樹脂封止部を形成するものである。As described above, the feature of this embodiment is that, as described above, in the cavity-down type BGA, the lead electrode and the pad electrode are formed on only one surface of the other surface of the one-sided circuit board. Is fixed to a heat sink of a metal plate that is separated by slits, and is wire-bonded after mounting the IC chip, and the transfer mold is formed with an opening that exposes only the pad electrode and is exposed by the entire surface of the circuit board and the slit. The resin sealing portion is formed so as to cover the side surface of the heat dissipation plate.
【００２２】尚、上記実施例で示した放熱板４に替わっ
て図８に示す如く、スリット４ｃの部分に複数の切欠部
４ｅを形成した放熱板４を使用することにより、封止樹
脂９と放熱板４との固着力をより一層向上出来るもので
ある。It should be noted that, instead of the heat dissipation plate 4 shown in the above embodiment, by using a heat dissipation plate 4 having a plurality of notches 4e in the slit 4c as shown in FIG. The fixing force with the heat sink 4 can be further improved.
【００２３】[0023]
【発明の効果】以上説明したように、本発明によれば、
回路基板は単層の片面基板のみでよいので、両面の回路
基板は不要となるため薄型化及びコストダウンとなり、
更に樹脂封止部はパッド電極のみを露呈する開口部以外
の回路基板の側面を含む全面を覆うので、耐吸湿性が優
れ、回路基板及びＩＣ特性の信頼性を維持することがで
きる。また放熱板はスリットで区分された短冊状の金属
板のため、多数個取りする治具となり生産性が良く、更
に樹脂封止部がスリット内に回り込み、放熱板の側面ま
で覆うことになり、回路基板と放熱板の接着力をより強
化するものである。即ち本発明の樹脂封止型半導体装置
は放熱特性が優れ、単層構造により薄く、安価で、信頼
性の高い樹脂封止型半導体装置であり、生産性の優れた
製造方法を提供することが可能である等多大の効果を奏
するものである。As described above, according to the present invention,
Since the circuit board only needs to be a single-layer single-sided board, the circuit boards on both sides are not required, resulting in a thin structure and cost reduction.
Further, since the resin sealing portion covers the entire surface including the side surface of the circuit board other than the opening where only the pad electrode is exposed, the moisture resistance is excellent and the reliability of the circuit board and IC characteristics can be maintained. In addition, since the heat sink is a strip-shaped metal plate divided by slits, it becomes a jig to take many pieces and the productivity is good.Furthermore, the resin sealing part wraps around the slit and covers the side surface of the heat sink, It further strengthens the adhesive force between the circuit board and the heat sink. That is, the resin-encapsulated semiconductor device of the present invention is a resin-encapsulated semiconductor device that has excellent heat dissipation characteristics, is thin due to the single-layer structure, is inexpensive, and has high reliability, and can provide a manufacturing method with excellent productivity. It has a great effect such as possible.
【図１】本発明の実施例に係わる樹脂封止型半導体装置
の断面図である。FIG. 1 is a cross-sectional view of a resin-sealed semiconductor device according to an embodiment of the present invention.
【図２】図１の回路基板の平面図である。FIG. 2 is a plan view of the circuit board shown in FIG.
【図３】図１の樹脂封止型半導体装置の製造方法に係わ
る放熱板のスリット形成工程の平面図である。FIG. 3 is a plan view of a slit forming step of the heat dissipation plate according to the method of manufacturing the resin-encapsulated semiconductor device of FIG.
【図４】図１の回路基板固着工程の平面図である。FIG. 4 is a plan view of the circuit board fixing step of FIG. 1.
【図５】図１のワイヤーボンディング工程の断面図であ
る。5 is a cross-sectional view of the wire bonding process of FIG.
【図６】図１のトランスファーモールド工程を示し、図
６（ａ）は平面図、図６（ｂ）は断面図である。6A and 6B show the transfer molding step of FIG. 1, FIG. 6A being a plan view and FIG. 6B being a sectional view.
【図７】従来技術のキャビティダウン型ＢＧＡの断面図
である。FIG. 7 is a cross-sectional view of a conventional cavity-down type BGA.
【図８】本発明の実施例である複数の切欠部を形成した
放熱板を使用した樹脂封止型半導体装置の要部平面図で
ある。FIG. 8 is a plan view of a principal portion of a resin-sealed semiconductor device using a heat dissipation plate having a plurality of cutouts according to an embodiment of the present invention.
１ 回路基板 １ａ 貫通穴 ２ リード電極 ３ パッド電極 ４ 放熱板 ４ａ 短冊状の金属板 ４ｃ スリット ６ ＩＣチップ ８ ボンディングワイヤー ９ 樹脂封止部 ９ａ 開口部 １０ 半田ペースト １１ 半田ボール １２ 半田バンプ １３ ＢＧＡ 1 Circuit Board 1a Through Hole 2 Lead Electrode 3 Pad Electrode 4 Heat Sink 4a Strip Metal Plate 4c Slit 6 IC Chip 8 Bonding Wire 9 Resin Sealing Part 9a Opening 10 Solder Paste 11 Solder Ball 12 Solder Bump 13 BGA
───────────────────────────────────────────────────── フロントページの続き (72)発明者 竹之内 季久男 東京都田無市本町６丁目１番12号 シチズ ン時計株式会社田無製造所内 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Kikuo Takenouchi 6-12 Hommachi, Tanashi City, Tokyo Citizen Watch Co., Ltd. Tanashi Factory
Claims (3)
する貫通穴を有し、且つ樹脂基板上にリード電極及びパ
ッド電極を形成した回路基板と、該回路基板の貫通穴を
覆う如く回路基板に固着した放熱板と、前記回路基板の
貫通穴と前記放熱板とにより形成された凹部に固着さ
れ、且つ前記リード電極とワイヤーボンディングされた
ＩＣチップと、該ＩＣチップを封止する樹脂封止部と、
前記パッド電極に半田バンプを設けてなる樹脂封止型半
導体装置において、前記回路基板の一方の面のみ前記リ
ード電極及びパッド電極を形成し、他方の面に前記放熱
板を固着すると共に、前記樹脂封止部は前記パッド電極
のみを露呈する開口部を設ける如く、且つ前記回路基板
の一方の面と側面及び前記放熱板の側面を覆う如く形成
し、前記半田バンプは前記樹脂封止部の開口部に形成さ
れていることを特徴とする樹脂封止型半導体装置。1. A circuit board having a through hole for accommodating an IC chip in a substantially central portion of a resin board and having lead electrodes and pad electrodes formed on the resin board, and a circuit so as to cover the through hole of the circuit board. A heat dissipation plate fixed to the substrate, an IC chip fixed to the recess formed by the through hole of the circuit board and the heat dissipation plate, and wire-bonded to the lead electrode, and a resin seal for sealing the IC chip. Tobe,
In a resin-sealed semiconductor device in which solder bumps are provided on the pad electrodes, the lead electrodes and the pad electrodes are formed only on one surface of the circuit board, and the heat dissipation plate is fixed on the other surface of the circuit board. The sealing portion is formed so as to provide an opening portion that exposes only the pad electrode, and covers one surface and the side surface of the circuit board and the side surface of the heat dissipation plate, and the solder bump is the opening of the resin sealing portion. A resin-encapsulated semiconductor device, characterized in that it is formed in a portion.
部内に充填された半田ペーストと、該半田ペースト上に
搭載された半田ボールとからなることを特徴とする請求
項１記載の樹脂封止型半導体装置。2. The resin seal according to claim 1, wherein the solder bump is composed of a solder paste filled in an opening of the resin sealing portion and a solder ball mounted on the solder paste. Static semiconductor device.
属板に、個々の放熱板を区分するスリット形成工程と、
前記個々の放熱板に、一方の面にのみリード電極及びパ
ッド電極を有し、略中央部にＩＣチップを収納する貫通
穴を有し、前記貫通穴を覆う如く回路基板の他方の面を
固着する回路基板固着工程と、前記回路基板の貫通穴と
前記放熱板とにより形成された凹部にＩＣチップを固着
するダイボンディング工程と、前記ＩＣチップの電極と
前記回路基板のリード電極とをワイヤーで接続するワイ
ヤーボンディング工程と、前記ワイヤーボンディングさ
れたＩＣチップを覆い前記パッド電極を除く回路基板の
一方の面及び側面と、前記スリットによって露出された
放熱板側面と、前記パッド電極上に開口部を形成する如
く樹脂封止部を形成するトランスファーモールド工程
と、前記パッド電極上の開口部に半田ペーストを塗布し
た後半田ボールを搭載し、加熱して半田バンプを形成す
る半田バンプ形成工程と、前記スリットの連結部を切り
離す製品分離工程とからなることを特徴とする樹脂封止
型半導体装置の製造方法。3. A slit forming step for dividing each heat sink into a strip-shaped metal plate for taking a plurality of the heat sinks,
Each of the heat sinks has a lead electrode and a pad electrode on only one surface, a through hole for accommodating an IC chip in the substantially central portion, and the other surface of the circuit board is fixed so as to cover the through hole. A circuit board fixing step, a die bonding step of fixing an IC chip to a recess formed by the through hole of the circuit board and the heat dissipation plate, and a wire between the electrode of the IC chip and the lead electrode of the circuit board. A wire bonding step of connecting, one surface and a side surface of the circuit board that covers the wire-bonded IC chip and excludes the pad electrode, a heat dissipation plate side surface exposed by the slit, and an opening portion on the pad electrode. The transfer molding step of forming the resin sealing part as it is formed, and the solder ball is mounted after applying the solder paste to the opening on the pad electrode. And a solder bump forming step of forming a solder bump by heating, method of manufacturing a resin-sealed semiconductor device characterized by comprising a product separation step to separate the connecting portions of the slits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7049467A JPH08250529A (en) | 1995-03-09 | 1995-03-09 | Plastic molded type semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7049467A JPH08250529A (en) | 1995-03-09 | 1995-03-09 | Plastic molded type semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08250529A true JPH08250529A (en) | 1996-09-27 |
Family
ID=12831953
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7049467A Pending JPH08250529A (en) | 1995-03-09 | 1995-03-09 | Plastic molded type semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08250529A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999012174A1 (en) * | 1997-09-03 | 1999-03-11 | Siemens Aktiengesellschaft | Electrical component with a jacket and a connection area located in said jacket |
| US6288444B1 (en) | 1998-11-17 | 2001-09-11 | Fujitsu Limited | Semiconductor device and method of producing the same |
| US7476811B2 (en) | 2004-12-27 | 2009-01-13 | Fujitsu Limited | Semiconductor device and manufacturing method therefor |
| JP2012248889A (en) * | 2008-01-15 | 2012-12-13 | Dainippon Printing Co Ltd | Wiring member for semiconductor device, composite wiring member for semiconductor device, and resin-sealed-type semiconductor device |
-
1995
- 1995-03-09 JP JP7049467A patent/JPH08250529A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999012174A1 (en) * | 1997-09-03 | 1999-03-11 | Siemens Aktiengesellschaft | Electrical component with a jacket and a connection area located in said jacket |
| US6288444B1 (en) | 1998-11-17 | 2001-09-11 | Fujitsu Limited | Semiconductor device and method of producing the same |
| EP1003214A3 (en) * | 1998-11-17 | 2002-09-11 | Fujitsu Limited | Semiconductor device and method of producing the same |
| US7476811B2 (en) | 2004-12-27 | 2009-01-13 | Fujitsu Limited | Semiconductor device and manufacturing method therefor |
| JP2012248889A (en) * | 2008-01-15 | 2012-12-13 | Dainippon Printing Co Ltd | Wiring member for semiconductor device, composite wiring member for semiconductor device, and resin-sealed-type semiconductor device |
| JP2014143450A (en) * | 2008-01-15 | 2014-08-07 | Dainippon Printing Co Ltd | Wiring member for semiconductor device, composite wiring member for semiconductor device, and resin-sealed-type semiconductor device |
| US9324636B2 (en) | 2008-01-15 | 2016-04-26 | Dai Nippon Printing Co., Ltd. | Resin-sealed semiconductor device and associated wiring and support structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5620928A (en) | Ultra thin ball grid array using a flex tape or printed wiring board substrate and method | |
| US6545366B2 (en) | Multiple chip package semiconductor device | |
| US6265783B1 (en) | Resin overmolded type semiconductor device | |
| KR100260997B1 (en) | Semiconductor package | |
| US5800958A (en) | Electrically enhanced power quad flat pack arrangement | |
| US6528722B2 (en) | Ball grid array semiconductor package with exposed base layer | |
| US6664615B1 (en) | Method and apparatus for lead-frame based grid array IC packaging | |
| KR20050002220A (en) | Stack type Ball grid array package and method for manufacturing the same | |
| JPH0846085A (en) | Semiconductor device and method of manufacture | |
| KR20020078931A (en) | Carrier frame for semiconductor package and semiconductor package using it and its manufacturing method | |
| US6300685B1 (en) | Semiconductor package | |
| US20020039811A1 (en) | A method of manufacturing a semiconductor device | |
| KR19990006158A (en) | Ball grid array package | |
| KR100282290B1 (en) | Chip scale package and method for manufacture thereof | |
| JPH0883865A (en) | Resin sealed semiconductor device | |
| KR19980042513A (en) | Lead frame for semiconductor device and semiconductor device | |
| JPH08250529A (en) | Plastic molded type semiconductor device and manufacture thereof | |
| JP2768315B2 (en) | Semiconductor device | |
| JPS6352461A (en) | Semiconductor device | |
| JP4038021B2 (en) | Manufacturing method of semiconductor device | |
| JP3136274B2 (en) | Semiconductor device | |
| JPH10154768A (en) | Semiconductor device and its manufacturing method | |
| US20080087999A1 (en) | Micro BGA package having multi-chip stack | |
| KR100247641B1 (en) | Package and method of manufacturing the same | |
| JPH07122701A (en) | Semiconductor device, its manufacture, and lead frame for pga |