JP2005159129A - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP2005159129A
JP2005159129A JP2003397236A JP2003397236A JP2005159129A JP 2005159129 A JP2005159129 A JP 2005159129A JP 2003397236 A JP2003397236 A JP 2003397236A JP 2003397236 A JP2003397236 A JP 2003397236A JP 2005159129 A JP2005159129 A JP 2005159129A
Authority
JP
Japan
Prior art keywords
insulating layer
semiconductor element
connection pad
main surface
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003397236A
Other languages
Japanese (ja)
Inventor
Kazuhito Imuta
一仁 藺牟田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2003397236A priority Critical patent/JP2005159129A/en
Publication of JP2005159129A publication Critical patent/JP2005159129A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Abstract

<P>PROBLEM TO BE SOLVED: To provide a small-sized semiconductor device whose outer shape has the same size with an outer shape of a semiconductor element. <P>SOLUTION: The semiconductor device is provided with the plate-shaped semiconductor element 1 wherein an electrode 1a is formed on the outer peripheral part of one main surface; a first insulating layer 3a which is laminated on the central part of the one main surface of the semiconductor element 1, and in which a connection pad 4 is formed on the outer peripheral part; a second insulating layer 3b which is laminated on a central part of the first insulating layer, and in which an external connection pad 5 is formed on the surface; a bonding wire 7 which connects electrically the electrode 1a and the connection pad 4; and resin 8 for sealing which covers the one main surface exposing the surface on which the external connection pad 5 of the second insulating layer 3b was formed. <P>COPYRIGHT: (C)2005,JPO&amp;NCIPI

Description

本発明は、ICやLSI等の半導体素子を搭載した半導体装置に関するものである。   The present invention relates to a semiconductor device on which a semiconductor element such as an IC or LSI is mounted.

従来、ICやLSI等の半導体素子を気密に封止してなる半導体装置は、上面に電子部品が搭載される搭載部を有する絶縁基体と、搭載部から絶縁基体の下面等にかけて導出された配線導体とを具備する配線基板の搭載部に半導体素子を搭載し、蓋体や封止用樹脂で半導体素子を気密に封止した構成である。なお、配線基板には、半導体素子の他に容量素子等の受動素子が併せて搭載され実装される場合もある。   Conventionally, a semiconductor device in which a semiconductor element such as an IC or LSI is hermetically sealed includes an insulating base having a mounting portion on which an electronic component is mounted on an upper surface, and wiring derived from the mounting portion to the lower surface of the insulating base. A semiconductor element is mounted on a mounting portion of a wiring board having a conductor, and the semiconductor element is hermetically sealed with a lid or a sealing resin. In addition to the semiconductor elements, passive elements such as capacitive elements may be mounted and mounted on the wiring board in some cases.

半導体素子は、一般に、シリコン基板等の板状の半導体基板の一方主面に電子回路を形成するとともに、その一方主面の外周部に複数の電極が並んで形成された構成である。半導体素子に形成された電子回路や電極は、外気に露出していると、外気中の塵埃が付着したり酸化腐食が進行したりして、ICやLSI等の半導体素子として正常に機能しなくなるので、外気に接触しないように封止する必要がある。   The semiconductor element generally has a configuration in which an electronic circuit is formed on one main surface of a plate-shaped semiconductor substrate such as a silicon substrate, and a plurality of electrodes are formed side by side on the outer peripheral portion of the one main surface. If the electronic circuits and electrodes formed in the semiconductor element are exposed to the outside air, dust in the outside air adheres or oxidative corrosion progresses, so that it does not function normally as a semiconductor element such as an IC or LSI. Therefore, it is necessary to seal so as not to come into contact with outside air.

また、従来の配線基板として一般的なものは、酸化アルミニウム質焼結体等のセラミックスから成る複数の絶縁層が積層されて成り、上面に電子部品が搭載される搭載部を有する絶縁基体と、絶縁層の表面に形成された配線導体とにより形成されている。上下の絶縁層の配線導体間を電気的に接続する場合、絶縁層を厚み方向に貫通する貫通孔を設けるとともに貫通孔内に導体を充填して成る貫通導体が形成される。   Further, a general wiring board as a conventional one is formed by laminating a plurality of insulating layers made of ceramics such as an aluminum oxide sintered body, and has an insulating base having a mounting portion on which electronic components are mounted on the upper surface, The wiring conductor is formed on the surface of the insulating layer. When electrical connection is made between the wiring conductors of the upper and lower insulating layers, a through-hole is formed by providing a through-hole penetrating the insulating layer in the thickness direction and filling the through-hole with a conductor.

搭載部は、通常、絶縁基体の上面の中央部に形成されており、搭載部またはその周囲に配線導体の一部が露出している。この配線導体の露出部分は、半導体素子の一方主面の外周部に形成された電極を接続するための接続パッドとして機能し、電極と接続パッドとはボンディングワイヤ等を介して電気的に接続される。   The mounting portion is usually formed at the center of the upper surface of the insulating base, and a part of the wiring conductor is exposed at or around the mounting portion. The exposed portion of the wiring conductor functions as a connection pad for connecting an electrode formed on the outer peripheral portion of one main surface of the semiconductor element, and the electrode and the connection pad are electrically connected through a bonding wire or the like. The

また、配線導体のうち絶縁基体の下面側の導出端部には、外部接続用の接続パッドが形成されている。   In addition, a connection pad for external connection is formed at the lead-out end portion on the lower surface side of the insulating base in the wiring conductor.

そして、絶縁基体の上面中央の搭載部にIC,LSI等の半導体素子を搭載するとともに、半導体素子の電極を配線導体の露出部分にボンディングワイヤを介して接続し、半導体素子を蓋体や封止樹脂等により覆って封止することにより半導体装置が構成される。   Then, a semiconductor element such as an IC or LSI is mounted on the mounting portion in the center of the upper surface of the insulating base, and the electrode of the semiconductor element is connected to the exposed portion of the wiring conductor via a bonding wire so that the semiconductor element is sealed or sealed A semiconductor device is formed by covering and sealing with resin or the like.

そして、接続パッドを半田あるいは導電性樹脂を介して外部回路基板の回路導体に接続することにより半導体装置が外部回路基板に実装され、半導体素子が外部電気回路と電気的に接続される。
特開2002−118204号公報
Then, the semiconductor device is mounted on the external circuit board by connecting the connection pads to the circuit conductor of the external circuit board via solder or conductive resin, and the semiconductor element is electrically connected to the external electric circuit.
JP 2002-118204 A

しかしながら、従来の半導体装置においては、絶縁基体の上面の中央部に半導体素子が搭載される搭載部を有し、搭載部から絶縁基体の下面等にかけて配線導体を形成した配線基板の搭載部に半導体素子を搭載した構成であるため、絶縁基体に半導体素子を搭載するとともに蓋体や封止樹脂で封止するための面積を確保する必要があるので、半導体素子の外形よりも、配線基板の外形が小さくなることは無く、近時の半導体装置の小型化、特に半導体装置を平面視したときの小型化に限界があった。   However, the conventional semiconductor device has a mounting portion on which the semiconductor element is mounted at the center of the upper surface of the insulating base, and the semiconductor is mounted on the mounting portion of the wiring board in which the wiring conductor is formed from the mounting portion to the lower surface of the insulating base. Since the element is mounted, it is necessary to secure an area for mounting the semiconductor element on the insulating base and sealing with a lid or a sealing resin. However, there has been a limit to the recent miniaturization of semiconductor devices, particularly the miniaturization of semiconductor devices in plan view.

本発明は、上記従来の技術における問題点に鑑みて完成されたものであり、その目的は、半導体装置の外形を半導体素子の外形と同じ大きさとした小型の半導体装置を提供することにある。   The present invention has been completed in view of the above problems in the prior art, and an object of the present invention is to provide a small semiconductor device in which the outer shape of the semiconductor device is the same as the outer shape of the semiconductor element.

本発明の半導体装置は、一方主面の外周部に電極が形成された板状の半導体素子と、該半導体素子の前記一方主面の中央部に積層された、外周部に接続パッドが形成されている第1の絶縁層と、該第1の絶縁層の中央部に積層された、表面に外部接続パッドが形成されている第2の絶縁層と、前記電極および前記接続パッドを電気的に接続するボンディングワイヤと、前記第2の絶縁層の前記外部接続パッドが形成された表面を露出させて前記一方主面を覆う封止用樹脂とを具備していることを特徴とするものである。   In the semiconductor device of the present invention, a plate-like semiconductor element having an electrode formed on the outer peripheral portion of one main surface, and a connection pad formed on the outer peripheral portion laminated at the central portion of the one main surface of the semiconductor element. The first insulating layer, the second insulating layer laminated on the center of the first insulating layer and having an external connection pad formed on the surface, and the electrode and the connection pad electrically A bonding wire to be connected; and a sealing resin that exposes the surface of the second insulating layer on which the external connection pads are formed and covers the one main surface. .

本発明の半導体装置によれば、一方主面の外周部に電極が形成された板状の半導体素子と、半導体素子の一方主面の中央部に積層された、外周部に接続パッドが形成されている第1の絶縁層と、第1の絶縁層の中央部に積層された、表面に外部接続パッドが形成されている第2の絶縁層と、電極および接続パッドを電気的に接続するボンディングワイヤと、第2の絶縁層の外部接続パッドが形成された表面を露出させて一方主面を覆う封止用樹脂とを具備していることから、半導体素子の外形よりも第1の絶縁層の外形が小さく、また第1の絶縁層の外形よりも第2の絶縁層の外形が小さい。そのため、半導体素子の電極は、半導体素子よりも外形の小さい第1の絶縁層に形成された接続パッドにボンディングワイヤを介して電気的に接続されるとともに、第1の絶縁層よりも外形の小さい第2の絶縁層に形成された外部接続パッドを介して外部に接続することができるので、半導体装置の外形を半導体素子の外形と同じ大きさまで小さくできる。   According to the semiconductor device of the present invention, a plate-like semiconductor element having an electrode formed on the outer peripheral portion of one main surface, and a connection pad formed on the outer peripheral portion laminated on the central portion of the one main surface of the semiconductor element. A first insulating layer, a second insulating layer laminated on the center of the first insulating layer and having an external connection pad formed on the surface thereof, and bonding for electrically connecting the electrode and the connection pad Since it comprises a wire and a sealing resin that exposes the surface of the second insulating layer on which the external connection pads are formed and covers one main surface, the first insulating layer is more than the outer shape of the semiconductor element. The outer shape of the second insulating layer is smaller than the outer shape of the first insulating layer. Therefore, the electrode of the semiconductor element is electrically connected to the connection pad formed on the first insulating layer having a smaller outer shape than the semiconductor element through the bonding wire, and has an outer shape smaller than that of the first insulating layer. Since the external connection pad formed in the second insulating layer can be connected to the outside, the external shape of the semiconductor device can be reduced to the same size as the external shape of the semiconductor element.

また、本発明の半導体装置によれば、第1の絶縁層と封止用樹脂とにより、半導体素子の一方主面の電子回路や電極を確実に封止することができるため、半導体素子の封止の信頼性を良好に確保することができる。   In addition, according to the semiconductor device of the present invention, the electronic circuit and the electrode on the one main surface of the semiconductor element can be reliably sealed by the first insulating layer and the sealing resin. The reliability of stopping can be ensured satisfactorily.

本発明の半導体装置ついて図面に基づき以下に説明する。図1は、本発明の半導体装置の実施の形態の一例を示す断面図である。図1において、1は半導体素子、3aは第1の絶縁層、3bは第2の絶縁層、4は接続パッド、5は外部接続パッド、7はボンディングワイヤ、8は封止用樹脂である。これらの、半導体素子1,第1の絶縁層3a,第2の絶縁層3b,接続パッド4,外部接続パッド5,ボンディングワイヤ7および封止用樹脂8により本発明の半導体装置9が基本的に構成される。   The semiconductor device of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view showing an example of an embodiment of a semiconductor device of the present invention. In FIG. 1, 1 is a semiconductor element, 3a is a first insulating layer, 3b is a second insulating layer, 4 is a connection pad, 5 is an external connection pad, 7 is a bonding wire, and 8 is a sealing resin. The semiconductor device 9 of the present invention is basically constituted by the semiconductor element 1, the first insulating layer 3a, the second insulating layer 3b, the connection pad 4, the external connection pad 5, the bonding wire 7 and the sealing resin 8. Composed.

半導体素子1は、シリコン等の半導体から成る板状の基板の一方主面(図1の例では下面)の外周部に電極1aが形成された形状であり、一方主面の中央部には、通常、集積回路等の電子回路が形成されている。   The semiconductor element 1 has a shape in which an electrode 1a is formed on the outer peripheral portion of one main surface (lower surface in the example of FIG. 1) of a plate-like substrate made of a semiconductor such as silicon, Usually, an electronic circuit such as an integrated circuit is formed.

第1の絶縁層3aは、外周部に接続パッド4が形成されており、この接続パッド4等を形成するための基体として機能する。この第1の絶縁層3aの中央部には、第2の絶縁層3bが積層され、第2の絶縁層3bの表面には外部接続パッド5が形成されている。   The first insulating layer 3a has connection pads 4 formed on the outer peripheral portion, and functions as a base for forming the connection pads 4 and the like. A second insulating layer 3b is laminated at the center of the first insulating layer 3a, and an external connection pad 5 is formed on the surface of the second insulating layer 3b.

なお、第1および第2の絶縁層3a,3bから構成される絶縁層は、半導体素子1の一方主面の中央部に形成されている電子回路等を封止する封止材の一部として機能し、平面視で半導体素子1よりも外形の小さい四角形状である。   The insulating layer composed of the first and second insulating layers 3a and 3b is a part of a sealing material that seals an electronic circuit or the like formed in the central portion of one main surface of the semiconductor element 1. It is a quadrangular shape that functions and has a smaller outer shape than the semiconductor element 1 in plan view.

この場合、第1の絶縁層3aは、半導体素子1の一方主面を覆って封止する上では、電極1aにかからない範囲で、外形が大きければ大きいほど好ましいが、後述する封止用樹脂8との接合面積を確保して接合強度を確保するために、半導体素子1の外形よりも、各辺で0.6mm以上小さい四角板状に形成することが好ましい。   In this case, when the first insulating layer 3a covers and seals one main surface of the semiconductor element 1, it is preferable that the outer shape is larger as long as it does not cover the electrode 1a. In order to secure the joining area and secure the joining strength, it is preferable to form a square plate that is smaller than the outer shape of the semiconductor element 1 by 0.6 mm or more on each side.

第2の絶縁層3bは、接続パッド4にボンディングワイヤ7を接続するときの作業性や接続の信頼性を高くするために、接続パッド4が0.8mm以上の長さで露出するようにして形成することが好ましい。接続パッド4は、ボンディングワイヤ7を接続しやすくすること等のために、第1の絶縁層3aの外周部分に形成されるので、第2の絶縁層3bは、各辺で第1の絶縁層3aよりも0.8mm程度小さい四角板状になる。   The second insulating layer 3b is formed so that the connection pad 4 is exposed with a length of 0.8 mm or more in order to increase workability and connection reliability when the bonding wire 7 is connected to the connection pad 4. It is preferable to form. Since the connection pad 4 is formed on the outer peripheral portion of the first insulating layer 3a for easy connection of the bonding wire 7, the second insulating layer 3b is formed on the first insulating layer on each side. It becomes a square plate shape smaller by about 0.8 mm than 3a.

外部接続パッド5は、半導体装置9を外部電気回路に電気的に接続するための接続用導体として機能する。この外部接続パッド5は、第2の絶縁層3bの内部に形成された配線導体6を介して電気的に接続されている。外部接続パッド5を外部の電気回路(図示せず)に半田等を介して電気的に接続することにより、半導体素子の電極1aが、ボンディングワイヤ7,接続パッド4,配線導体6および外部接続パッド5を介して、外部の電気回路と電気的に接続される。   The external connection pad 5 functions as a connection conductor for electrically connecting the semiconductor device 9 to an external electric circuit. The external connection pad 5 is electrically connected through a wiring conductor 6 formed inside the second insulating layer 3b. By electrically connecting the external connection pad 5 to an external electric circuit (not shown) via solder or the like, the electrode 1a of the semiconductor element is bonded to the bonding wire 7, the connection pad 4, the wiring conductor 6, and the external connection pad. 5 is electrically connected to an external electric circuit.

なお、配線導体6は、図1の例では第2の絶縁層3bを厚み方向に貫通する貫通導体の形態で形成しているが、第2の絶縁層3bの側面等に形成してもよい。   The wiring conductor 6 is formed in the form of a through conductor that penetrates the second insulating layer 3b in the thickness direction in the example of FIG. 1, but may be formed on the side surface of the second insulating layer 3b or the like. .

第1および第2の絶縁層3a,3bは、酸化アルミニウム質焼結体,窒化アルミニウム質焼結体,ムライト質焼結体,窒化珪素質焼結体,炭化珪素質焼結体,ガラスセラミックス焼結体等のセラミック焼結体や、エポキシ樹脂,ポリイミド樹脂等の樹脂、またはセラミック粉末を樹脂で結合して成る複合材料等の電気絶縁材料により形成されている。   The first and second insulating layers 3a and 3b are made of an aluminum oxide sintered body, an aluminum nitride sintered body, a mullite sintered body, a silicon nitride sintered body, a silicon carbide sintered body, and a glass ceramic sintered body. It is formed of an electrically insulating material such as a ceramic sintered body such as a bonded body, a resin such as an epoxy resin or a polyimide resin, or a composite material formed by bonding ceramic powder with a resin.

第1および第2の絶縁層3a,3bは、生産性や両者の接合の信頼性を良好に確保するために、同じ材料で形成される。例えば、第1および第2の絶縁層3a,3bが酸化アルミニウム質焼結体から成る場合には以下のようにして作製される。まず、酸化アルミニウム,酸化珪素,酸化カルシウム,酸化マグネシウム等の原料粉末に適当な有機樹脂バインダ,溶剤を添加混合して泥漿状のセラミックスラリーを作製し、このセラミックスラリーをドクターブレード法やカレンダーロール法等のシート成形技術を採用してシート状となすことによって、四角板状の複数のセラミックグリーンシート(セラミック生シートで、以下、グリーンシートともいう)を得る。しかる後、グリーンシートを所定の順に上下に積層して積層体と成す。この積層体を還元雰囲気中で約1600℃の高温で焼成することによって、直方体状の第1および第2の絶縁層3a,3bから成る絶縁層が製作される。   The first and second insulating layers 3a and 3b are formed of the same material in order to ensure good productivity and reliability of bonding between them. For example, when the first and second insulating layers 3a and 3b are made of an aluminum oxide sintered body, they are manufactured as follows. First, an appropriate organic resin binder and solvent are added to and mixed with raw material powders such as aluminum oxide, silicon oxide, calcium oxide, and magnesium oxide to produce a slurry-like ceramic slurry. A plurality of square plate-like ceramic green sheets (ceramic green sheets, hereinafter also referred to as green sheets) are obtained by adopting a sheet forming technique such as the above. Thereafter, the green sheets are laminated in the predetermined order in a predetermined order to form a laminate. By firing this laminated body at a high temperature of about 1600 ° C. in a reducing atmosphere, an insulating layer made of the rectangular parallelepiped first and second insulating layers 3a and 3b is manufactured.

なお、第1の絶縁層3aと半導体素子1との接合は、樹脂接着剤やガラス等の電気絶縁性の接合材を介して行われる。   The first insulating layer 3a and the semiconductor element 1 are joined through an electrically insulating joining material such as a resin adhesive or glass.

接続パッド4や外部接続パッド5,配線導体6は、タングステンやモリブデン,銅,銀等の金属材料から成る。このような金属材料は、メタライズ導体,金属箔,めっき層等の形態で絶縁層に形成することができ、例えば、タングステンのメタライズ導体から成る場合、タングステンの粉末に有機溶剤,樹脂バインダ等を添加混練して得た金属ペーストを、各絶縁層3a,3bとなるグリーンシートの表面に所定パターンに印刷しておくことにより形成される。この場合、配線導体6を、図1に示したような、絶縁層3bを厚み方向に貫通する貫通導体とするには、予め絶縁層3bとなるグリーンシートに貫通孔を打抜き形成しておき、この貫通孔内に金属ペーストを印刷し充填しておくこと等により形成される。   The connection pad 4, the external connection pad 5, and the wiring conductor 6 are made of a metal material such as tungsten, molybdenum, copper, or silver. Such a metal material can be formed on the insulating layer in the form of a metallized conductor, metal foil, plating layer, etc. For example, when made of a tungsten metallized conductor, an organic solvent, a resin binder, etc. are added to the tungsten powder. The metal paste obtained by kneading is formed by printing a predetermined pattern on the surface of the green sheet to be the insulating layers 3a and 3b. In this case, in order to make the wiring conductor 6 a through conductor that penetrates the insulating layer 3b in the thickness direction as shown in FIG. 1, a through hole is punched and formed in the green sheet that becomes the insulating layer 3b in advance. The through-hole is formed by printing and filling a metal paste.

また、本発明の半導体装置は、第2の絶縁層3bの外部接続パッド5が形成された表面を露出させて半導体素子1の一方主面を覆う封止用樹脂8を具備している。封止用樹脂8は、半導体素子1の一方主面のうち絶縁層で覆われない部位を含めて覆い、半導体素子1の一方主面や電極1a,ボンディングワイヤ7等を覆い、半導体素子1を気密封止する機能を有する。   In addition, the semiconductor device of the present invention includes the sealing resin 8 that covers the one main surface of the semiconductor element 1 by exposing the surface of the second insulating layer 3b where the external connection pads 5 are formed. The sealing resin 8 covers a part of one main surface of the semiconductor element 1 that is not covered with the insulating layer, covers one main surface of the semiconductor element 1, the electrode 1 a, the bonding wire 7, etc. It has a function of hermetically sealing.

この場合、封止用樹脂8は、外部接続パッド5を露出させているので、外部接続パッド5を外部の電気回路に半田等を介して接続するときの妨げとなることはなく、半導体装置9の外部接続を容易かつ確実なものとすることができる。   In this case, the sealing resin 8 exposes the external connection pads 5, and therefore does not hinder the connection of the external connection pads 5 to an external electric circuit via solder or the like, and the semiconductor device 9 The external connection can be made easy and reliable.

このような封止用樹脂8は、エポキシ樹脂やシリコーン樹脂等の樹脂から成り、例えば、未硬化のエポキシ樹脂を、半導体素子1の一方主面に、外部接続パッド5が形成されている第2の絶縁層3bの主面を露出させるようにして塗布し、その後、加熱硬化させること等により形成される。   Such a sealing resin 8 is made of a resin such as an epoxy resin or a silicone resin. For example, an uncured epoxy resin is formed on the one main surface of the semiconductor element 1 with the external connection pads 5 formed thereon. The main surface of the insulating layer 3b is applied so as to be exposed, and then heated and cured.

このように封止用樹脂8で半導体素子1を封止する際、封止用樹脂8の側面が半導体素子1の側面よりも外側に出てしまうと、半導体装置9の小型化ができなくなるので、封止用樹脂8は、その側面が半導体素子1の側面と同じ平面上に位置するか、または若干内側に、電極1aが露出しない程度に位置するものとして形成する。また、電極1aが多数配列形成されている場合、封止用樹脂8は、その側面が、電極1aが形成されている部位では半導体素子1の側面と同じ平面上に位置するようにするとともに、電極1aと電極1aとの間の部位では内側に入り込ませるようにして形成してもよい。   Thus, when the semiconductor element 1 is sealed with the sealing resin 8, if the side surface of the sealing resin 8 protrudes outside the side surface of the semiconductor element 1, the semiconductor device 9 cannot be reduced in size. The sealing resin 8 is formed such that its side surface is located on the same plane as the side surface of the semiconductor element 1 or is located slightly inside so as not to expose the electrode 1a. When a large number of electrodes 1a are arranged, the sealing resin 8 has its side surface located on the same plane as the side surface of the semiconductor element 1 at the portion where the electrode 1a is formed. You may form so that it may enter inside in the site | part between the electrode 1a and the electrode 1a.

なお、本発明は上記の実施の形態に限定されるものではなく、本発明の要旨を逸脱しない範囲内であれば種々の変更は可能である。例えば、外部接続パッド5の露出表面に、ニッケル,銅,金等のめっき層を被着させて外部電気回路への接続を強固なものとするとともに、酸化腐食を有効に防止するようにしてもよい。   The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention. For example, a plated layer of nickel, copper, gold or the like is deposited on the exposed surface of the external connection pad 5 to strengthen the connection to the external electric circuit and effectively prevent oxidative corrosion. Good.

本発明の半導体装置の実施の形態の一例を示す断面図である。It is sectional drawing which shows an example of embodiment of the semiconductor device of this invention.

符号の説明Explanation of symbols

1・・・半導体素子
1a・・・電極
3a・・・第1の絶縁層
3b・・・第2の絶縁層
4・・・接続パッド
5・・・外部接続パッド
6・・・配線導体
7・・・ボンディングワイヤ
8・・・封止用樹脂
9・・・配線基板
DESCRIPTION OF SYMBOLS 1 ... Semiconductor element 1a ... Electrode 3a ... 1st insulating layer 3b ... 2nd insulating layer 4 ... Connection pad 5 ... External connection pad 6 ... Wiring conductor 7 ..Bonding wire 8 ... Resin for sealing 9 ... Wiring substrate

Claims (1)

一方主面の外周部に電極が形成された板状の半導体素子と、該半導体素子の前記一方主面の中央部に積層された、外周部に接続パッドが形成されている第1の絶縁層と、該第1の絶縁層の中央部に積層された、表面に外部接続パッドが形成されている第2の絶縁層と、前記電極および前記接続パッドを電気的に接続するボンディングワイヤと、前記第2の絶縁層の前記外部接続パッドが形成された表面を露出させて前記一方主面を覆う封止用樹脂とを具備していることを特徴とする半導体装置。 On the other hand, a plate-like semiconductor element having an electrode formed on the outer peripheral portion of the main surface, and a first insulating layer laminated on the central portion of the one main surface of the semiconductor element and having a connection pad formed on the outer peripheral portion A second insulating layer laminated on the center of the first insulating layer and having an external connection pad formed on the surface; a bonding wire for electrically connecting the electrode and the connection pad; A semiconductor device comprising: a sealing resin that exposes a surface of the second insulating layer on which the external connection pads are formed and covers the one main surface.
JP2003397236A 2003-11-27 2003-11-27 Semiconductor device Pending JP2005159129A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003397236A JP2005159129A (en) 2003-11-27 2003-11-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003397236A JP2005159129A (en) 2003-11-27 2003-11-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2005159129A true JP2005159129A (en) 2005-06-16

Family

ID=34722443

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003397236A Pending JP2005159129A (en) 2003-11-27 2003-11-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2005159129A (en)

Similar Documents

Publication Publication Date Title
JP5823043B2 (en) Electronic device mounting substrate, electronic device, and imaging module
JP6791719B2 (en) Substrate for mounting electronic components, electronic devices and electronic modules
US10985098B2 (en) Electronic component mounting substrate, electronic device, and electronic module
JP2000340687A (en) Package for storing semiconductor element
JP4711823B2 (en) Electronic component storage package and electronic device
JP6780996B2 (en) Wiring boards, electronics and electronic modules
JP2004288660A (en) Wiring board
JP2005159129A (en) Semiconductor device
JP4587587B2 (en) Electronic component mounting board
JP7433766B2 (en) Circuit boards, electronic components and electronic modules
JP2004281473A (en) Wiring board
JP4986500B2 (en) Laminated substrate, electronic device and manufacturing method thereof.
JP3850343B2 (en) Electronic component mounting board
JP2004281470A (en) Wiring board
CN110832773B (en) Package for housing electronic component, electronic device, and electronic module
JP4203501B2 (en) Semiconductor device
JP4423181B2 (en) Multiple wiring board
JP6818609B2 (en) Wiring substrate and imaging device
JP3801935B2 (en) Electronic component mounting board
JP2008160055A (en) Package for housing electronic components, package for multiple housing of electronic components and electronic device, and method of discriminating these
JP2001185675A (en) Semiconductor device
JP2006185977A (en) Wiring board
JP2004281471A (en) Wiring board
JP2005159130A (en) Wiring board
JP2020136310A (en) Circuit board, electronic component, and electronic module