JP2005150179A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2005150179A
JP2005150179A JP2003382023A JP2003382023A JP2005150179A JP 2005150179 A JP2005150179 A JP 2005150179A JP 2003382023 A JP2003382023 A JP 2003382023A JP 2003382023 A JP2003382023 A JP 2003382023A JP 2005150179 A JP2005150179 A JP 2005150179A
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semiconductor
semiconductor element
carrier
sealing resin
semiconductor device
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Shigeru Nonoyama
茂 野々山
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the creeping of a sealing resin 6 on the side and backside of a semiconductor carrier 3 while realizing high quality and reliability. <P>SOLUTION: The semiconductor device is composed of the semiconductor carrier 3 having a plurality of electrodes 4 and wiring patterns connected to the electrodes 4 on a top face while consisting of an insulating substrate having terminals 7 for an external connection electrically connected to the electrodes 4 and the wiring on a base. The semiconductor device is further composed of a semiconductor element 2 bonded with a plurality of the electrodes 4 on the top face of the carrier 3 by a plurality of bump electrodes 1 and the sealing resin 6 filling and coating an opening between the element 2 and the carrier 3 and the peripheral end of the element 2. In the semiconductor device, protrusions 10 are formed in parallel with the periphery of the element 2 linearly or in a face shape at the outer-peripheral end of the carrier 3 on the surface of the carrier 3. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、半導体素子の集積回路部を保護し、かつ外部装置と半導体素子の電気的接続を安定に確保し、小型で高密度な実装の要求に対応可能な半導体装置およびその製造方法に関するものである。   The present invention relates to a semiconductor device that protects an integrated circuit portion of a semiconductor element, stably secures an electrical connection between an external device and the semiconductor element, and can meet a demand for small and high-density mounting, and a method of manufacturing the same. It is.

また、情報通信機器、事務用電子機器、家庭用電子機器、測定装置、組立ロボット等の産業用電子機器、医療用電子機器、電子玩具等の小型化を容易にする半導体装置およびその製造方法に関するものである。   The present invention also relates to a semiconductor device that facilitates miniaturization of industrial electronic devices such as information communication devices, office electronic devices, household electronic devices, measuring devices, and assembly robots, medical electronic devices, and electronic toys, and a method for manufacturing the same. Is.

以下、従来の半導体装置について図面を参照しながら説明する。図８は従来の半導体装置の平面図である。図９は従来の半導体装置の断面図であり、図８のＤ−Ｄ’線部分の断面を示している。図８および図９において、従来の半導体装置の構成について説明する。   Hereinafter, a conventional semiconductor device will be described with reference to the drawings. FIG. 8 is a plan view of a conventional semiconductor device. FIG. 9 is a cross-sectional view of a conventional semiconductor device, showing a cross section taken along line D-D ′ of FIG. 8. 8 and 9, the structure of a conventional semiconductor device will be described.

まず、図８および図９に示すように従来の半導体装置は、半導体素子２の表面電極上に突起電極１を形成し、突起電極１が形成された面が下になるように半導体素子２を絶縁基体とした多層回路基板である半導体キャリア３上に搭載している。半導体キャリア３の上面には半導体素子２との電気的接続のために複数の電極４を形成し、電極４と半導体素子２上に形成された突起電極１が導電性接着剤５により電気的に接続されている。半導体素子２と半導体キャリア３との間の隙間に半導体素子２の周辺端部から封止樹脂６を注入し、半導体素子２と半導体キャリア３間および半導体素子２の周辺端部を封止樹脂６によって充填被覆されている。
特開平６−２２４２５９号公報（特許第２８２６０４９号） First, as shown in FIGS. 8 and 9, in the conventional semiconductor device, the protruding electrode 1 is formed on the surface electrode of the semiconductor element 2, and the semiconductor element 2 is placed so that the surface on which the protruding electrode 1 is formed faces down. It is mounted on a semiconductor carrier 3 which is a multilayer circuit board as an insulating base. A plurality of electrodes 4 are formed on the upper surface of the semiconductor carrier 3 for electrical connection with the semiconductor element 2, and the protruding electrodes 1 formed on the electrodes 4 and the semiconductor element 2 are electrically connected by the conductive adhesive 5. It is connected. The sealing resin 6 is injected from the peripheral end of the semiconductor element 2 into the gap between the semiconductor element 2 and the semiconductor carrier 3, and the sealing resin 6 is provided between the semiconductor element 2 and the semiconductor carrier 3 and the peripheral end of the semiconductor element 2. Filled with coating.
JP-A-6-224259 (Patent No. 2826049)

このような構造を有する半導体装置では、樹脂注入辺において、半導体素子２の端から半導体キャリア３端までの距離を十分確保しないと、封止樹脂６を注入する際に封止樹脂６が半導体キャリア３の側面や裏面に回りこみ、封止樹脂６の回り込みによる製品不良が発生する。   In the semiconductor device having such a structure, when the distance from the end of the semiconductor element 2 to the end of the semiconductor carrier 3 is not sufficiently secured at the resin injection side, the sealing resin 6 is used when the sealing resin 6 is injected. 3 wraps around the side surface and the back surface of the product 3, resulting in a product defect due to the sealing resin 6 wrapping around.

また、半導体素子２の表面電極の狭ピッチ化に伴い、突起電極１の小型化および半導体キャリア３の電極４の幅の細線化により、半導体素子２と半導体キャリア３の接続部分での接続領域が減少し、機械的接続強度が低下するため、半導体素子２の周辺端部を被覆する封止樹脂６の平面形状の凹凸が半導体素子２の各辺に対し大きくなると、半導体素子２の端周辺に発生する応力が不均一になり、半導体素子２と半導体キャリア３の接続部分で接続抵抗値の上昇並びに、機械的接続強度の劣化や破壊が発生する確率が高くなり、品質・信頼性を損なう問題が発生する可能性がある。   Further, as the pitch of the surface electrodes of the semiconductor element 2 is reduced, the projecting electrode 1 is reduced in size and the width of the electrode 4 of the semiconductor carrier 3 is reduced. Since the mechanical connection strength is decreased and the unevenness of the planar shape of the sealing resin 6 covering the peripheral edge of the semiconductor element 2 becomes larger with respect to each side of the semiconductor element 2, A problem that the generated stress becomes non-uniform, the connection resistance value increases at the connection portion of the semiconductor element 2 and the semiconductor carrier 3, and the probability that the mechanical connection strength deteriorates or breaks down, and the quality and reliability are impaired. May occur.

本発明は、上記問題を解決するために、半導体キャリア３の周辺端部に線状、或いは面状の突起部１０を形成することで、封止樹脂６を注入する際に封止樹脂６が半導体キャリア３の側面や裏面に回りこむことを防止し、
また半導体素子２の外周端部を被覆する封止樹脂６の平面形状を半導体素子２の各辺に対し、平行に形成することで、半導体素子２の各辺の接続部分に発生する応力を均一化し、接続性を安定化し、高い品質・信頼性を実現できる半導体装置およびその製造方法を提供することを目的とするものである。 In order to solve the above problem, the present invention forms a linear or planar protrusion 10 at the peripheral edge of the semiconductor carrier 3 so that the sealing resin 6 is injected when the sealing resin 6 is injected. Prevent it from wrapping around the side or back of the semiconductor carrier 3,
Further, by forming the planar shape of the sealing resin 6 covering the outer peripheral edge of the semiconductor element 2 in parallel with each side of the semiconductor element 2, the stress generated at the connecting portion of each side of the semiconductor element 2 is uniform. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that can realize high quality and reliability.

この発明の半導体装置は、絶縁性基板を有しその上面に電極４を有する半導体キャリア３と、前記電極４に突起電極１により接合された半導体素子２と、前記半導体素子２と前記半導体キャリア３との間の隙間に前記半導体素子２の周辺端部から注入されて前記半導体素子２と前記半導体キャリア３間および前記半導体素子２の周辺端部に充填被覆された封止樹脂６とを備えた半導体装置であって、前記半導体キャリア３上の表面上で前記半導体素子２の樹脂注入辺側に前記封止樹脂６をせき止める突起部１０を形成したことを特徴とするものである。   The semiconductor device according to the present invention includes a semiconductor carrier 3 having an insulating substrate and having an electrode 4 on its upper surface, a semiconductor element 2 bonded to the electrode 4 by a protruding electrode 1, the semiconductor element 2 and the semiconductor carrier 3 And a sealing resin 6 filled and coated between the semiconductor element 2 and the semiconductor carrier 3 and in the peripheral end of the semiconductor element 2. The semiconductor device is characterized in that a protrusion 10 is formed on the surface of the semiconductor carrier 3 to block the sealing resin 6 on the resin injection side of the semiconductor element 2.

上記構成において、前記突起部１０は前記半導体素子２の前記樹脂注入辺以外の三辺に対向する前記半導体キャリア３表面上にも形成されている。   In the above configuration, the protrusion 10 is also formed on the surface of the semiconductor carrier 3 facing the three sides of the semiconductor element 2 other than the resin injection side.

上記構成において、前記半導体素子２の前記樹脂注入辺側の前記突起部１０と前記樹脂注入辺との間の距離は、前記半導体素子２の前記樹脂注入辺以外の三辺とこれに対向する前記突起部１０との距離よりも大きい。   In the above-described configuration, the distance between the protrusion 10 on the resin injection side of the semiconductor element 2 and the resin injection side is the three sides of the semiconductor element 2 other than the resin injection side opposite to the three sides. It is larger than the distance to the protrusion 10.

この発明の半導体装置の製造方法は、半導体素子２の表面電極に突起電極１を形成する工程と、前記突起電極１が接合される電極４を有する絶縁性基板からなる半導体キャリア３の周辺端部に線状或いは面状の突起部１０を形成する工程と、前記半導体素子２上の前記突起電極１と前記突起電極１に対応した前記半導体キャリア３の前記電極４とを接続する工程と、前記半導体素子２と前記半導体キャリア３との間に形成された隙間に前記半導体素子２の周辺部の前記突起部１０側から封止樹脂６を注入し、前記封止樹脂６を硬化させる工程とを含むものである。   The method for manufacturing a semiconductor device according to the present invention includes a step of forming a protruding electrode 1 on a surface electrode of a semiconductor element 2 and a peripheral edge of a semiconductor carrier 3 comprising an insulating substrate having an electrode 4 to which the protruding electrode 1 is bonded. Forming a linear or planar protrusion 10 on the substrate, connecting the protruding electrode 1 on the semiconductor element 2 and the electrode 4 of the semiconductor carrier 3 corresponding to the protruding electrode 1, Injecting a sealing resin 6 into the gap formed between the semiconductor element 2 and the semiconductor carrier 3 from the protrusion 10 side at the periphery of the semiconductor element 2 and curing the sealing resin 6. Is included.

以上、詳細に説明したように、本発明によれば、以下のような効果を得ることが可能である。   As described above in detail, according to the present invention, the following effects can be obtained.

半導体素子２の樹脂注入辺に対し、半導体キャリア３の周辺端部の表面上で半導体素子２の樹脂注入辺に例えば平行に線状或いは面状の突起部１０を形成することにより、半導体素子２と半導体キャリア３間に封止樹脂６を注入する際に、封止樹脂６が半導体キャリア３の側面や裏面に回りこむことを防止することが可能となり、封止樹脂６の回りこみによる不良発生を低減することが可能となる。   By forming, for example, a linear or planar protrusion 10 parallel to the resin injection side of the semiconductor element 2 on the surface of the peripheral edge of the semiconductor carrier 3 with respect to the resin injection side of the semiconductor element 2, the semiconductor element 2. When the sealing resin 6 is injected between the semiconductor carrier 3 and the semiconductor resin 3, it is possible to prevent the sealing resin 6 from wrapping around the side surface or the back surface of the semiconductor carrier 3, and a defect caused by the wrapping of the sealing resin 6 occurs. Can be reduced.

この場合、半導体素子２の端から半導体キャリア３の端の距離を小さくし、かつ封止樹脂６の平面形状を半導体素子２の樹脂注入辺に対し平行に形成すれば、半導体素子２の樹脂注入辺の接続部分に発生する応力を均一化し、接続性を安定化することが可能となり、品質・信頼性が高くかつ小型な半導体装置を実現することが可能となる。   In this case, if the distance from the end of the semiconductor element 2 to the end of the semiconductor carrier 3 is reduced and the planar shape of the sealing resin 6 is formed parallel to the resin injection side of the semiconductor element 2, the resin injection of the semiconductor element 2 is performed. It is possible to make uniform the stress generated in the connecting portion of the side and stabilize the connectivity, and to realize a small semiconductor device with high quality and reliability.

半導体キャリア３の表面上で半導体素子２の樹脂注入辺以外の三辺においても、例えば半導体キャリア３の表面上で半導体素子２の各辺に平行に線状あるいは面状の突起部１０を形成することにより、半導体素子２の周辺端部を被覆する封止樹脂６の平面形状を半導体素子２の各辺に対し、平行に形成することが可能となり、半導体素子２の各辺の接続部分に発生する応力を均一化し、接続性を安定化させることで高い品質・信頼性を実現することが可能となる。   On three surfaces other than the resin injection side of the semiconductor element 2 on the surface of the semiconductor carrier 3, for example, linear or planar protrusions 10 are formed on the surface of the semiconductor carrier 3 in parallel with each side of the semiconductor element 2. As a result, the planar shape of the sealing resin 6 covering the peripheral edge of the semiconductor element 2 can be formed parallel to each side of the semiconductor element 2, and is generated at the connection portion of each side of the semiconductor element 2. It is possible to achieve high quality and reliability by equalizing the stress to be applied and stabilizing the connectivity.

半導体キャリア３の表面上で半導体素子２の樹脂注入辺に対し、半導体素子２端から線状、或いは面状の突起部１０までの距離を樹脂注入エリアが確保できるように、他の三辺と比較して距離が大きくなるよう、半導体素子２の樹脂注入辺の線状或いは面状の突起部１０を形成することにより、半導体素子２と半導体キャリア３との間の隙間に封止樹脂６を注入する際に、封止樹脂６の注入が容易になり、生産性の高い半導体装置を実現することが可能となる。   With respect to the resin injection side of the semiconductor element 2 on the surface of the semiconductor carrier 3, the other three sides are secured so that a distance from the end of the semiconductor element 2 to the linear or planar protrusion 10 can be secured. By forming a linear or planar protrusion 10 on the resin injection side of the semiconductor element 2 so as to increase the distance, the sealing resin 6 is placed in the gap between the semiconductor element 2 and the semiconductor carrier 3. When injecting, the sealing resin 6 can be easily injected, and a highly productive semiconductor device can be realized.

以下、本発明の第１の実施形態について、図面を参照しながら説明する。図１は本実施形態にかかる半導体装置の平面図である。図２は本実施形態にかかる半導体装置の断面図であり、図１のA−A’線部分の断面を示している。図１および図２において、第１の実施形態にかかる半導体装置の構成について説明する。   Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a plan view of the semiconductor device according to the present embodiment. FIG. 2 is a cross-sectional view of the semiconductor device according to the present embodiment, showing a cross section taken along line A-A ′ of FIG. 1. 1 and 2, the configuration of the semiconductor device according to the first embodiment will be described.

図１および図２に示す半導体装置は、上面に複数の電極４と電極４に接続された配線パターンを有すると共に、電極４および配線と電気的に接続された外部接続用端子７を底面に有した絶縁性基板からなる半導体キャリア３と、半導体キャリア３の上面の複数の電極４に対して導電性を有する複数の突起電極１により接合された半導体素子２と、半導体素子２と半導体キャリア３との間の隙間に半導体素子２の周辺端部の一辺から封止樹脂６を注入し、半導体素子２と半導体キャリア３間および半導体素子２の周辺端部を封止樹脂６で充填被覆している半導体装置である。なお、半導体キャリア３は、セラッミク基板等のアルミナ系や窒化アルミナ系からなる絶縁性の単層および多層回路基板等を用いる。   The semiconductor device shown in FIGS. 1 and 2 has a plurality of electrodes 4 on the top surface and a wiring pattern connected to the electrodes 4, and has an external connection terminal 7 electrically connected to the electrodes 4 and the wiring on the bottom surface. A semiconductor carrier 3 made of an insulating substrate, a semiconductor element 2 bonded to a plurality of electrodes 4 on the upper surface of the semiconductor carrier 3 by a plurality of projecting electrodes 1, a semiconductor element 2, and a semiconductor carrier 3 The sealing resin 6 is injected from one side of the peripheral edge of the semiconductor element 2 into the gap between the semiconductor element 2 and the peripheral edge of the semiconductor element 2 and the semiconductor element 2 are filled and covered with the sealing resin 6. It is a semiconductor device. The semiconductor carrier 3 uses an insulating single layer and multilayer circuit board made of alumina or alumina nitride such as a ceramic substrate.

また、突起電極１には、半田バンプやＡｕバンプ８等の金属バンプを用い（図７（ａ）参照）、Ａｕバンプ８を用いた場合、半導体キャリア３の上面の複数電極４と半導体素子２の表面電極間での接合には、Ａｕバンプ８上にＡｇペースト等の導電性接着剤５を供給し、半導体素子２の表面を下にして半導体キャリア３上に搭載し、導電接着剤５を硬化することで、半導体キャリア３と半導体素子２間での電気的および機械的接続を確保している。また、封止樹脂６には、低粘度のエポキシ系の封止樹脂６とか液状の封止樹脂６を使用することで、半導体素子２と半導体キャリア３との間の隙間に半導体素子２の周辺端部から封止樹脂６を注入し、半導体素子２と半導体キャリア３間および半導体素子２の周辺端部を封止樹脂６で充填被覆している。   Further, metal bumps such as solder bumps and Au bumps 8 are used for the protruding electrodes 1 (see FIG. 7A). When the Au bumps 8 are used, the plurality of electrodes 4 and the semiconductor element 2 on the upper surface of the semiconductor carrier 3 are used. For bonding between the surface electrodes, a conductive adhesive 5 such as an Ag paste is supplied onto the Au bump 8 and mounted on the semiconductor carrier 3 with the surface of the semiconductor element 2 facing down. Curing ensures electrical and mechanical connection between the semiconductor carrier 3 and the semiconductor element 2. Further, as the sealing resin 6, a low-viscosity epoxy-based sealing resin 6 or a liquid sealing resin 6 is used, so that the periphery of the semiconductor element 2 is formed in the gap between the semiconductor element 2 and the semiconductor carrier 3. The sealing resin 6 is injected from the end portion, and the gap between the semiconductor element 2 and the semiconductor carrier 3 and the peripheral end portion of the semiconductor element 2 are filled and covered with the sealing resin 6.

この発明における第１の実施形態としては、図１および図２に示すように、半導体キャリア３の周辺端部において、半導体素子２の樹脂注入辺側に半導体素子２の樹脂注入辺に平行に線状、或いは面状の突起部１０を形成することである。なお、半導体キャリア３の外周端部の線状、或いは面状の突起部１０については、アルミナ系や窒化アルミナ系等の絶縁材料をシート状で積層する方法を用いて形成したり、或いは絶縁材料や有機系の材料を用いて、ペースト状態でのスクリーン印刷やディスペンス方式の塗布等により、形成することが可能となる。   As a first embodiment of the present invention, as shown in FIGS. 1 and 2, a line parallel to the resin injection side of the semiconductor element 2 is provided on the resin injection side of the semiconductor element 2 at the peripheral edge of the semiconductor carrier 3. Or a planar projection 10 is formed. The linear or planar protrusions 10 at the outer peripheral edge of the semiconductor carrier 3 are formed by using a method of laminating an insulating material such as alumina or alumina nitride in the form of a sheet, or an insulating material. It can be formed by screen printing in a paste state or dispensing method coating using an organic material.

この発明の第２の実施形態を図３および図４に示す。第１の実施の形態において、半導体キャリア３の樹脂注入辺以外の三辺において、半導体キャリア３の表面上で半導体素子２の各辺に平行に線状、或いは面状の突起部１０を形成したものである。なお、線状、或いは面状の突起部１０の形成においては、第１の実施形態と同一の方法を用いることが可能である。この実施の形態によれば、封止樹脂６の平面形状が半導体素子２の全周にわたって各周辺に平行に形成される。   A second embodiment of the present invention is shown in FIGS. In the first embodiment, linear or planar protrusions 10 are formed in parallel with each side of the semiconductor element 2 on the surface of the semiconductor carrier 3 on three sides other than the resin injection side of the semiconductor carrier 3. Is. It should be noted that the same method as in the first embodiment can be used for forming the linear or planar protrusion 10. According to this embodiment, the planar shape of the sealing resin 6 is formed in parallel to each periphery over the entire circumference of the semiconductor element 2.

この発明の第３の実施形態を図５および図６に示す。第２の実施の形態において、半導体素子２の樹脂注入辺側に対し、樹脂注入エリアが確保できるよう、半導体素子２の端から線状、或いは面状の突起部１０までの距離を、他の三辺における半導体素子２の端から突起部１０までの距離と比較して、大きくしている。これにより、半導体素子２と半導体キャリア３との間の隙間に封止樹脂６を注入する際に、封止樹脂６の注入が容易になり、生産性の高い半導体装置を実現することが可能となる。   A third embodiment of the present invention is shown in FIGS. In the second embodiment, the distance from the end of the semiconductor element 2 to the linear or planar protrusion 10 is set so as to ensure a resin injection area with respect to the resin injection side of the semiconductor element 2. The distance from the end of the semiconductor element 2 on the three sides to the protrusion 10 is increased. As a result, when the sealing resin 6 is injected into the gap between the semiconductor element 2 and the semiconductor carrier 3, the sealing resin 6 can be easily injected, and a highly productive semiconductor device can be realized. Become.

また、半導体キャリア３の周辺端部に線状、或いは面状の突起部１０を形成することで、半導体キャリア３表面上に露出した配線パターンを被覆することが可能となり、配線パターンの露出エリアを低減することで、結露や人体接触等の影響による配線パターンの腐食を防止し、配線パターン間でのマイグレーションの発生等の不具合を防止することが可能となる。   Further, by forming the linear or planar protrusions 10 at the peripheral edge of the semiconductor carrier 3, it is possible to cover the wiring pattern exposed on the surface of the semiconductor carrier 3, and the exposed area of the wiring pattern can be reduced. By reducing it, it is possible to prevent corrosion of the wiring pattern due to the influence of dew condensation or human body contact, and to prevent problems such as occurrence of migration between the wiring patterns.

次に、本発明の半導体装置の製造方法の実施の形態について、第１の実施の形態を例として、図７（ａ）〜（ｄ）を参照しながら説明する。図７（ａ）は、半導体素子２の表面電極上にＡｕバンプ８を形成する工程を示す図である。図７（ｂ）〜図７（ｄ）は本実施の形態にかかる半導体装置の製造方法を工程別に示した部分断面図である。   Next, a semiconductor device manufacturing method according to an embodiment of the present invention will be described with reference to FIGS. 7A to 7D, taking the first embodiment as an example. FIG. 7A is a diagram illustrating a process of forming the Au bump 8 on the surface electrode of the semiconductor element 2. FIG. 7B to FIG. 7D are partial cross-sectional views showing the method of manufacturing the semiconductor device according to the present embodiment by process.

まず、図７（ａ）に示すように、ワイヤーボンディング法（ボールボンディング法）を用いて、露出した半導体素子２の電極４上にＡｕバンプ８（Ａｕ二段突起）を形成する。この方法は、キャピラリー９より出たＡｕワイヤーの先端に形成したボールをアルミニウム電極に熱圧接することにより、二段突起の下段部を形成し、さらにキャピラリー９を移動させることにより形成したＡｕワイヤーループをもって、二段突起の上段部を形成する。この状態においては、Ａｕ二段突起の高さは均一でなく、また頭頂部の平坦性にも欠けているために、Ａｕ二段突起を加圧することにより高さの均一化ならびに頭頂部の平坦化、いわゆるレベリングを行う。   First, as shown in FIG. 7A, Au bumps 8 (Au two-stage protrusions) are formed on the exposed electrodes 4 of the semiconductor element 2 by using a wire bonding method (ball bonding method). In this method, a ball formed at the tip of the Au wire protruding from the capillary 9 is heat-welded to the aluminum electrode to form a lower step portion of the two-step projection, and further, an Au wire loop formed by moving the capillary 9 To form the upper step of the two-step projection. In this state, the height of the Au two-step protrusion is not uniform, and the flatness of the top of the head is also lacking. Therefore, by pressing the Au two-step protrusion, the height is made uniform and the top of the head is flat. Or so-called leveling.

次に、回転する円盤上にドクターブレード法を用いて適当な厚みにＡｇ−Ｐｄを導電物質として含有する導電性接着剤５を塗布する。この際、導電性接着剤５にＡｕバンプ８を設けた半導体素子２を押し当てた後に引き上げる方法、いわゆる転写法によって、図７（ｂ）に示すように、Ａｕバンプ８に導電性接着剤５を供給する。導電性接着剤５としては、信頼性および熱応力などを考慮して例えばバインダーとしてエポキシレジン、導体フィラーとしてＡｇ−Ｐｄ合金によりなる接着剤５を用いている。   Next, the conductive adhesive 5 containing Ag—Pd as a conductive material is applied to a suitable thickness on the rotating disk using a doctor blade method. At this time, as shown in FIG. 7B, the conductive adhesive 5 is applied to the Au bumps 8 by a method in which the semiconductor element 2 provided with the Au bumps 8 is pressed against the conductive adhesive 5 and then pulled up, that is, a so-called transfer method. Supply. As the conductive adhesive 5, for example, an adhesive 5 made of an epoxy resin as a binder and an Ag—Pd alloy as a conductor filler is used in consideration of reliability and thermal stress.

次に図７（ｃ）に示すように、半導体素子２の表面を下にして実装する方法であるフリップチップ方式によって半導体素子２上の導電性接着剤５が供給されたＡｕバンプ８と、半導体キャリア３の表面上の外周端部に線状、或いは面状の突起部１０を形成し、底面に外部接続用端子７が一定の間隔で格子状に形成されている半導体キャリア３上の電極４とを位置精度よく合わせて接合した後、一定の温度にて熱硬化させる。   Next, as shown in FIG. 7C, the Au bump 8 supplied with the conductive adhesive 5 on the semiconductor element 2 by a flip chip method, which is a method of mounting with the surface of the semiconductor element 2 down, and the semiconductor The electrode 4 on the semiconductor carrier 3 is formed with a linear or planar protrusion 10 at the outer peripheral end on the surface of the carrier 3 and the external connection terminals 7 are formed in a lattice at regular intervals on the bottom. Are bonded together with high positional accuracy and then cured at a constant temperature.

次に、図７（ｄ）に示すようにエポキシ系の封止樹脂６を半導体素子２の周辺端部と、半導体素子２と半導体キャリア３との間に形成された隙間に注入し、一定の温度にて硬化させて樹脂モールドする。この樹脂モールドの方法としては、封止樹脂６を注入ノズルを用いて一方向すなわち突起部１０側から半導体素子２と半導体キャリア３との間に形成された隙間に注入し、隙間を埋めてから半導体素子２の周辺端部を封止する。封止樹脂６としてエポキシ系樹脂に高熱伝導セラミックである窒化アルミニウム（ＡｌＮ）もしくは窒化珪素（ＳｉＣ）等をフィラーとして添加したものを用いる。封止樹脂６の供給後、オーブン中で加熱をすることにより封止樹脂６を硬化させる。なお、半導体素子２の周辺端部を被覆する封止樹脂６の傾斜面は、半導体素子２の端面から半導体キャリア３の平面に対し、６０度以下の角度で形成されている。   Next, as shown in FIG. 7 (d), an epoxy-based sealing resin 6 is injected into the peripheral edge of the semiconductor element 2 and the gap formed between the semiconductor element 2 and the semiconductor carrier 3 to obtain a certain level. Harden at temperature and mold with resin. As a method of this resin molding, the sealing resin 6 is injected into a gap formed between the semiconductor element 2 and the semiconductor carrier 3 from one direction, that is, from the protruding portion 10 side, using an injection nozzle, and the gap is filled. The peripheral edge of the semiconductor element 2 is sealed. As the sealing resin 6, an epoxy resin obtained by adding aluminum nitride (AlN) or silicon nitride (SiC), which is a high thermal conductive ceramic, as a filler is used. After supplying the sealing resin 6, the sealing resin 6 is cured by heating in an oven. The inclined surface of the sealing resin 6 covering the peripheral edge of the semiconductor element 2 is formed at an angle of 60 degrees or less with respect to the plane of the semiconductor carrier 3 from the end face of the semiconductor element 2.

図１から図６に示すように、本発明の半導体装置の製造方法は、半導体キャリア３の外周端部に線状、或いは面状の突起部１０を形成する工程を有する半導体装置の製造方法である。半導体キャリア３の外周端部の線状、或いは面状の突起部１０の形成については、アルミナ系や窒化アルミナ系等の絶縁材料をシート状で積層する方法を用いたり、或いは絶縁材料や有機系の材料を用いて、ペースト状態のスクリーン印刷やディスペンス方式の塗布 等により、形成することが可能となる。   As shown in FIGS. 1 to 6, the method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device including a step of forming a linear or planar protrusion 10 on an outer peripheral end portion of a semiconductor carrier 3. is there. For forming the linear or planar protrusions 10 on the outer peripheral edge of the semiconductor carrier 3, a method of laminating an insulating material such as alumina or alumina nitride in a sheet form, or using an insulating material or an organic material. This material can be formed by paste-type screen printing or dispensing method coating.

なお、本実施の形態では、半導体キャリア３の表面上に形成した線状あるいは面状の突起部１０について、樹脂注入辺以外の線状あるいは面状の突起部１０においては、半導体素子２の端から線状あるいは面状の突起部１０までの距離を０．５ｍｍ以下とし、封止樹脂６を注入する辺においては、半導体素子２の端から線状あるいは面状の突起部１０までの距離を１．０ｍｍ以下になるよう、線状あるいは面状の突起部１０を形成することとした。   In the present embodiment, the linear or planar protrusion 10 formed on the surface of the semiconductor carrier 3 is the end of the semiconductor element 2 in the linear or planar protrusion 10 other than the resin injection side. And the distance from the end of the semiconductor element 2 to the linear or planar protrusion 10 on the side where the sealing resin 6 is injected is 0.5 mm or less. The linear or planar protrusion 10 was formed so as to be 1.0 mm or less.

本発明にかかる半導体装置およびその製造方法は、半導体素子２の外周部を被覆する封止樹脂６の平面形状を制御することが可能となり、封止樹脂６が半導体キャリア３の側面や裏面に回りこむことを防止でき、封止樹脂６の回りこみによる不良発生を低減することが可能となる等の効果があり、より小型化が必要な情報通信機器等に用いる半導体装置およびその製造方法として有用である。   The semiconductor device and the manufacturing method thereof according to the present invention can control the planar shape of the sealing resin 6 that covers the outer peripheral portion of the semiconductor element 2, and the sealing resin 6 travels around the side surface and the back surface of the semiconductor carrier 3. The semiconductor device can be prevented from being indented, has the effect of reducing the occurrence of defects due to the encroachment of the sealing resin 6, and is useful as a semiconductor device used for information communication equipment and the like that require further downsizing and a method for manufacturing the same. It is.

本発明の第１の実施形態にかかる半導体装置の平面図である。1 is a plan view of a semiconductor device according to a first embodiment of the present invention. そのＡ−Ａ′線断面図である。It is the AA 'sectional view taken on the line. 本発明の第２の実施形態にかかる半導体装置の平面図である。It is a top view of the semiconductor device concerning the 2nd Embodiment of this invention. そのＢ−Ｂ′線断面図である。It is the BB 'sectional view taken on the line. 本発明の第３の実施形態にかかる半導体装置の平面図である。It is a top view of the semiconductor device concerning a 3rd embodiment of the present invention. そのＣ−Ｃ′線断面図である。It is the CC 'sectional view taken on the line. 本発明の半導体装置の製造方法の実施の形態を示す工程図である。It is process drawing which shows embodiment of the manufacturing method of the semiconductor device of this invention. 従来の半導体装置を示す平面図である。It is a top view which shows the conventional semiconductor device. 従来の半導体装置を示す断面図である。It is sectional drawing which shows the conventional semiconductor device.

符号の説明Explanation of symbols

１ 突起電極
２ 半導体素子
３ 半導体キャリア
４ 電極
５ 導電性接着剤
６ 封止樹脂
７
８ Ａｕバンプ
９ キャピラリー
１０ 線状あるいは面状の突起部 DESCRIPTION OF SYMBOLS 1 Protruding electrode 2 Semiconductor element 3 Semiconductor carrier 4 Electrode 5 Conductive adhesive 6 Sealing resin 7
8 Au bump 9 Capillary 10 Linear or planar protrusion

Claims (4)

絶縁性基板を有しその上面に電極を有する半導体キャリアと、前記電極に突起電極により接合された半導体素子と、前記半導体素子と前記半導体キャリアとの間の隙間に前記半導体素子の周辺端部から注入されて前記半導体素子と前記半導体キャリア間および前記半導体素子の周辺端部に充填被覆された封止樹脂とを備えた半導体装置であって、前記半導体キャリア上の表面上で前記半導体素子の樹脂注入辺側に前記封止樹脂をせき止める突起部を形成したことを特徴とする半導体装置。   A semiconductor carrier having an insulating substrate and having an electrode on its upper surface, a semiconductor element joined to the electrode by a protruding electrode, and a gap between the semiconductor element and the semiconductor carrier from a peripheral edge of the semiconductor element A semiconductor device comprising a sealing resin that is injected and filled between the semiconductor element and the semiconductor carrier and at a peripheral end portion of the semiconductor element, wherein the resin of the semiconductor element is formed on the surface of the semiconductor carrier. A semiconductor device characterized in that a protruding portion for blocking the sealing resin is formed on the injection side. 前記突起部は前記半導体素子の前記樹脂注入辺以外の三辺に対向する前記半導体キャリア表面上にも形成されている請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the protrusion is also formed on the surface of the semiconductor carrier facing three sides of the semiconductor element other than the resin injection side. 前記半導体素子の前記樹脂注入辺側の前記突起部と前記樹脂注入辺との間の距離は、前記半導体素子の前記樹脂注入辺以外の三辺とこれに対向する前記突起部との距離よりも大きい請求項２記載の半導体装置。   The distance between the protrusion on the resin injection side of the semiconductor element and the resin injection side is greater than the distance between the three sides of the semiconductor element other than the resin injection side and the protrusion facing the side. 3. The semiconductor device according to claim 2, wherein the semiconductor device is large. 半導体素子の表面電極に突起電極を形成する工程と、前記突起電極が接合される電極を有する絶縁性基板からなる半導体キャリアの周辺端部に線状或いは面状の突起部を形成する工程と、前記半導体素子上の前記突起電極と前記突起電極に対応した前記半導体キャリアの前記電極とを接続する工程と、前記半導体素子と前記半導体キャリアとの間に形成された隙間に前記半導体素子の周辺部の前記突起部側から封止樹脂を注入し、前記封止樹脂を硬化させる工程とを含む半導体装置の製造方法。   Forming a protruding electrode on a surface electrode of a semiconductor element; forming a linear or planar protruding portion on a peripheral edge of a semiconductor carrier made of an insulating substrate having an electrode to which the protruding electrode is bonded; Connecting the protruding electrode on the semiconductor element and the electrode of the semiconductor carrier corresponding to the protruding electrode; and a peripheral portion of the semiconductor element in a gap formed between the semiconductor element and the semiconductor carrier And a step of injecting a sealing resin from the protruding portion side and curing the sealing resin.
JP2003382023A 2003-11-12 2003-11-12 Semiconductor device and its manufacturing method Pending JP2005150179A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009289999A (en) * 2008-05-29 2009-12-10 Renesas Technology Corp Semiconductor device and method for manufacturing it
JP2010050481A (en) * 2009-11-04 2010-03-04 Oki Semiconductor Co Ltd Method of manufacturing semiconductor device
US8541891B2 (en) 2007-03-30 2013-09-24 Lapis Semiconductor Co., Ltd. Semiconductor device
EP3300463A1 (en) * 2016-09-26 2018-03-28 Hitachi Power Semiconductor Device, Ltd. Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8541891B2 (en) 2007-03-30 2013-09-24 Lapis Semiconductor Co., Ltd. Semiconductor device
JP2009289999A (en) * 2008-05-29 2009-12-10 Renesas Technology Corp Semiconductor device and method for manufacturing it
CN103367176B (en) * 2008-05-29 2016-03-16 瑞萨电子株式会社 The manufacture method of semiconductor device
JP2010050481A (en) * 2009-11-04 2010-03-04 Oki Semiconductor Co Ltd Method of manufacturing semiconductor device
EP3300463A1 (en) * 2016-09-26 2018-03-28 Hitachi Power Semiconductor Device, Ltd. Semiconductor device

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