JP2005136060A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a fuse element which is apt to break, even with small current density. <P>SOLUTION: A semiconductor device includes a substrate; a first conductive layer M1 formed on the substrate; a first interlayer insulating film I formed on the layer M1; and a second conductive layer M2 including a first connection hole CH formed in the film I, to reach the upper surface of the first conductive layer, a flat part F1 formed on the first interlayer insulating film, a bent part following the flat part formed on the side face and the bottom face of the first connection hole, and defining a cavity with a shape of reducing its diameter, from the bottom face toward the opening end of the first connection hole. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a fuse element technique used for a trimming circuit or a redundant circuit.

  In the reference voltage generation circuit, slight variations in generated voltage due to manufacturing variations can occur. In many cases, a trimming circuit is formed in a semiconductor integrated circuit in order to adjust a slight variation in generated voltage. In addition, a redundant circuit is used to replace a memory element that has malfunctioned due to the influence of particles or the like with another memory element.

  When a fuse element is used for a trimming circuit or a redundant circuit, trimming processing or the like can be performed after the completion of the semiconductor integrated circuit or in a process in the middle of manufacturing, so that preferable characteristics can be obtained as much as possible or defects can be avoided. It becomes possible.

  Patent Document 1 discloses a first technique for filling a fuse material into a through hole formed between a lower layer wiring and an upper layer wiring as shown in FIG.

In the fuse element shown in FIG. 26, a first interlayer insulating film 203 is formed on a single crystal silicon substrate 200, and a first metal wiring layer 205 is formed thereon. A second interlayer insulating film 207 is formed to cover the first metal wiring layer 205.
The second interlayer insulating film 207 is opened in a partial region on the first metal wiring layer 205 to form a through hole CH. A second metal wiring layer 211 is formed on the second interlayer insulating film 207 so as to cover the through hole CH. The first metal wiring layer 205 and the second metal wiring layer 211 are connected through the through hole CH. A protective insulating film 215 that covers the second metal wiring layer 211 and has an opening above the through hole CH is formed. The metal layer filled in the through hole CH constitutes a fuse.

  On the other hand, Patent Document 2 discloses a second technique in which a through hole is formed using a damascene process as shown in FIG. 27 and a fuse material is filled therein.

  As shown in FIG. 27, a recess is formed in the TEOS film 221. A metal layer 223 made of W or Mo is formed in the recess. An interlayer insulating film 225 is formed on the TEOS film 221 so as to cover the metal layer 223. A damascene through hole CH is formed to open the interlayer insulating film 225 on a partial region of the metal layer 223. A metal layer 227 is filled in the through hole CH. A wiring layer 231 is formed on the interlayer insulating film 225 so as to cover the metal layer 227. When a damascene structure having a large upper opening width and a lower opening width is filled with a metal layer, a void 235 is generated in the lower portion depending on conditions. A thin portion is formed in the metal layer 227 in the through hole CH by the void 235 and used as a fuse.

On the other hand, according to recent integrated circuit manufacturing technology, a contact hole or a through hole is formed in an interlayer insulating film deposited on the lower structure, and a tungsten layer, for example, is deposited on the contact hole or the through hole to form a contact hole or a through hole. after embedding, chemical mechanical polishing (C hemical M echanical P olishing: CMP) is often used technique to planarize the surface by using a. By making the upper surface of the interlayer insulating film and the upper surface of the connection plug embedded in the contact hole or through hole substantially flush with each other, a substantially flat wiring can be formed on the contact hole or through hole. This technique is suitable for increasing the number of wirings, and is becoming an indispensable technique for high integration of integrated circuits.

JP-A-6-5707 Japanese Patent Laid-Open No. 13-024063

  In the fuse element using the first technique shown in FIG. 26, since the metal material for the fuse is filled in the entire contact hole, the fuse cannot be cut unless the current value is considerably increased.

  When the second technique shown in FIG. 27 is used, in order to form a void in the contact hole, the inner diameter of the contact hole needs to be less than 0.2 μm. Therefore, state-of-the-art processing technology is required. In addition, since the condition range in which voids can be formed is limited, there is a problem that it is difficult to control manufacturing process conditions.

  An object of the present invention is to form a fuse element that can be cut at a low current density by a relatively simple process.

  According to one aspect of the present invention, a substrate, a conductive layer formed in or on the substrate, an interlayer insulating film formed on the substrate so as to cover the conductive layer, and the interlayer insulating film A connection hole reaching the upper surface of the conductive layer, a flat portion formed on the interlayer insulating film, and a bent portion following the flat portion, on the side surface and the bottom surface of the connection hole. There is provided a semiconductor device including a wiring layer having a function of a fuse including a bent portion that defines a hollow portion that is formed and has a shape whose diameter is reduced toward the opening direction of the connection hole.

  According to the semiconductor device described above, a fuse structure that can cut the connection portion in the vicinity of the bottom surface of the connection hole can be formed by passing a current of a predetermined current value or more between the conductive layer and the flat portion. Since it has a hollow portion whose shape is reduced in diameter toward the upper end portion, fragments of the connecting portion after cutting are unlikely to jump out of the cavity.

  According to another aspect of the present invention, a substrate, a first conductive layer and a second conductive layer formed in or above the substrate, and the first conductive layer and the second conductive layer are covered. An interlayer insulating film formed on the substrate; a first connection hole formed in the interlayer insulating film reaching the upper surface of the first conductive layer; and an interlayer insulating film formed in the interlayer insulating film. A second connection hole reaching the upper surface, the second connection hole having a smaller aspect ratio than the first connection hole, a flat portion formed on the interlayer insulating film, and a bent portion following the flat portion. A wiring having a function of a fuse including a bent portion formed on a side surface and a bottom surface of the first connection hole and having a hollow portion having a diameter reduced toward an opening direction of the first connection hole. A semiconductor device comprising a layer is provided.

  According to the semiconductor device, the fuse structure and the connection structure of the upper and lower conductive layers can be formed on the same level.

  According to still another aspect of the present invention, (a) a step of forming a conductive layer in or above the substrate, and (b) a step of covering the conductive layer and forming an interlayer insulating film on the substrate; (C) a step of forming a connection hole having an aspect ratio of 1 or more reaching the upper surface of the conductive layer in the interlayer insulating film; and (d) a metal wiring material on the interlayer insulating film including the connection hole. A bend is formed in the connection hole so as to delimit a cavity having a shape that is reduced in diameter toward the opening direction of the connection hole, and has a bent portion having an opening in the upper portion, and is formed on the interlayer insulating film following the bent portion. And a step of forming a wiring layer having a function of a fuse including a flat portion.

  According to still another aspect of the present invention, (a) a step of forming a first conductive layer and a second conductive layer in or above the substrate, and (b) the first conductive layer and the second conductive layer, Forming an interlayer insulating film on the substrate so as to cover the substrate; and (c) a first connection hole reaching the upper surface of the first conductive layer in the interlayer insulating film, and a second reaching the upper surface of the second conductive layer. Forming a second connection hole having a smaller aspect ratio than the first connection hole; and (d) a metal wiring on the interlayer insulating film including the first connection hole and the second connection hole. A material is deposited, and a cavity portion having a shape that is reduced in diameter toward the opening direction of the first connection hole is defined in the first connection hole, and a bent portion having an opening in the upper portion, and the bent portion following the bent portion, And a step of forming a wiring layer having a function of a fuse including a flat portion formed on the interlayer insulating film. The method of manufacturing a semiconductor device is provided.

  According to the present invention, it is possible to form a fuse element that can be easily cut even at a small current density at a bent portion formed in the inner wall of the connection hole. Consistency with the manufacturing process of a normal multilayer wiring structure is also improved. Furthermore, if a hollow portion is formed in the bent portion, a metal mass generated when the fuse is cut can be received, and scattering from the fuse structure to the outside can be prevented.

  In the present specification, the term “connection hole” is used as a concept including a contact hole exposing the upper surface of the semiconductor layer and a via hole exposing the upper surface of the wiring layer. Further, the terms “conductive layer” and “conductive” are used as a concept including a conductive semiconductor layer and a metal wiring layer.

Terms used in this specification will be described with reference to FIG. An interlayer insulating film I is formed on the first metal layer (conductive layer) M1. A connection hole CH reaching the upper surface of the first metal layer M1 is formed in the interlayer insulating film I. When the diameter of the connection hole CH is W and the height is H, the aspect ratio is represented by H / W. Next, consider a case where the second metal layer M2 is deposited in a region covering the inner wall of the connection hole CH. A portion where the second metal layer M2 is deposited on the flat upper surface of the interlayer insulating film I is referred to as a flat portion. A portion where the second metal layer is deposited in the connection hole is referred to as a bent portion. In general, the second metal layer in the bent portion is thinner than the second metal layer in the flat portion. When the thickness of the second metal layer in the flat portion is t _A and the thickness of the second metal layer M2 (connection portion) in the predetermined region of the bent portion is t _B , the coverage (coverage) of the second metal layer in the predetermined region Can be expressed as t _B / t _A.

  The inventor paid attention to the relationship between the shape of the connection hole CH formed between the upper and lower wirings (for example, M1 and M2) and the coverage of the metal layer on the inner wall of the connection hole CH of the fuse material.

  The electrical connection between the upper and lower wirings can be cut even with a small current density as the coverage of the metal layer in the connection hole CH is poor. If the metal layer forming the bent portion in the connection hole CH is used as a fuse, the connection between the upper and lower metal layers can be used as a fuse element that can be electrically disconnected.

  FIG. 1B is a cross-sectional view showing a state in which the second metal layer M2 is deposited in the connection hole CH and a bent portion is formed. As shown in FIG. 1B, the second metal layer M2 is deposited in a region including the connection hole CH having a large aspect ratio. First, a thin barrier metal BM is deposited. The barrier metal BM is deposited conformally on the inner wall F2 and the bottom surface F3 of the connection hole CH. Further, when the second metal layer M2 is continuously deposited, the thickness of the second metal layer M2 deposited on the inner wall F2 of the connection hole CH is thinner than the thickness of the second metal layer M2 deposited on the flat portion F1. Become.

  In the vicinity of the upper end of the connection hole CH (indicated by the points P1 and P1 ′ in FIG. 1B), at the side end of the second metal layer M2 (in FIG. 1B, the points P2 and P2 ′ Approached). The amount of the metal layer that enters the connection hole CH is further reduced. A hollow portion having a diameter reduced toward the upper portion as shown by a solid line in FIG. 1B is formed inside the bent portion formed by the metal layer ML deposited in the connection hole CH. In a portion having a wide cavity, the thickness of the second metal layer M2 attached to the inner wall of the connection hole CH is thin. When a current of a predetermined value or more is passed between the upper and lower metal layers, the electrical connection between the upper and lower metal layers M1 and M2 is cut at the thin portion. On the bottom portion F3 of the connection hole CH, the thickness of the second metal layer M2 is slightly increased near the center thereof.

  Incidentally, the second metal layer M2 may be closed as shown by a one-dot chain line in the drawing at substantially the same height as the upper end portions P1 and P1 ′ of the interlayer insulating film I, or the upper side as shown by a solid line. It may have an opening without being completely closed. In the state of FIG. 1B, when the opening is not closed, the opening can be closed by depositing an insulating film thereon. In any case, if an insulating film is deposited from the state of FIG. 1B, a closed cavity is formed in the connection hole CH. The hollow portion can accommodate the scattered matter that is scattered when the fuse is cut. Therefore, it is possible to prevent the scattered matter from staying in the cavity and scattering outside the cavity.

  Based on the above consideration, the semiconductor technology according to the first embodiment of the present invention will be described with reference to FIG. 2 (A) to FIG. 11 (B).

  As shown in FIG. 2A, a p-type silicon substrate 1 is prepared. A p-type well 3 is formed in the p-type silicon substrate 1 by using, for example, an annealing method for ion implantation and activation.

  As shown in FIG. 2A ', when a CMOS is formed, a p-type well 3p and an n-type well 3n are formed. For n-type well 3n, the conductivity type in the following steps is reversed. In order to separate the processes for the p-type well 3p and the n-type well 3n, a mask such as a resist is used.

  As shown in FIG. 2B, a thermal oxide film 5 is formed on the surface of the p-type silicon substrate 1 by, for example, a thermal oxidation method. Next, a silicon nitride film is formed by a CVD method, and the silicon nitride film is left in a region where an element region is to be formed later. Using the silicon nitride film as a mask, an element isolation film 7 shown in FIG. 3C is formed by using a local oxidation method (LOCOS). In FIG. 3C, the first element region 2a is formed on the left side and the second element region 2b is formed on the right side. The silicon nitride film used as the mask is removed.

As shown in FIG. 3D, a polycrystalline silicon film 8 and a metal film 10 made of, for example, tungsten are formed on the surface of the substrate 1 by using a CVD method, a sputtering method, or the like. Next, a photoresist pattern is formed on the metal film 10, and the metal film 10 and the polycrystalline silicon layer 8 are dry-etched. In this way, as shown in FIG. 4E, the first and second element regions 2a and 2b have the laminated structures of the polycrystalline silicon layers 8a and 8b and the metal layers 10a and 10b, respectively. A first gate electrode G1 and a second gate electrode G2 are formed. Forming an LDD (L ightly D oped D rain ) shallow n-type impurity layer 11a and 11b of one for the first gate electrode G1 and a second gate electrode G2 as a mask.

  As shown in FIG. 4F, after silicon oxide is deposited on the substrate, the silicon oxide layer is anisotropically etched. Side spacer films 12a and 12b are formed by leaving silicon oxide on the side walls of the first gate electrode G1 and the second gate electrode G2. Ion implantation for forming source / drain regions is performed by ion implantation using the gate electrodes G1 and G2 including the side spacer films 12a and 12b as a mask. By performing heat treatment for activation, the impurities are activated to form LDD regions 11a and 11b and source / drain regions 14a / 14b.

  As shown in FIGS. 5G and 5H, after forming an insulating film 15 such as a CVD oxide film on the substrate, the surface is flattened by a known flattening technique, for example, a coated insulating film by SOG or the like. Then, the first interlayer insulating film 18 having a substantially flat upper surface is formed by etching back. Or you may planarize by CMP.

  As shown in FIG. 6I, a resist mask R1 having an opening pattern AR1 is formed on the source / drain regions 14a and 14b, for example, by a photolithography technique using a photoresist.

  Using the resist mask R1 as a mask, first connection holes 19a and 19a 'and second connection holes 19b and 19b' exposing the source / drain regions in the first element region 2a and the second element region 2b are formed. The resist mask R1 is removed.

  A plug material layer (for example, a W film) for forming a connection plug is deposited on the first interlayer insulating film 18. In a state where the first connection holes 19a, 19a ′ and the second connection holes 19b, 19b ′ are filled, the plug material layer formed on the upper surface of the first interlayer insulating film 18 is selected by, for example, CMP. Thus, conductive connection plugs 20a, 20a ′, 20b, and 20b ′ are formed in the connection holes.

  As shown in FIG. 6J, a connection wiring layer 20a, 20a ′ on the first interlayer insulating film 18 is formed by forming a metal layer for the first wiring such as Al and performing patterning using photolithography. And the first conductive layer 21a and the second conductive layer 21b are left on the region including 20b and 20b ′.

As shown in FIG. 7K, a second interlayer insulating film 22 is formed on the first interlayer insulating film 18 so as to cover the first conductive layer 21a and the second conductive layer 21b by CVD or the like. The second interlayer insulating film 22 is formed of, for example, silicon oxide. As shown in FIG. 7L, a resist mask R12 having an opening AR2 is formed on the first conductive layer 21a formed on the first element region 2a. The resist mask R12 is anisotropically etched by a second interlayer insulating film 22 as a mask for example RIE (R eactive I on E tching ) method to form a third contact hole 25a to expose the upper surface of the first conductive layer 21a. The resist mask R12 is removed. A connection hole having an inner wall substantially perpendicular to the upper surface of the first conductive layer 21a is formed. The aspect ratio of the third connection hole 25a is about 1 to 3, for example, about 1.5.

  As shown in FIG. 8M, a resist mask R13 is formed on the second interlayer insulating film 22 so as to cover the third connection holes 25a. The resist mask R13 has an opening AR3 on the second conductive layer 21b formed on the second element region 2b. The second interlayer insulating film 22 is etched by an isotropic etching method, for example, a wet etching method, to approximately half the thickness of the second interlayer insulating film 22. By using an isotropic etching method, as shown in FIG. 8M, a hole 27a having a spherical etched surface is formed. After that, by using an anisotropic etching method, a hole 27b that is continuous with the hole 27a and exposes the upper surface of the second conductive layer 21b is formed. The resist mask R13 is removed.

  As shown in FIG. 8N, the third connection hole 25a formed on the first conductive layer 21a on the first element region 2a has a shape in which the inner wall thereof is almost upright, and the aspect ratio Is also expensive. On the other hand, on the second conductive layer 21b on the second element region 2b, a connecting hole 27 (27a) is formed by a hole 27b having an inner wall whose shape is almost upright and a hole 27a whose inner wall is gently inclined. 27b) is formed.

  As shown in FIG. 9O, a metal wiring layer including a barrier metal layer 31, a metal layer 33, and an antireflection film 34 is formed on a region including the connection hole 25a. The barrier metal layer 31 is a layer including, for example, a TiN layer, a TiON layer, or a Ti layer, and is formed by a sputtering method or a CVD method. When these materials are used, the contact resistance with the first conductive layer is lowered, the long-term reliability of the metal wiring is improved, and the adhesion with the interlayer insulating film (silicon oxide layer) on the inner wall of the connection hole is also improved. . For example, a Ti layer is deposited to a thickness between 5 nm and 50 nm, preferably about 20 nm. Next, a TiN layer having a thickness of, for example, 50 nm to 200 nm, preferably 100 nm is formed on the Ti layer.

  As the metal wiring layer 33, for example, an Al alloy layer such as an Al layer or Al—Si—Cu is deposited by a sputtering method. The thickness of the metal wiring layer 33 is not less than half of the hole diameter, and is, for example, 100 nm to 1000 nm, preferably 500 nm. As an example of the film forming conditions at this time, the substrate temperature is 200 ° C., the Ar flow rate is 33 SCCM, the gas pressure is 2 mTorr (about 0.27 Pa), and the sputtering power is 9 kW.

  For example, when the aspect ratio of the third connection hole 25a is in the range of about 0.8 to 1.5, the coverage of the TiN layer is about 30% to 40%. On the other hand, the coverage of the Al layer is about 0 to 10%. Accordingly, the coverage of the entire wiring is about 20%. Since the aspect ratio of the third connection hole 25a is high, when the metal wiring layer 33 is deposited to a predetermined thickness or more, the upper portions of the metal wiring layer 33 are close to each other on the third connection hole 25a. A flat portion is formed on the second interlayer insulating film 22 in the vicinity of the third connection hole 25a. Along with the formation of the metal wiring layer 33, a bent portion having a hollow portion whose diameter is reduced upward is defined in the third connection hole 25 a following the flat portion. Note that, as indicated by the alternate long and short dash line, the upper portion of the metal wiring layer 33 may be closed in the vicinity of the upper end portion of the second interlayer insulating film 22. In this case, as shown in FIG. 9 (O), the opening is closed at a position in the horizontal direction substantially equal to the upper surface of the second interlayer insulating film 22.

  As shown in FIG. 9P, a photoresist mask R14 is formed above the connection hole. The metal wiring layer 33 and the barrier metal layer 31 are processed by etching using the resist mask as an etching mask. Thereafter, the photoresist mask R14 is removed.

  As shown in FIG. 10Q, the third conductive layer L1 is formed on the first element region 2a, and the fourth conductive layer L2 is formed on the second element region 2b. The third conductive layer L1 includes a part 33a of the metal wiring layer 33, and the fourth conductive layer L2 includes a part 33b of the metal wiring layer 33. A third interlayer insulating film 37 is formed of, for example, a silicon oxide film so as to cover the third conductive layer L1 and the fourth conductive layer L2. The third interlayer insulating film 37 is formed of, for example, a silicon oxide layer having a thickness of 150 nm and a silicon nitride layer or a silicon oxynitride layer having a thickness of 1000 nm sequentially from the substrate side. These films are formed by, for example, a plasma CVD method. The third interlayer insulating film 37 is unlikely to enter the third connection hole 25a where the upper portions of the metal wiring layer 33a are close to each other. A closed cavity 38 is defined in the third connection hole 25 a by the metal wiring layer 33 a and the lower surface of the third interlayer insulating film 37.

  On the other hand, in the connection holes 27 (27a, 27b) having a lower aspect ratio than the third connection holes 25a and easily entering the metal layer, the coverage of the metal layer on the inner wall is better than that of the third connection holes 25a. That is, the inner wall of the connection hole 27 is covered with the metal wiring layer 33b having a sufficient thickness.

  FIG. 10 (R) is a plan view corresponding to FIG. 10 (Q), while FIG. 10 (Q) is a cross-sectional view taken along the line Q-Q ′ of FIG. 10 (R). As shown in FIGS. 10Q and 10R, a fuse element having a fuse formed in the connection hole 25a is formed between the first conductive layer 21a and the third conductive layer L1. A normal two-layer wiring structure connected through the connection hole 27 is formed between the second conductive layer 21b and the fourth conductive layer L2.

  In the fuse structure formed in the first element region 2a shown in FIG. 11A, a current of a predetermined current value or more is passed between the first conductive layer 21a and the third conductive layer L1. As shown in FIG. 11 (B), since the resistance of the portion of the bent portion with poor coverage in the connection hole is high, the heat generated in this portion is increased, and the first portion is cut by selectively generating heat or melting. There is no conduction between the conductive layer 21a and the third conductive layer L1. At this time, the metal piece (metal reservoir) 39 scattered by sublimation or explosion remains in the hollow portion 38 forming a closed space in the bent portion, for example, sublimation occurs and scatters out of the third connection hole 25a. Can be prevented.

  As described above, when the semiconductor technology according to the first embodiment is used, a connection hole having a substantially different aspect ratio is formed on the same substrate, and a metal layer is formed on the inner wall of the connection hole. Elements and normal wiring can be created with good controllability. When the fuse element is formed in the connection hole, if the cavity is formed in the connection hole, the metal reservoir generated when the fuse element is cut can be retained in the cavity, and the outside The metal pool can be prevented from scattering.

  Next, a semiconductor manufacturing technique according to a modification of the first embodiment of the present invention will be described with reference to FIGS. 12 (A) to 14 (E). 12A to 14E are cross-sectional views for explaining a manufacturing process of a semiconductor device according to a modification, and FIG. 12A corresponds to FIG. 7L. . Note that the same components as those of the semiconductor device according to the first embodiment are denoted by the same reference numerals and the details thereof are omitted.

  As shown in FIG. 12A, the first conductive layer 21a and the second conductive layer 21b are covered and, for example, a first silicon oxide film 22-1, a first interlayer insulating film are sequentially formed from the substrate side. The silicon nitride film 22-2, the second silicon oxide film 22-3, and the second silicon nitride film 22-4 are formed. A photoresist mask R12 'having an opening AR2' and an opening AR3'-1 is formed on the first conductive layer 21a and the second conductive layer 21b, respectively. The opening AR3'-1 has a larger opening diameter than the opening AR2 '.

  Using the photoresist mask R12 ', the second silicon nitride film 22-4, the second silicon oxide film 22-3, and the first silicon nitride film 22-2 are etched in order from the top. Openings reaching the upper surface of the first silicon oxide film 22-1 are formed adjacent to the first element region 2a and the second element region 2b, respectively. At this time, the first silicon nitride film 22-2 functions as an etching stopper film. The etching stopper film is selectively removed with respect to the first silicon oxide film 22-1. The photoresist mask R12 'is removed.

  As shown in FIG. 12B, the first element region 2a and the first conductive layer 21a are not covered with the photoresist R13 ′, but the second element region 2b is covered and the opening AR3 included in the opening AR3′-1. '-2 is formed. The silicon oxide film 22-1 on the first and second conductive layers 21a and 21b is anisotropically etched.

  As shown in FIG. 13C, the second silicon nitride film 22-4 to the first silicon oxide film 22-1 are opened in order from the top in the first element region 2a, and the first conductive layer 21a is formed. A third connection hole 25 is formed to reach. In the second element region 2b, the second silicon nitride film 22-4 and the first silicon nitride film 22-2 are opened in order from the top, and a connection hole 27c larger in diameter than the third connection hole 25, A fourth connection hole 27 is formed including the connection hole 27d that opens the first silicon oxide film 22-1 and reaches the second conductive layer 21b.

  As shown in FIG. 14D, a barrier metal layer 31 ′ and a metal wiring layer 33 ′ are deposited on the substrate so as to cover the connection holes 25 and 27. Since the aspect ratio of the third connection hole 25 is higher than that of the fourth connection hole 27, the coverage of the metal wiring layer 33 'is deteriorated. After that, when the Al is reflowed by heating in the reflow chamber without breaking the vacuum, the fourth connection hole 27 is filled with Al.

  As shown in FIG. 14E, the barrier metal layer 31 ′ and the metal wiring layer 33 ′ are processed, and the third conductive layer L1 is formed on the first element region 2a, and the fourth element is formed on the second element region 2b. A conductive layer L2 is formed. Similar to the semiconductor device according to the first embodiment, the aspect ratio of the third connection hole 25 is high. Therefore, the coverage of the third conductive layer L1 (bent portion), particularly the metal wiring layer 33a ', on the inner wall of the third connection hole 25 is poor. When the metal wiring layer 33 is deposited to a predetermined thickness or more, the upper side portions of the metal wiring layer 33 a ′ are close to each other on the third connection hole 25.

  The third interlayer insulating film 37 'is formed of a silicon oxide film deposited using, for example, a CVD method. A silicon oxide film is difficult to enter into the third connection hole 25, and a cavity 38 ′ is formed in a bent portion formed in the third connection hole 25.

  A fuse element for connecting the first conductive layer 21a and the third conductive layer L1 is formed in the first element region 2a. In the second element region 2b, the second conductive layer 21b and the fourth conductive layer L2 are electrically connected through the fourth connection hole 27 in the same manner as in the normal multilayer wiring technique.

  According to the semiconductor technology according to this modification, connection holes with high controllability and high aspect ratios and connection holes with relatively low aspect ratios can be formed on the same substrate using anisotropic etching.

  Next, a semiconductor manufacturing technique according to the second embodiment of the present invention will be described with reference to FIGS. 15 (A) to 16 (D). The first interlayer shown in FIG. 6 (I) is performed by performing the same steps as those shown in FIGS. 2 (A) to 6 (I) referred to in the description of the semiconductor manufacturing technique according to the first embodiment. An insulating film 18 is formed. In FIGS. 15A to 16D, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 15A, the connection hole 20a 'formed on the first element region 2a has a shape in which the inner wall is almost upright, and has a high aspect ratio. On the other hand, another connection hole 20a formed on the first element region 2a and connection holes 20b and 20b 'formed on the second element region 2b have a lower portion having a shape in which the inner wall is substantially upright. The upper part of the inner wall is gently inclined. The connection holes 20a, 20a ', 20b and 20b' can be formed by a method similar to the method of forming the connection holes 25a and 27 shown in FIG.

In this state, the substrate is subjected to heat treatment for reflow. In order to perform reflow, it is preferable that the interlayer insulating film 18 is formed of PSG or BPSG, or a laminate of a BPSG film and a PSG film. The film formation can be performed by atmospheric pressure CVD using SiH ₄ as a Si raw material, or O ₃ -TEOS-CVD method using TEOS as a Si raw material.

In atmospheric pressure CVD using SiH ₄ as a raw material, for example, PH ₃ / B ₂ H ₆ / SiH ₄ = 2.0 / 1.8 / 0.6 [l / min], carrier O ₂ gas 3 [l / min] min] at a flow rate and temperature of 450 ° C. In the O ₃ -TEOS-CVD method, for example, a bubbler using TMPO (Tri Methyl Phosphate: PO (OCH ₃ ) ₃ ), TMB (B (OCH ₃ ) ₃ ), or TEB (B (OC ₂ H ₅ ) ₃ ) is used. TEOS / TMPO / TEB = 3.0 slm / 2.0 slm / 1.5 slm, carrier N ₂ gas 18.0 slm / O ₂ gas 7.5 slm, O ₃ concentration of about 85 g / Nm ³ , temperature 400 ° C. Select a condition.

The film thickness is 500 to 1000 nm, preferably 600 to 800 nm (PSG: 100 nm + BPSG: 650 nm). PSG is 3～8Mol% of P and _P 2 _{O 5} as source preferably include 5 mol%. BPSG contains P ₂ O ₅ as a source and P in an amount of 4 to 8 mol%, preferably 5.5 mol%, and B ₂ O ₃ as a source, and B is included in an amount of 8 to 10 mol%, preferably 8.5 mol%.

  As heat treatment conditions for reflow, for example, the temperature is 900 to 1100 ° C. for PSG and 800 to 1000 ° C. for BPSG. Furnace annealing is performed for about 10 to 30 minutes, and RTA is performed for about 10 to 60 seconds.

  By this heat treatment, the first interlayer insulating film 22 flows. The connection hole 20a 'has an inner wall substantially upright with respect to the substrate surface that has not been subjected to round etching. Therefore, even if heat treatment is performed, the shape thereof hardly changes and a high aspect ratio is maintained. On the other hand, the other connection holes 20a, 20b and 20b 'are round-etched at the top. Therefore, when the heat treatment is performed under the condition that the first interlayer insulating film 18 flows, the connection holes 20a, 20b, and 20b 'change to a shape having a tapered surface whose diameter gradually increases upward. This state is shown in FIG.

  Processes up to the state shown in FIG. A barrier metal layer, a metal wiring layer, and an antireflection film are deposited on the first interlayer insulating film 18 so as to cover the connection holes 20a, 20a ', 20b, and 20b'. By patterning this stacked layer, wirings 21 a, 21 a ′, 21 b and 21 b ′ are left on the first interlayer insulating film 18. The wirings 21a, 21a ', 21b, and 21b' are electrically connected to the impurity diffusion regions exposed on the bottom surfaces thereof through the connection holes 20a, 20a ', 20b, and 20b', respectively. In FIG. 16C, the three-layer structure of these wirings is not clearly shown, but actually has the above-described three-layer structure. Since the aspect ratio of the connection hole 20a 'is higher than that of the other connection holes, the coverage of the wiring 21a' is worse than that of the other wirings 21a, 21b, and 21b '. As a result, the wiring 21a 'functions as a fuse element.

  Processes up to the state shown in FIG. A second interlayer insulating film 22 made of silicon oxide is formed on the first interlayer insulating film 18 using a CVD method. Connection holes 25 c and 27 c are formed in the second interlayer insulating film 22. The method for forming the connection holes 25c and 27c is the same as the method for forming the connection hole 27 shown in FIG. For this reason, the upper end portions of the inner peripheral surfaces of the connection holes 25c and 27c have a shape that expands upward, and the lower end portion has a substantially upright shape. Wirings L1 and L2 and a third interlayer insulating film 37 are formed by a process similar to the process of FIGS. 9O to 10Q. The wiring L1 is connected to the lower layer wiring 21a 'via the connection hole 25c, and the wiring L2 is connected to the lower layer wiring 21b' via the connection hole 27c.

  The MOSFET formed in the first element region 2a and the upper layer wiring L1 are connected by a wiring 21a 'functioning as a fuse element. The MOSFET formed in the second element region 2b is connected to the upper layer wiring L2 by a normal wiring 21b '.

  Next, a semiconductor technology according to the third embodiment of the present invention will be described with reference to FIGS. 17 (A) to 18 (D). FIG. 17A is a diagram showing a state in which a resist is patterned after FIG. 7K in the first embodiment. The process leading to FIG. 17A is similar to the semiconductor manufacturing technique according to the first embodiment, and the description of the process up to that step is omitted. Further, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 17A, the resist mask R21 has a first opening AR21 on the first conductive layer 21a on the first element region 2a and on the second conductive layer 21b on the second element region 2b. Has a second opening AR22. The diameter of the first opening AR21 is 0.9 times or less, preferably 0.7 times or less, compared to the diameter of the normal second opening AR22.

The second interlayer insulating film 22 is anisotropically etched using the resist mask R21.
As shown in FIG. 17B, the third connection hole 55a reaching the upper surface of the first conductive layer 21a on the first element region 2a and the upper surface of the second conductive layer 21b on the second element region 2b are reached. A fourth connection hole 57a is formed. The third connection hole 55a preferably has an aspect ratio of 1 or less.

  A barrier metal layer and a metal wiring layer are deposited on the substrate so as to cover the third connection hole 55a and the fourth connection hole 57a. Since the aspect ratio of the third connection hole 55a is higher than that of the fourth connection hole 57a, the coverage of the metal wiring layer is deteriorated.

  As shown in FIG. 18C, the barrier metal layer and the metal wiring layer are processed so that the third conductive layer L1 is formed on the first element region 2a and the fourth conductive layer L2 is formed on the second element region 2b. Form. Similar to the semiconductor device according to the first embodiment, the aspect ratio of the third connection hole 55a is large. Therefore, the coverage of the third conductive layer L1 (bent portion), particularly the metal wiring layer 63a, on the inner wall of the third connection hole 55a is poor. When the metal wiring layer 63a is deposited to a predetermined thickness or more, the upper portions of the metal wiring layer 63a come close to each other on the third connection hole 55a. Since the fourth connection hole 57a has a tapered shape whose diameter increases toward the top, the coverage of the metal wiring layer 63b is good.

  As shown in FIG. 18D, the third interlayer insulating film 37 is formed of a silicon oxide film deposited by using, for example, a CVD method. The silicon oxide film is unlikely to enter the third connection hole 55a. A void 68 is formed in the third connection hole 55a.

  A fuse element for connecting the first conductive layer 21a and the third conductive layer L1 is formed in the first element region 2a. In the second element region 2b, the second conductive layer 21b and the fourth conductive layer L2 are electrically connected through the fourth connection hole 57a in the same manner as in the normal multilayer wiring technique.

  The aspect ratio of the third connection hole 55a is in the range of about 0.8 to 1.5. The coverage of the TiN layer is about 30 to 40%. On the other hand, the coverage of the Al layer (metal wiring layer) is about 0 to 10%. Accordingly, the coverage of the entire wiring is about 20%. On the other hand, the coverage of the TiN layer and the Al layer (metal wiring layer) in the fourth connection hole 57a is as good as a normal connection hole because the diameter of the inner wall of the connection hole is large.

  According to the semiconductor technology according to the present embodiment, it is possible to form a fuse element and a normal multilayer wiring structure on the same substrate only by forming connection holes having different inner diameters. The manufacturing process is simple, and the manufacturing cost and yield are improved.

  Next, semiconductor technology according to the fourth embodiment of the present invention will be described with reference to FIGS. 19A to 24J. In the semiconductor manufacturing technique according to the present embodiment, a fuse structure and a normal multilayer wiring structure are separately formed depending on the size of the step difference of the base.

  As shown in FIG. 19A, a p-type silicon substrate 101 is prepared. A p-type well 103 is formed on the p-type silicon substrate 101 by using, for example, an annealing method for ion implantation and activation. As shown in FIG. 19A ', when a CMOS is formed, a p-type well 103p and an n-type well 103n are formed. For n-type well 103n, the conductivity type in the following process is reversed. In order to separate the processes for the p-type well 103p and the n-type well 103n, a mask such as a resist is used. As shown in FIG. 19B, a thermal oxide film 105 is formed on the surface of the p-type silicon substrate 101 by, eg, thermal oxidation. Next, a silicon nitride film is formed, and the silicon nitride film is left in a region where an element region is to be formed later. Using the silicon nitride film as a mask, an element isolation film 107 shown in FIG. 20C is formed by local oxidation (LOCOS). In the figure, a first element region 102a is formed on the left side and a second element region 102b is formed on the right side.

  A polycrystalline silicon film and a metal film made of, for example, tungsten are formed on the surface of the substrate 101. As shown in FIG. 20D, on the element isolation film 107 on both sides of the first element region 102a, a first stacked structure SS1 and a second stacked structure SS1 and second layers of polycrystalline silicon layers 108b and 108c and metal layers 110b and 110c, respectively. A stacked structure SS2 is formed. A gate electrode G3 is formed in the second element region 102b by the polycrystalline silicon layer 108a and the metal layer 110a.

  As shown in FIG. 21E, an LDD region 111 and source / drain regions 114a / 114b are formed in the second element region 102b using the gate electrode G3 as a mask.

  As shown in FIG. 22F, a first interlayer insulating film 115 is formed by BPSG / PSG with good reflow, and openings reaching the source region 114a and the drain region 114b are formed. Source / drain electrodes 117a / 117b in contact with the source / drain regions 114a / 114b are formed in the openings. As shown in FIG. 23G, a large recess 120 is formed in the first element region 102a between the left and right element isolation regions due to the influence of the element isolation region 107 and the stacked structures SS1 and SS2 thereon. On the other hand, no particularly large unevenness is formed in the second element region 102b. A metal layer for the first wiring is formed, and a first conductive layer 121 and a second conductive layer 123 are formed on the first element region 102 a on the first interlayer insulating film 115. On the upper surface of the first conductive layer 121, a recess 121a having a shape along the recess 120 therebelow is formed. Large irregularities are not formed on the second conductive layer 123.

  As shown in FIG. 23H, a second interlayer insulating film 125 is formed over the first interlayer insulating film 115 so as to cover the first conductive layer 121 and the second conductive layer 123. A resist mask R31 having an opening AR31 on the first conductive layer 121 formed on the first element region 102a and an opening AR32 on the second conductive layer 123 is formed. Using the resist mask R31 as a mask, the second interlayer insulating film 125 is anisotropically etched by, eg, RIE. The resist mask R31 is removed.

  As shown in FIG. 24I, a third connection hole 131a exposing the upper surface of the first conductive layer 121 is formed, and a fourth connection hole 131b exposing the upper surface of the second conductive layer 123 is formed.

  The depth of the recess 121a is d1, and the depth of the fourth connection hole 131b is t1. The diameters of the third connection hole 131a and the fourth connection hole 131b are both L11. The aspect ratio of the third connection hole 131a is (d1 + t1) / L11. The aspect ratio of the fourth connection hole 131b is t1 / L11. Therefore, the aspect ratio of the third connection hole 131a is larger than the aspect ratio of the fourth connection hole 131b by the depth d1 of the recess 121a.

  As shown in FIG. 24J, a barrier metal layer and a conductive layer are deposited on the substrate, and predetermined processing is performed to form a third conductive layer L31 and a fourth conductive layer L32. Further, a third interlayer insulating film 141 is formed on the second interlayer insulating film 125 so as to cover the third and fourth conductive layers L31 and L32, for example, using silicon oxide. The step coverage of the third conductive layer L31 in the third connection hole 131a is worse than the step coverage of the fourth conductive layer L32 (bent portion) in the fourth connection hole 131b.

  The third interlayer insulating film 141 is formed by, for example, a plasma CVD method. The third interlayer insulating film 141 does not easily enter the third connection hole 131a having a high aspect ratio and in which the upper portions of the metal wiring layer L31 are close to each other. A cavity 145 is formed in the third connection hole 131a. This structure functions as a fuse element.

  On the other hand, the fourth connection hole 131b having a lower aspect ratio than that of the third connection hole 131a is covered with a metal wiring layer L32 having a sufficient thickness. This structure works as a normal multilayer wiring structure.

  By using the semiconductor technology described above, it is possible to easily create a fuse element and a normal multilayer wiring structure on the same substrate.

  Next, the cutting current of the fuse element formed using the semiconductor technology according to each of the above embodiments will be considered with reference to FIGS. FIG. 25A is a cross-sectional view showing a schematic structure in which a metal layer with poor coverage is formed in the connection hole, and a void is formed therein. FIG. 25B is a cross-sectional view taken along line B-B ′ of FIG.

  As shown in FIG. 25A, a first interlayer insulating film S1 is formed on the first conductive layer L51. A connection hole CH that reaches the upper surface of the first conductive layer L51 and has a large aspect ratio is formed in the first interlayer insulating film S1. A second conductive layer L61 is formed on the first interlayer insulating film S1 so as to cover the connection hole CH. Since the aspect ratio of the connection hole CH is large, there is a portion with poor coverage in the connection hole CH. A second interlayer insulating film S2 is formed to cover the second conductive layer L61. The second interlayer insulating film S2 is difficult to enter into the connection hole CH, and a hollow portion V having a triangular pyramid shape is formed in the connection hole CH.

  FIG. 25B is a cross-sectional view taken along line B-B ′ of FIG. The inner diameter of the connection hole CH is R, and the distance (diameter) from the center of the connection hole CH to the inner wall of the thinnest portion of the second conductive layer L61 is r.

  Here, when used as a fuse, the current concentrates on the thinnest portion of the second conductive layer L61, the amount of heat generation increases, and it melts and cuts. When the material for the second conductive layer L61 exists in all the spaces in the connection hole CH as in the prior art, the cutting current of the fuse element is Is, while the structure shown in FIGS. 25 (A) and 25 (B) If the cutting current at is Is ′, Is and Is ′ are expressed by the following ratio.

Is: Is ′ = R ² : (R ² −r ² )
In other words, when a transistor having the same drive capability using the same power supply voltage Vdd is used as compared with the conventional structure, the cutting current of the fuse is reduced.

  As mentioned above, although this invention was demonstrated along embodiment, this invention is not restrict | limited to these. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

FIG. 1A is a schematic cross-sectional view showing a structure including a connection hole and a metal layer formed so as to cover the inner wall, and FIG. 1A is a cross-sectional view for defining coverage and an aspect ratio. 1 (B) is a cross-sectional view showing a state in which a metal layer is deposited in a connection hole to form a bent portion. 2A, 2A, and 2B are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the first embodiment of the present invention. 3C and 3D are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the first embodiment of the invention. 4E and 4F are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the first embodiment of the present invention. FIGS. 5G and 5H are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the first embodiment of the invention. 6 (I) and 6 (J) are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the first embodiment of the present invention. 7K and 7L are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the first embodiment of the invention. 8 (M) and 8 (N) are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the first embodiment of the invention. FIG. 9O and FIG. 9P are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the first embodiment of the present invention. FIG. 10Q is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention, and FIG. 10R is a plan view. FIG. 11A is a cross-sectional view showing the structure of the fuse element in the semiconductor device according to the first embodiment of the present invention, and FIG. 11B is a cross-sectional view showing the state when the fuse element is cut. FIG. 12A and 12B are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the modification of the first embodiment of the present invention. FIG. 13C is a cross-sectional view showing the manufacturing process of the semiconductor device according to the modification of the first embodiment of the present invention. 14D and 14E are cross-sectional views showing the manufacturing steps of the semiconductor device according to the modification of the first embodiment of the present invention. 15A and 15B are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the second embodiment of the present invention. 16C and 16D are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the second embodiment of the present invention. 17A and 17B are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the third embodiment of the present invention. 18C and 18D are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the third embodiment of the present invention. 19A, 19A ', and 19B are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the fourth embodiment of the present invention. 20C and 20D are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the fourth embodiment of the present invention. FIG. 21E is a cross-sectional view showing the manufacturing process of the semiconductor device according to the fourth embodiment of the present invention. FIG. 22F is a cross-sectional view showing the manufacturing process for the semiconductor device according to the fourth embodiment of the present invention. 23G and 23H are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the fourth embodiment of the present invention. FIGS. 24I and 24J are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the fourth embodiment of the present invention. FIG. 25A is a cross-sectional view showing a schematic structure of a fuse element including a connection hole and a metal layer covering the connection hole. FIG. 25B is a plan view taken along the line B-B ′ of FIG. It is sectional drawing which shows a general fuse structure. It is sectional drawing which shows another general fuse structure.

Explanation of symbols

1 p-type silicon substrate, 2a first element region, 2b second element region, 3 p-type well, 5 thermal oxide film, 7 element isolation film, 8 polycrystalline silicon film, 10 metal film, G1 first gate electrode, G2 Second gate electrode, 11a, 11b n-type impurity layer for LDD, 12a, 12b side spacer film, 14a source region, 14b drain region, 15 insulating film, 17a source electrode, 17b drain electrode, 18 first interlayer insulating film, R1 Photoresist, 20a 1st connection hole, 20b 2nd connection hole, 21a 1st conductive layer, 21b 2nd conductive layer, 22 2nd interlayer insulation film, 25a 3rd connection hole, 27a 4th connection hole, 27b 5th Connection hole, 31 barrier metal layer, 33 metal layer, L1 third conductive layer, L2 fourth conductive layer, 37 third interlayer insulating film, 38 cavity, 39 gold Pieces (metal reservoir).

Claims (15)

A substrate,
A conductive layer formed in or over the substrate;
A first interlayer insulating film formed on the substrate to cover the conductive layer;
A connection hole formed in the first interlayer insulating film and reaching the upper surface of the conductive layer;
Following the flat portion formed on the first interlayer insulating film, a bend that is formed on the side surface and the bottom surface of the connection hole and defines a cavity portion having a diameter that decreases toward the opening direction of the connection hole. And a fuse layer including the semiconductor device. The semiconductor device according to claim 1, wherein the bent portion defines a bottleneck-shaped opening. The semiconductor device according to claim 2, further comprising a second interlayer insulating film that covers the fuse layer and is formed on the first interlayer insulating film and closes the opening. The fuse layer includes a barrier metal layer covering the connection hole;
4. The semiconductor device according to claim 1, further comprising: a metal wiring layer formed on the barrier metal layer and having an inner wall that defines the shape of the cavity. 5. A substrate,
A conductive layer formed above the substrate and having a convex upper surface;
An interlayer insulating film formed on the substrate to cover the conductive layer;
A connection hole formed in the interlayer insulating film and reaching the upper surface of the conductive layer having a convex upper surface;
A flat portion formed on the interlayer insulating film and a bent portion following the flat portion, formed on the side surface and the bottom surface of the connection hole, and reduced in diameter toward the opening direction of the connection hole. A semiconductor device comprising a fuse layer including a bent portion defining a hollow portion having a shape. A substrate,
A first conductive layer formed in or on the substrate;
A second conductive layer formed in or above the substrate;
An interlayer insulating film formed on the substrate to cover the first conductive layer and the second conductive layer;
A first connection hole formed in the interlayer insulating film and reaching the upper surface of the first conductive layer;
A second connection hole formed in the interlayer insulating film, reaching the upper surface of the second conductive layer, and having an aspect ratio smaller than that of the first connection hole;
Following the flat portion formed on the interlayer insulating film, a hollow portion formed on the side surface and the bottom surface of the first connection hole and having a diameter reduced toward the opening direction of the first connection hole is provided. A semiconductor device including a bent portion and a wiring layer having a function of a fuse. The semiconductor device according to claim 6, further comprising: a wiring layer formed simultaneously with the wiring layer having a function of the fuse and covering the inside of the second connection hole. The second connection hole is formed on the lower connection hole, the lower connection hole having an inner diameter substantially equal to the inner diameter of the first connection hole in order from the upper surface of the second conductive layer. The semiconductor device according to claim 6, further comprising an upper connection hole having a large inner diameter. The semiconductor device according to claim 8, wherein an inner diameter of the upper connection hole has a tapered shape that increases in diameter as the distance from the upper surface of the second conductive layer increases. 8. The semiconductor device according to claim 6, wherein the second connection hole has a tapered shape having a larger diameter as the distance from the upper surface of the second conductive layer increases. The first conductive layer is a conductive layer formed above the substrate and having a convex upper surface underneath,
The semiconductor device according to claim 6, wherein the first connection hole is formed on an upper surface of a conductive layer having a convex upper surface. (A) forming a conductive layer in or above the substrate;
(B) forming a first interlayer insulating film on the substrate so as to cover the conductive layer;
(C) a step of reaching a top surface of the conductive layer in the first interlayer insulating film and forming a connection hole having an aspect ratio of 1 or more;
(D) Depositing a metal wiring material on the first interlayer insulating film including the connection hole, and having a hollow portion having a shape that is reduced in diameter toward the opening direction of the connection hole in the connection hole and opening in the upper part And a step of forming a fuse layer including a bent portion that defines a bent portion and a flat portion formed on the first interlayer insulating film following the bent portion. further,
13. The semiconductor device according to claim 12, further comprising: (e) forming a second interlayer insulating film that covers the fuse layer and closes the opening with the cavity remaining on the first interlayer insulating film. Production method. (A) forming a first conductive layer and a second conductive layer in or above the substrate;
(B) forming an interlayer insulating film on the substrate so as to cover the first conductive layer and the second conductive layer;
(C) a first connection hole reaching the upper surface of the first conductive layer in the interlayer insulating film and a second connection hole reaching the upper surface of the second conductive layer, wherein the aspect ratio is higher than that of the first connection hole. Forming a small second connection hole,
(D) A shape in which a metal wiring material is deposited on the interlayer insulating film including the first connection hole and the second connection hole, and the diameter is reduced in the opening direction of the first connection hole in the first connection hole. And a step of forming a first wiring layer including a bent portion having an opening in the upper portion and a flat portion formed on the interlayer insulating film following the bent portion. Production method. The method of manufacturing a semiconductor device according to claim 14, wherein the step (d) further includes a step of forming a second wiring layer covering the inside of the second connection hole simultaneously with the first wiring layer.

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