JP2005134542A - Substrate for electrooptical device, its manufacturing method and electrooptical device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a substrate for an electrooptical device which can be protected from a flaw, etc., and its manufacturing method, and an electrooptical device. <P>SOLUTION: The substrate for the electrooptical device includes substrate materials 10' and 20", elements formed on the element forming surface side of the substrate materials 10' and 20" and amorphous carbon films 91 formed on the non-element forming surface side of the substrate materials 10' and 20". <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a substrate for an electro-optical device, a method for manufacturing the same, and an electro-optical device that prevent the surface of the substrate from being damaged during the manufacturing process.

  In general, an electro-optical device, for example, a liquid crystal device that performs predetermined display using liquid crystal as an electro-optical material has a configuration in which liquid crystal is sandwiched between a pair of substrates. Among these, in an electro-optical device such as an active matrix driving type liquid crystal device by TFT driving, TFD driving, etc., at each intersection of a large number of scanning lines (gate lines) and data lines (source lines) arranged vertically and horizontally. Correspondingly, a pixel electrode and a switching element are provided on a substrate (active matrix substrate).

  A switching element such as a TFT element is turned on by an on signal supplied to the gate line, and an image signal supplied via the source line is written to the pixel electrode (transparent electrode (ITO)). Thereby, a voltage based on the image signal is applied to the liquid crystal layer between the pixel electrode and the counter electrode to change the arrangement of the liquid crystal molecules. In this way, the transmittance of the pixel is changed, and light passing through the pixel electrode and the liquid crystal layer is changed according to the image signal to perform image display.

  An element substrate constituting such a switching element is configured by laminating a semiconductor thin film, an insulating thin film or a conductive thin film having a predetermined pattern on a glass or quartz substrate. That is, as in the semiconductor device manufacturing process, the TFT substrate and the like are formed by repeating a film forming process of various films and a photolithography process.

As a liquid crystal device having such a laminated structure, there is one described in Patent Document 1.
JP 2002-123192 A

  By the way, in order to carry out each step in the manufacturing process, the substrate is sequentially transported to a stage for each process. However, during this transport, the back surface of the substrate comes into sliding contact with a transport member, a stage, and the like, and there is a problem that the back surface of the substrate is damaged. This flaw remains until the end of the manufacturing process. For example, in a transmissive liquid crystal device, light passes through the back surface of the substrate, and image quality deteriorates due to scratches formed on the back surface of the substrate.

  The present invention has been made in view of such problems, and provides a substrate for an electro-optical device, a manufacturing method thereof, and an electro-optical device that can improve scratch resistance and the like by being coated with an amorphous carbon film. For the purpose.

  An electro-optical device substrate according to the present invention includes a substrate material, an element formed on an element formation surface side of the substrate material, and an amorphous carbon film formed on a non-element formation surface side of the substrate material. It is characterized by that.

  According to such a configuration, the amorphous carbon film is formed on the non-element formation surface side of the substrate material. Amorphous carbon films have a low coefficient of friction and are not easily scratched, and have high density and few pinholes. Furthermore, the amorphous carbon film has high corrosion resistance and is not easily corroded. Thereby, the substrate surface can be protected from scratches and the like.

  The amorphous carbon film is a diamond-like carbon film.

  According to such a configuration, diamond-like carbon has a low friction coefficient, high density, high hardness, and high corrosion resistance, and can protect the substrate surface from scratches and the like.

  The substrate material and the amorphous carbon film are transparent.

  Such a configuration can be used for an electro-optical device or the like that transmits light.

  And a step of forming an element by a high temperature process on the element forming surface side of the substrate material, and a step of forming an amorphous carbon film on the non-element forming surface side of the substrate material after the high temperature process. And

  According to such a configuration, the amorphous carbon film is formed after completion of the high temperature process. Thereby, the amorphous carbon film can remain on the non-element formation surface side of the substrate material after the high temperature process is completed.

  In addition, after the step of forming the amorphous carbon film, there is further provided a step of forming an element by a low temperature process on the element forming surface side of the substrate material.

  According to such a configuration, an amorphous carbon film can be formed at any time after the high temperature process is completed, and an element can be formed by a low temperature process after the amorphous carbon film is formed.

  Further, the electro-optical device substrate and the electro-optical material are used.

  According to such a configuration, the non-element formation surface side of the substrate for the electro-optical device is protected by the amorphous carbon film that is not easily scratched, so that it is possible to prevent image quality deterioration due to the scratch or the like.

  The electro-optical device substrate of the present invention is characterized in that an element is provided on one surface of an insulating transparent substrate, and an amorphous carbon film is provided on the other surface of the one surface.

  Furthermore, an electro-optical device according to the present invention is configured using the electro-optical device substrate.

  According to the above configuration, since the non-element formation surface side of the insulating transparent substrate is protected by the amorphous carbon film which is not easily damaged, an electro-optical substrate having no damage can be formed. Therefore, for example, it has a great effect in preventing image quality deterioration particularly in a transmissive display device and a reflective transflective display device.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a cross-sectional view showing an electro-optical device configured using the electro-optical device substrate according to the first embodiment of the invention. This embodiment is applied to an electro-optical device substrate such as a TFT substrate (element substrate) as an electro-optical device substrate. FIG. 2 is a plan view of a liquid crystal device, which is an electro-optical device configured using the substrate for an electro-optical device according to the present embodiment, as viewed from the counter substrate side together with each component formed thereon. FIG. 1 is a cross-sectional view taken along the line HH ′ of FIG. 2 and shows the liquid crystal device after the assembly process in which liquid crystal is sealed by bonding the element substrate and the counter substrate together. . FIG. 3 is an equivalent circuit diagram of various elements and wirings in a plurality of pixels constituting the pixel region of the liquid crystal device. FIG. 4 is a cross-sectional view showing the pixel structure of the liquid crystal device in detail. FIG. 5 is a plan view showing a main part of the film formation pattern of each layer for a plurality of adjacent pixels formed on the element substrate of the present embodiment. 6 and 7 are process diagrams showing the method of manufacturing the substrate for an electro-optical device according to the present embodiment in the order of steps by cross-sectional views. 8 and 9 are flowcharts showing the method for manufacturing the electro-optical device substrate according to the present embodiment. In each of the above drawings, the scale is different for each layer and each member so that each layer and each member can be recognized in the drawing.

First, an overall configuration of a liquid crystal device, which is an electro-optical device configured using the electro-optical device substrate of the present embodiment, will be described with reference to FIGS. 1 to 3.
As shown in FIGS. 1 and 2, the liquid crystal device includes, for example, an element substrate 10 configured using a substrate material 10 ′ such as a quartz substrate, a glass substrate, a silicon substrate, and the like, and a counter substrate, for example, a glass substrate. Further, the liquid crystal 50 is sealed between the counter substrate 20 formed using a substrate material 20 ′ such as a quartz substrate. The element substrate 10 and the counter substrate 20 that are arranged to face each other are bonded to each other by a sealing material 52.

  On the substrate material 10 ′ of the element substrate 10, pixel electrodes (ITO) 9 a constituting pixels are arranged in a matrix. A counter electrode (ITO) 21 is provided on the entire surface of the substrate material 20 ′ of the counter substrate 20. On the pixel electrode 9 a of the element substrate 10, an alignment film 16 that has been subjected to a rubbing process is provided. On the other hand, an alignment film 22 subjected to a rubbing process is also provided on the counter electrode 21 formed over the entire surface of the counter substrate 20. The alignment films 16 and 22 are made of a transparent organic film such as a polyimide film, for example.

  FIG. 3 shows an equivalent circuit of elements on the element substrate 10 constituting the pixel. As shown in FIG. 3, in the pixel region, a plurality of scanning lines 11a and a plurality of data lines 6a are wired so as to intersect with each other, and a pixel electrode is formed in a region partitioned by the scanning lines 11a and the data lines 6a. 9a are arranged in a matrix. A TFT 30 is provided corresponding to each intersection of the scanning line 11 a and the data line 6 a, and the pixel electrode 9 a is connected to the TFT 30.

  The TFT 30 is turned on by the ON signal of the scanning line 11a, whereby the image signal supplied to the data line 6a is supplied to the pixel electrode 9a. A voltage between the pixel electrode 9 a and the counter electrode 21 provided on the counter substrate 20 is applied to the liquid crystal 50. In addition, a storage capacitor 70 is provided in parallel with the pixel electrode 9a, and the storage capacitor 70 makes it possible to hold the voltage of the pixel electrode 9a for a time that is, for example, three orders of magnitude longer than the time when the source voltage is applied. The storage capacitor 70 improves the voltage holding characteristic and enables image display with a high contrast ratio.

  In the present embodiment, as shown in FIG. 1, the liquid crystal device has a diamond-like carbon (hereinafter also referred to as DLC) on the surface opposite to the element formation surface (hereinafter referred to as a non-element formation surface) such as the TFT 30. An amorphous carbon film 91 such as is formed. The amorphous carbon film 91 has a small coefficient of friction, a high density, is hardly scratched, and does not easily generate pinholes. The amorphous carbon film 91 is also excellent in corrosion resistance.

  In the present embodiment, an example in which the amorphous carbon film 91 is formed only on the back surface of the substrate material 10 ′ of the element substrate 10 is shown, but the counter substrate 20 is also formed on the non-element formation surface of the substrate material 20 ′. An amorphous carbon film may be formed.

(Manufacturing process)
Next, a method of manufacturing the electro-optical device substrate described with reference to FIGS. 1 to 3 will be described with reference to FIGS. FIG. 4 is a schematic cross-sectional view of a liquid crystal device focusing on one pixel, and FIG. 5 is a plan view showing a film formation pattern of each layer. 4 is a cross-sectional view taken along line AA ′ of FIG. 6 and 7 show manufacturing steps in the pixel region in the order of steps. 8 and 9 show the timing of the coating process using the amorphous carbon film during the entire manufacturing process.

  As a method for manufacturing a substrate for an electro-optic device, for example, a film formation and a photolithography process are repeated on a mother substrate material such as a silicon wafer or quartz and glass without dividing each element for a plurality of substrates simultaneously. Adopt array manufacturing to form. In array manufacturing, each substrate formed in an array on a mother substrate material is divided to obtain a substrate for each chip. This embodiment may employ such array manufacturing, or may employ a manufacturing method for each chip.

  In FIG. 5, a plurality of pixel electrodes 9a are provided in a matrix on the substrate material 10 ′ of the element substrate 10, and data lines 6a and scanning lines 11a are provided along the vertical and horizontal boundaries of the pixel electrodes 9a. ing. FIG. 5 shows only a predetermined 2 × 2 pixel area. As will be described later, the data line 6a has a laminated structure including an aluminum film, and the scanning line 11a is made of, for example, a conductive polysilicon film. Further, the scanning line 11a is electrically connected to the gate electrode 3a facing the channel region 1a 'indicated by the hatched region rising to the right in the drawing in the semiconductor layer 1a. That is, the pixel switching TFT 30 is configured by disposing the gate electrode 3a and the channel region 1a 'connected to the scanning line 11a so as to face each other at the intersection of the scanning line 11a and the data line 6a.

  On one surface (element formation surface) of the substrate material 10 ′, various structures including these in addition to the TFT 30 and the pixel electrode 9 a are provided in a laminated structure. As shown in FIG. 4, this stacked structure has a first layer (film formation layer) including the scanning line 11a, a second layer including the TFT 30 including the gate electrode 3a, and a third layer including the storage capacitor 70 in order from the bottom. A fourth layer including the data line 6a, a fifth layer including the shield layer 400, and a sixth layer (uppermost layer) including the pixel electrode 9a and the alignment film 16 and the like. Further, the base insulating film 12 is provided between the first layer and the second layer, the first interlayer insulating film 41 is provided between the second layer and the third layer, and the second interlayer insulating film 42 is provided between the third layer and the fourth layer. A third interlayer insulating film 43 is provided between the fourth layer and the fifth layer, and a fourth interlayer insulating film 44 is provided between the fifth layer and the sixth layer, so that the above-described elements are short-circuited. Is preventing. Further, these various insulating films 12, 41, 42, 43 and 44 are also provided with, for example, a contact hole for electrically connecting the high concentration source region 1d in the semiconductor layer 1a of the TFT 30 and the data line 6a. It has been.

Further, in the present embodiment, an amorphous carbon film 91 is formed on the non-element formation surface opposite to the element formation surface of the substrate material 10 ′.
First, in step S1 of FIG. 8, as shown in step (1) of FIG. 6, a substrate material 10 'such as a quartz substrate, glass, or silicon substrate is prepared. Next, various manufacturing processes are performed on the substrate material 10 'after step S2. For example, first, the substrate material 10 ′ is preferably annealed at a high temperature of about 900 to 1300 ° C. in an inert gas atmosphere such as N (nitrogen), and then the substrate material 10 ′ is subjected to a high-temperature process performed later. Pre-processing is performed so that the generated distortion is reduced.

  Next, a metal alloy film such as a metal such as Ti, Cr, W, Ta, or Mo or a metal silicide is formed on the entire surface of the element formation surface of the substrate material 10 ′ thus processed by sputtering to about 100 to 500 nm. To a thickness of 200 nm, preferably 200 nm. Then, the metal alloy film is patterned by photolithography and etching to form scanning lines 11a having a stripe shape in plan view.

  Next, on the scanning line 11a, for example, TEOS (tetra-ethyl ortho-silicate) gas, TEB (tetra-ethyl boat rate) gas, TMOP (tetra-methyl oxy. A silicate glass film such as NSG (non-silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron phosphorus silicate glass), silicon nitride film, silicon oxide film, etc. A base insulating film 12 made of or the like is formed. The thickness of the base insulating film 12 is, for example, about 500 to 2000 nm.

  Next, the semiconductor layer 1a is formed. That is, first, low pressure CVD (for example, using a monosilane gas, a disilane gas, or the like at a flow rate of about 400 to 600 cc / min on a base insulating film 12 in a relatively low temperature environment of about 450 to 550 ° C., preferably about 500 ° C. An amorphous silicon film is formed by CVD at a pressure of about 20-40 Pa. Next, heat treatment is performed in a nitrogen atmosphere at about 600 to 700 ° C. for about 1 to 10 hours, preferably 4 to 6 hours, so that the p-Si (polysilicon) film has a thickness of about 50 to 200 nm. The solid phase growth is preferably performed until the thickness becomes about 100 nm. As a method for solid phase growth, annealing using RTA or laser annealing using an excimer laser or the like may be used. At this time, a dopant of a group V element or a group III element may be slightly doped by ion implantation or the like depending on whether the pixel switching TFT 30 is an n-channel type or a p-channel type. Then, a semiconductor layer 1a having a predetermined pattern is formed by photolithography and etching.

  Next, as shown in step (2) of FIG. 6, the lower gate insulating film is formed by thermally oxidizing the semiconductor layer 1a constituting the TFT 30 at a temperature of about 900 to 1300 ° C., preferably about 1000 ° C. In some cases, an upper gate green film is formed by a low pressure CVD method or the like, thereby forming a single-layer or multilayer high-temperature silicon oxide film (HTO film) or silicon nitride film (including a gate insulating film). ) The insulating film 2 is formed. As a result, the semiconductor layer 1a has a thickness of about 30 to 150 nm, preferably about 35 to 50 nm, and the insulating film 2 has a thickness of about 20 to 150 nm, preferably about 30 to 100 nm. It becomes thickness.

  Next, in order to control the threshold voltage Vth of the TFT 30 for pixel switching, the n-channel region or the p-channel region of the semiconductor layer 1a is doped with a predetermined amount of a dopant such as boron by ion implantation or the like. To do.

  Next, a groove 12cv that communicates with the scanning line 11a is formed in the base insulating film 12. The groove 12cv is formed by dry etching such as reactive ion etching or reactive ion beam etching.

  Next, as shown in step (3) of FIG. 6, a polysilicon film is deposited by a low pressure CVD method or the like, and phosphorus (P) is further thermally diffused to make this polysilicon film conductive. Instead of this thermal diffusion, a doped silicon film in which P ions are introduced simultaneously with the formation of the polysilicon film may be used. The thickness of this polysilicon film is about 100 to 500 nm, preferably about 350 nm. Then, a gate electrode 3a having a predetermined pattern including the gate electrode portion of the TFT 30 is formed by photolithography and etching. When the gate electrode 3a is formed, a side wall 3b extending to the gate electrode 3a is also formed at the same time. The sidewall 3b is formed by depositing the polysilicon film described above also on the inside of the groove 12cv. At this time, since the bottom of the groove 12cv is in contact with the scanning line 11a, the side wall 3b and the scanning line 11a are electrically connected. Further, the relay electrode 719 is also formed simultaneously with the patterning of the gate electrode 3a.

  Next, a low concentration source region 1b and a low concentration drain region 1c, and a high concentration source region 1d and a high concentration drain region 1e are formed for the semiconductor layer 1a.

Here, the case where the TFT 30 is an n-channel TFT having an LDD structure will be described. Specifically, first, in order to form the low concentration source region 1b and the low concentration drain region 1c, the gate electrode 3a is used as a mask. A dopant of a group V element such as P is doped at a low concentration (for example, P ions are doped at a dose of 1 to 3 × 10 ¹³ cm ₂ ). As a result, the semiconductor layer 1a under the gate electrode 3a becomes a channel region 1a ′. At this time, the gate electrode 3a serves as a mask, so that the low concentration source region 1b and the low concentration drain region 1c are formed in a self-aligned manner. Next, in order to form the high concentration source region 1d and the high concentration drain region 1e, a resist layer having a planar pattern wider than the gate electrode 3a is formed on the gate electrode 3a. Thereafter, a dopant of a group V element such as P is doped at a high concentration (for example, P ions are doped at a dose of 1 to 3 × 10 ¹⁵ / cm ₂ ).

  In addition, it is not necessary to dope by dividing into two steps of low concentration and high concentration. For example, a TFT having an offset structure may be used without doping at a low concentration, or a self-aligned TFT may be formed by an ion implantation technique using P ions, B ions, or the like using the gate electrode 3a (gate electrode) as a mask. Good. By doping the impurities, the gate electrode 3a is further reduced in resistance.

  Next, as shown in step (4) of FIG. 6, NSG, PSG, BSG, and the like are formed on the gate electrode 3a by, for example, atmospheric pressure or low pressure CVD using TEOS gas, TEB gas, TMOP gas, or the like. A first interlayer insulating film 41 made of a silicate glass film such as BPSG, a silicon nitride film, or a silicon oxide film is formed. The film thickness of the first interlayer insulating film 41 is, for example, about 500 to 2000 nm. Here, preferably, annealing is performed at a high temperature of about 800 ° C. to improve the film quality of the first interlayer insulating film 41.

  Next, the contact hole 83 and the contact hole 881 are opened by dry etching such as reactive ion etching and reactive ion beam etching for the first interlayer insulating film 41. At this time, the former is formed so as to communicate with the high-concentration drain region 1e of the semiconductor layer 1a, and the latter is formed so as to communicate with the relay electrode 719.

  Next, as shown in step (5) of FIG. 6, a metal film such as Pt or a polysilicon film is formed on the first interlayer insulating film 41 to a thickness of about 100 to 500 nm by low pressure CVD or sputtering. A metal film of the lower electrode 71 having a predetermined pattern is formed. In this case, the metal film is formed so that both of the contact hole 83 and the contact hole 881 are filled, whereby the high-concentration drain region 1e, the relay electrode 719, and the lower electrode 71 are electrically connected. It is done.

  Next, a dielectric film 75 is formed on the lower electrode 71. The dielectric film 75 can be formed by various known techniques generally used for forming a TFT gate insulating film, as in the case of the insulating film 2. The silicon oxide film 75a is formed by the above-described thermal oxidation, CVD method or the like, and then the silicon nitride film 75b is formed by low pressure CVD method or the like. As the dielectric film 75 is made thinner, the storage capacitor 70 becomes larger. Therefore, it is advantageous to form a very thin insulating film with a film thickness of 50 nm or less on the condition that no defects such as film breakage occur after all. It is. Next, a metal film such as a polysilicon film or AL (aluminum) is formed on the dielectric film 75 to a thickness of about 100 to 500 nm by low pressure CVD or sputtering, and the metal film of the capacitive electrode 300 is formed. Form.

  Next, as shown in step (6) of FIG. 7, the lower electrode 71, the dielectric film 75, and the capacitor electrode 300 are patterned at once to form the lower electrode 71, the dielectric film 75, and the capacitor electrode 300. Thus, the storage capacity 70 is completed. Next, for example, a normal glass or low pressure CVD method using TEOS gas or the like, preferably a plasma CVD method is used to form a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like. A two-layer insulating film 42 is formed. When aluminum is used for the capacitor electrode 300, it is necessary to form a film at a low temperature by plasma CVD. The film thickness of the second interlayer insulating film 42 is about 500 to 1500 nm, for example.

  Up to the formation process of the second interlayer insulating film 42 is one or more manufacturing processes (step S2) including the high temperature process of FIG. In the subsequent steps for manufacturing the liquid crystal substrate, there is no high-temperature process exceeding the melting point of the amorphous carbon film. Accordingly, the amorphous carbon film 91 is formed after the second interlayer insulating film 42 is formed. Note that the coating process of the amorphous carbon film can be performed at any timing as long as the high temperature process exceeding the melting point of the amorphous carbon film is completed.

  In step S3 of FIG. 8, an amorphous carbon film 91 is formed on the non-element formation surface. FIG. 10 is an explanatory diagram showing a configuration of a manufacturing apparatus for diamond-like carbon (DLC) which is an amorphous carbon film 91.

  The apparatus of FIG. 10 employs a CVD method using ECR (Electron Cyclotron Resonance) plasma using a microwave and a magnetic field, and is described in Non-Patent Document “Shimadzu Review Vol.54 No2 (1997.8) page 136”. It has been done.

  The element substrate 10 on which the second interlayer insulating film 42 is formed is attached to the substrate holder 111 with the second interlayer insulating film 42 side facing the substrate holder 111. In the substrate holder 111, the mounting surface side of the element substrate 10 is introduced into the reaction chamber 112, and the other end side is disposed outside the reaction chamber 112 and connected to the matching box 114 via the capacitor 113. The matching box 114 is connected to the RF oscillator 115 and applies a high frequency bias to the substrate holder 111.

  The reaction chamber 112 is provided with a gas inlet 116 and an exhaust port 117, and the front surface of the reaction chamber 112 is opened and connected to a cylindrical plasma chamber 118. A quartz glass window 120 and a waveguide 121 are attached to the front surface of the plasma chamber 118, and the plasma chamber 118 is connected to the microwave oscillator 123 through the waveguide 121. A magnet coil 119 is disposed around the plasma chamber 118.

  After the reaction chamber 112 is evacuated to a high vacuum, a raw material gas is allowed to flow into the reaction chamber 112 through the gas inlet 116. Next, the microwave oscillated by the microwave oscillator 123 is introduced into the plasma chamber 118 through the waveguide and the quartz glass window 120. The plasma chamber 118 acts as a cavity resonator, and when a magnetic field is applied to the plasma chamber 118 by the magnet coil 119, electrons start a cyclotron motion. With appropriate settings, resonance between electron cyclotron motion and microwaves occurs. As a result, collision between electrons and gas molecules increases, and high-density plasma is obtained in the plasma chamber 118.

  On the other hand, the high frequency signal generated by the RF oscillator 115 is applied to the matching box 114, and the matching box 114 applies a negative self-bias to the element substrate 10 via the capacitor and the substrate holder 111. The high-density plasma generated in the plasma chamber 118 is drawn toward the element substrate 10 in the reaction chamber 112 by a divergent magnetic field, as indicated by the hatched portion in FIG. Thus, diamond-like carbon having a thickness of, for example, 10 to 100 nm, which is the amorphous carbon film 91, is formed on the non-element forming surface of the element substrate 10.

  After the amorphous carbon film 91 is formed on the non-element forming surface of the element substrate 10, one or more manufacturing processes including only a low temperature process are performed in step S4 of FIG. That is, the contact holes 81, 801 and 882 are opened by dry etching such as reactive ion etching and reactive ion beam etching with respect to the second interlayer insulating film 42 formed on the element forming surface side of the substrate material 10 ′. To do. At this time, the contact hole 81 is formed so as to communicate with the high concentration source region 1d of the semiconductor layer 1a, the contact hole 801 is communicated with the capacitor electrode 300, and the contact hole 882 is formed so as to communicate with the relay electrode 719. The

  Next, on the entire surface of the second interlayer insulating film 42, a thickness of about 100 to 500 nm, preferably about 300 nm, is formed by using a low resistance metal such as light-shielding aluminum or a metal silicide as a metal film by sputtering or the like. accumulate. Then, the data line 6a having a predetermined pattern is formed by photolithography and etching. At this time, at the time of the patterning, the shield layer relay layer 6a1 and the second relay layer 6a2 are also formed at the same time. The shield layer relay layer 6a1 is formed to cover the contact hole 801, and the second relay layer 6a2 is formed to cover the contact hole 882.

  Next, after a film made of titanium nitride is formed on the entire surface of these upper layers by a plasma CVD method or the like, a patterning process is performed so that the film remains only on the data line 6a (in step (7) in FIG. 7). Reference 41TN). However, the titanium nitride layer may be formed so as to remain on the shield layer relay layer 6a1 and the second relay layer 6a2, or may be formed so as to remain on the entire surface of the element substrate 10. Also good. Alternatively, the aluminum film may be formed at the same time as the aluminum film and etched in a lump.

  Next, as shown in step (8) of FIG. 7, a plasma CVD method that can form a film preferably at a low temperature by, for example, atmospheric or reduced pressure CVD using TEOS gas or the like so as to cover the data line 6a or the like. Thus, a third interlayer insulating film 43 made of a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed. The film thickness of the third interlayer insulating film 43 is, eg, about 500-3500 nm. Next, as shown in FIG. 4, the third interlayer insulating film 43 is planarized using, for example, CMP.

  Next, contact holes 803 and 804 are formed by dry etching such as reactive ion etching or reactive ion beam etching for the third interlayer insulating film 43. At this time, the contact hole 803 is formed so as to communicate with the shield layer relay layer 6a1, and the contact hole 804 is formed so as to communicate with the second relay layer 6a2.

  Next, a metal film of the shield layer 400 is formed on the third interlayer insulating film 43 by sputtering or plasma CVD. Here, first, a lower layer film is formed directly on the third interlayer insulating film 43 by using a low resistance material such as aluminum, and then a pixel electrode 9a to be described later such as titanium nitride is formed on the lower layer film. An upper layer film is formed using a material that does not cause electric corrosion and ITO that constitutes, and finally, the lower layer film and the upper layer film are patterned together to form a shield layer 400 having a two-layer structure. At this time, the third relay electrode 402 is also formed together with the shield layer 400.

  Next, a fourth interlayer insulating film 44 made of a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed by, for example, atmospheric pressure or low pressure CVD using TEOS gas or the like. . The film thickness of the fourth interlayer insulating film 44 is about 500 to 1500 nm, for example.

  Next, as shown in FIG. 4, the fourth interlayer insulating film 44 is planarized using, for example, CMP. Next, a contact hole 89 is formed by dry etching such as reactive ion etching or reactive ion beam etching for the fourth interlayer insulating film 44. At this time, the contact hole 89 is formed so as to communicate with the third relay electrode 402.

  Next, a transparent conductive film such as an ITO film is deposited on the fourth interlayer insulating film 44 to a thickness of about 50 to 200 nm by sputtering or the like. Then, the pixel electrode 9a is formed by photolithography and etching. When the electro-optical device is used as a reflection type, the pixel electrode 9a may be formed of an opaque material having a high reflectance such as AL.

  After applying a polyimide-based alignment film coating solution on the pixel electrode 9a of the element substrate 10 on which the pixels are configured in this manner, a rubbing process is performed in a predetermined direction so as to have a predetermined pretilt angle. Thus, the alignment film 16 is formed (see FIG. 4).

  On the other hand, for the counter substrate 20, a substrate material 20 ′ such as a glass substrate is first prepared, and a light shielding film 53 as a frame is formed by sputtering metal chromium, for example, and then performing photolithography and etching. These light shielding films 53 do not have to be conductive, and may be formed of a material such as resin black in which carbon or Ti is dispersed in a photoresist in addition to a metal material such as Cr, Ni, or AL.

  Next, a counter electrode 21 is formed by depositing a transparent conductive film such as ITO to a thickness of about 50 to 200 nm by sputtering or the like on the entire surface of the substrate material 20 '. Further, after the polyimide-based alignment film coating solution is applied to the entire surface of the counter electrode 21, the alignment film 22 is formed by performing a rubbing process in a predetermined direction so as to have a predetermined pretilt angle.

  Finally, as shown in FIGS. 1 and 2, the element substrate 10 and the counter substrate 20 on which the respective layers are formed, for example, form a seal material 52 along four sides of the counter substrate 20, and The upper and lower conductive materials 106 are formed at the four corners, and the alignment films 16 and 22 are bonded together by the sealing material 52 so as to face each other. Thus, the vertical conduction member 106 contacts the vertical conduction terminal 107 of the element substrate 10 at the lower end, and contacts the common electrode 21 of the counter substrate 20 at the upper end.

  Then, a liquid crystal layer 50 having a predetermined thickness is formed by sucking, for example, liquid crystal formed by mixing a plurality of types of nematic liquid crystals into the space between both substrates by vacuum suction or the like.

  The sealing material 52 is made of, for example, an ultraviolet curable resin, a thermosetting resin, or the like, and is cured by ultraviolet rays, heating, or the like in order to bond the two substrates together. In addition, if the liquid crystal device according to the present embodiment is applied to a liquid crystal device in which the liquid crystal device is small and performs enlarged display like a projector, the distance between the substrates (inter-substrate gap) ) Is set to a predetermined value, and a glass fiber or a cap material (spacer) such as glass beads is dispersed. Alternatively, such a gap material may be included in the liquid crystal layer 50 if the liquid crystal device is applied to a large-sized liquid crystal device such as a liquid crystal display or a liquid crystal television that displays the same size. When the liquid crystal device is used, an FPC copper foil pattern is connected to the external connection terminal.

  Needless to say, if the delay of the scanning signal supplied to the scanning line 11a and the gate electrode 3a is not a problem, the scanning line driving circuit 104 may be only on one side. The data line driving circuit 101 may be arranged on both sides along the side of the image display area 10a.

  On the element substrate 10, in addition to the data line driving circuit 101, the scanning line driving circuit 104, and the like, a sampling circuit that applies image signals to the plurality of data lines 6a at a predetermined timing, and a plurality of data lines 6a. In addition, a precharge circuit for supplying a precharge signal of a predetermined voltage level in advance of an image signal, an inspection circuit for inspecting quality, defects, etc. of the electro-optical device during manufacturing or at the time of shipment may be formed. Good.

  Further, in the above-described embodiment, instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the element substrate 10, for example, a driving LSI mounted on a TAB (Tape Automated Bonding) substrate is connected to the element substrate. You may make it connect electrically and mechanically through the anisotropic conductive film provided in the 10 peripheral part. Further, for example, a TN (Twisted Nematic) mode, a VA (Vertical Aligned) mode, and a PDLC (Polymer Dispersed Liquid Crystal) are respectively provided on the side on which the projection light of the counter substrate 20 enters and the side on which the outgoing light of the element substrate 10 exits. A polarizing film, a retardation film, a polarizing plate, and the like are arranged in a predetermined direction according to an operation mode such as a mode, or a normally white mode or a normally black mode.

  As described above, in the present embodiment, the amorphous carbon film 91 is formed on the non-element formation surface of the substrate material 10 ′ after the formation process of the second interlayer insulating film 42 is completed. The amorphous carbon film 91 has a sufficiently small friction coefficient, and is not easily damaged. Therefore, in the processes after the amorphous carbon film 91 forming process, the amorphous carbon film 91 is damaged even when the non-element forming surface of the element substrate 10 is brought into sliding contact with a non-illustrated conveying member or the like as the element substrate 10 is conveyed. There is nothing. Further, the density of the amorphous carbon film 91 is extremely high, and the occurrence of defects such as pinholes is small. Further, the amorphous carbon film 91 is excellent in corrosion resistance, and can be prevented from being corroded by a chemical solution during each manufacturing process after the formation process of the amorphous carbon film 91 or incorporation into a module of a liquid crystal device. Further, since DLC is a transparent film, it does not adversely affect the transmission of light. Therefore, it is not necessary to remove the substrate after completion of the substrate and after completion of the electro-optical device using the completed substrate.

  Note that the amorphous carbon film 91 may be removed after the pixel electrode 9a is formed.

  As described above, the amorphous carbon film 91 may be formed at any timing after the high temperature process is completed. For example, FIG. 9 shows an amorphous carbon film 91 forming step (step S3) between one or more manufacturing processes including only the low temperature process of step S11 and one or more manufacturing processes including only the low temperature process of step S12. The example which provided is shown. Even in this case, the element substrate 10 can be protected from scratches and the like after the amorphous carbon film 91 is formed.

  In the DLC film forming process, since the element substrate 10 is attached to the substrate holder 111, amorphous carbon is formed with an interlayer insulating film formed on the uppermost surface of the element substrate 10 on the element forming surface side. It is desirable to form the film 91.

  In the above embodiment, an example in which the non-element forming surface of the element substrate 10 is coated with the amorphous carbon film has been described. However, the non-element forming surface of the counter substrate 20 (the surface opposite to the common electrode 21 forming surface). It is clear that the counter substrate 20 can be protected from scratches and the like by covering the surface with an amorphous carbon film. In this case, the completed liquid crystal device has an advantage that the protective effect is high because both surfaces of the light incident / exit surface are covered with the amorphous carbon film 91.

  The amorphous carbon film 91 formed in the present embodiment has a physical property range shown in Table 1 below, for example.

[Table 1]
Density [g / cm ³ ] 1.5-1.8 to 2.23
Hydrogen concentration in the film [at.%] 33-40 to 0.3
Hardness [GPa] 21-33
Young's modulus [GPa] 160-225
Refractive index [λ = 270 nm / 633 nm] 2.0 / 1.9 to 2.7 / 2.6
SP3 ratio 60% ~ 90%
In the above embodiment, an example of a substrate for an electro-optical device has been described. However, it is obvious that the substrate can be applied to a semiconductor substrate or the like.

  In the above embodiment, an example in which a DLC film, which is an amorphous carbon film, is formed by an ECR plasma CVD apparatus has been described. However, an amorphous carbon film is formed by sputtering, a method using arc discharge, or a composition using an ion beam. It can be configured by a film method or the like.

  For example, the DLC film can be formed using a known cathodic arc process. The cathodic arc process is a technique for extracting plasma by applying an electric discharge having a high current to a material serving as a cathode in a vacuum, and has a feature that ion energy can be easily controlled. Further, the cathodic arc process includes a system for guiding only element ions having a selected ion energy to a substrate by a magnetic filter constituted by a solenoid.

  The element substrate 10 on which the second interlayer insulating film 42 is formed is placed on the stage with the second interlayer insulating film 42 facing the stage, that is, the non-element forming surface of the element substrate 10 facing upward. Then, plasma C + ions are supplied to the non-element forming surface of the element substrate 10 by a cathodic arc process. In this case, unnecessary cluster particles and neutral atoms simultaneously generated from the cathode material can be eliminated by the magnetic filter, and only purer element ions can be supplied to the element substrate 10. By adopting the cathodic arc process, a film structure having a high SP3 coupling ratio can be generated, and a high-purity, high-density, and hard DLC film can be formed on the non-element forming surface of the element substrate 10. it can.

(Electronics)
Next, an overall configuration, particularly an optical configuration, of an embodiment of a projection color display device as an example of an electronic apparatus using the electro-optical device described in detail as a light valve will be described. FIG. 11 is an explanatory diagram of a projection type color display device.

  In FIG. 11, a liquid crystal projector 1100, which is an example of a projection type color display device according to the present embodiment, prepares three liquid crystal modules including a liquid crystal device having a drive circuit mounted on a TFT array substrate, and each has a light bulb 100R for RGB. , 100G and 100B. In the liquid crystal projector 1100, when projection light is emitted from a lamp unit 1102 of a white light source such as a metal halide lamp, the light components R, G, and R corresponding to the three primary colors of RGB are obtained by three mirrors 1106 and two dichroic mirrors 1108. The light is divided into B and led to the light valves 100R, 100G and 100B corresponding to the respective colors. In particular, the B light is guided through a relay lens system 1121 including an incident lens 1122, a relay lens 1123, and an exit lens 1124 in order to prevent light loss due to a long optical path. The light components corresponding to the three primary colors modulated by the light valves 100R, 100G, and 100B are synthesized again by the dichroic prism 1112 and then projected as a color image on the screen 1120 via the projection lens 1114.

  The present invention can be applied not only to the TFT liquid crystal device substrate described above but also to various electro-optical device substrates. As an electro-optical device, not only a passive matrix type liquid crystal display panel but also an active matrix type liquid crystal panel (for example, a liquid crystal display panel including a TFT (thin film transistor) or a TFD (thin film diode) as a switching element) is similarly used. It is possible to apply. In addition to liquid crystal display panels, various devices such as electroluminescence devices, organic electroluminescence devices, plasma display devices, electrophoretic display devices, and devices using electron emission (Field Emission Display and Surface-Conduction Electron-Emitter Display, etc.) The present invention can be similarly applied to the electro-optical device. Furthermore, the present invention can be applied not only to a substrate for an electro-optical device but also to various semiconductor substrates.

FIG. 3 is a cross-sectional view illustrating an electro-optical device configured using the electro-optical device substrate according to the first embodiment of the invention. FIG. 2 is a plan view of a liquid crystal device, which is an electro-optical device configured using the electro-optical device substrate according to the present embodiment, viewed from the counter substrate side together with each component formed thereon. FIG. 6 is an equivalent circuit diagram of various elements, wirings, and the like in a plurality of pixels constituting a pixel region of the liquid crystal device. FIG. 4 is a cross-sectional view illustrating a pixel structure of a liquid crystal device in detail. The top view which shows the film-forming pattern of the principal part among the film-forming patterns of each layer about the some adjacent pixel formed on the element substrate of this Embodiment. Process drawing which shows the manufacturing method of the board | substrate for electro-optical devices in this Embodiment in order of a process with sectional drawing. Process drawing which shows the manufacturing method of the board | substrate for electro-optical devices in this Embodiment in order of a process with sectional drawing. 9 is a flowchart showing a method for manufacturing a substrate for an electro-optical device according to the present embodiment. 9 is a flowchart showing a method for manufacturing a substrate for an electro-optical device according to the present embodiment. Explanatory drawing which shows the structure of the manufacturing apparatus of the diamond-like carbon (DLC) which is the amorphous carbon film | membrane 91. FIG. Explanatory drawing of a projection type color display apparatus.

Explanation of symbols

    9a ... pixel electrode, 10 ... element substrate, 20 ... counter substrate, 21 ... counter electrode, 52 ... sealing material, 91 ... amorphous carbon film.

Claims (8)

A substrate material;
An element formed on the element forming surface side of the substrate material;
An electro-optical device substrate comprising: an amorphous carbon film formed on a non-element forming surface side of the substrate material.   The electro-optical device substrate according to claim 1, wherein the amorphous carbon film is a diamond-like carbon film.   The substrate for an electro-optical device according to claim 1, wherein the substrate material and the amorphous carbon film are transparent. Forming an element by a high temperature process on the element forming surface side of the substrate material;
And a step of forming an amorphous carbon film on the non-element forming surface side of the substrate material after the high temperature process is completed.   A method of manufacturing a substrate for an electro-optical device, further comprising a step of forming an element by a low temperature process on the element forming surface side of the substrate material after the step of forming the amorphous carbon film.   An electro-optical device comprising the electro-optical device substrate and an electro-optical material.   A substrate for an electro-optical device, wherein an element is provided on one surface of an insulating transparent substrate, and an amorphous carbon film is provided on the other surface of the one surface.   An electro-optical device comprising the electro-optical device substrate according to claim 7.

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