JP2005134541A - Resist pattern forming method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily and reliably perform exposure without using a dedicated exposure mask even if dimensional variation differs for every device when an opening is formed in a solder resist layer. <P>SOLUTION: An upper light shielding layer 13 comprising a light shielding pigment ink such as a carbon black ink is formed by an ink jet head 100 on a top face of an upper solder resist layer 4 in a portion corresponding to an electrode pad part of upper wiring 3. Exposure is performed by irradiation with UV from the top face side to cure the upper solder resist layer 4 in the region except the portion under the upper light shielding layer 13. Development is then performed to remove the uncured upper solder resist layer 4 under the upper light shielding layer 13 together with the upper light shielding layer 13 thereon, accordingly an opening is formed. When the position of the electrode pad undergoes a change by expansion or contraction of a substrate 1, the position where the light shielding layer is formed by the ink jet head 100 is properly corrected according to the position change. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a resist pattern forming method for patterning a resist layer such as a solder resist layer formed on a wiring board into a predetermined shape.

  A conventional method for forming a resist layer such as a solder resist layer includes a negative solder on the entire surface of an insulating layer including wiring having electrode pad portions such as connection pads formed on an insulating layer on a substrate such as a wiring substrate. A resist layer is formed, exposed using an exposure mask having a light-shielding portion in a portion corresponding to the electrode pad portion, and then developed to pattern the solder resist layer in the portion corresponding to the electrode pad portion, thereby opening the opening portion. There is a method of forming (see, for example, Patent Document 1).

JP 2000-114693 A

  By the way, when performing exposure using the exposure mask, the position of the electrode pad fluctuates (dimension fluctuation) from a predetermined position due to thermal expansion or contraction due to the thermal history or the like so far on the substrate. There may be a deviation from the position of the light shielding part. In such a case, it may be necessary to recreate the exposure mask several times in order to accurately align the position of the light shielding portion of the exposure mask with the position of the electrode pad. Moreover, since such dimensional variations may differ from one substrate to another, there is a problem that it takes a lot of time and cost.

  Accordingly, an object of the present invention is to provide a resist pattern forming method capable of easily and reliably performing exposure without using a dedicated exposure mask and even if the dimensional variation differs for each substrate. To do.

According to the first aspect of the present invention, a resist layer is formed on a substrate, a light shielding ink is applied on the resist layer by an ink jet head to form a light shielding layer, and the resist layer is exposed through the light shielding layer. Then, the resist layer is patterned by performing development.
According to a second aspect of the present invention, in the first aspect of the invention, the resist layer is a negative type, the substrate has at least one electrode pad portion, and the portion in the portion corresponding to the electrode pad portion. The light shielding layer is formed on the resist layer, and exposure and development are performed to form an opening in the resist layer in a portion corresponding to the electrode pad portion.
The invention according to claim 3 is the invention according to claim 1 or 2, wherein the substrate is a printed wiring board, and includes at least an insulating substrate, an upper layer wiring formed on the insulating substrate, and the upper layer wiring. And the electrode pad portion formed by a part of the electrode pad portion.
According to a fourth aspect of the present invention, in the first or second aspect of the present invention, the substrate includes at least one semiconductor structure including at least a semiconductor substrate and a plurality of external connection electrodes provided on the semiconductor substrate. A body, an insulating layer provided around the semiconductor structure, and at least one layer provided on the insulating layer at least partially electrically connected to an external connection electrode of the semiconductor structure An upper layer rewiring and the electrode pad portion formed by a part of the upper layer rewiring are provided.
According to a fifth aspect of the present invention, in the first to fourth aspects of the present invention, the resist layer is a solder resist layer.
According to a sixth aspect of the present invention, in the first to fourth aspects of the present invention, the light-shielding ink is a light-shielding pigment ink.
According to a seventh aspect of the present invention, in the first to fourth aspects of the present invention, the resist layer is formed by applying a liquid resist.
According to an eighth aspect of the present invention, in the first to fourth aspects of the present invention, the resist layer is formed by laminating a dry film resist.
The invention according to claim 9 is the invention according to claim 7 or 8, wherein the light shielding layer is removed together with the resist layer by the development.
The invention described in claim 10 is characterized in that, in the invention described in claim 7, the light shielding layer is removed before the development.
The invention according to claim 11 is the invention according to claim 8, wherein a transparent cover film is laminated on the upper surface of the dry film resist, and the light shielding layer is formed on the upper surface of the cover film. The exposure is performed, and then the cover film is peeled off together with the light shielding layer, and then the development is performed.
According to a twelfth aspect of the present invention, in the invention according to the second to fourth aspects, the position at which the light shielding layer is formed by the ink jet head is a deviation amount from a predetermined position of the position of the electrode pad on the substrate. The correction is made according to the above.

  According to this invention, since the light shielding ink is applied to the resist layer by the ink jet head to form the light shielding layer, the light shielding layer is formed at a desired position without using a dedicated exposure mask. The layer can be patterned. Furthermore, even when the position of the electrode pad for forming the light shielding layer varies due to the expansion and contraction of the substrate, the formation position of the light shielding layer by the inkjet head may be corrected according to the variation in the position of the electrode pad. Formation can be performed easily and reliably.

(Application example 1 to printed wiring boards)
FIG. 1 shows a partial cross-sectional view of an example of a printed wiring board provided with a solder resist layer formed by the resist pattern forming method of the present invention. This printed wiring board includes an insulating substrate 1. The insulating substrate plate 1 is, for example, a glass fiber, an aramid fiber, a liquid crystal fiber or the like impregnated with an epoxy resin, a polyimide resin, a BT (bismaleimide / triazine) resin, PPE (polyphenylene ether), or the like, or a resin It consists of an insulating material such as a simple substance.

  An upper base metal layer 2 made of copper or the like is provided on the upper surface of the insulating substrate 1. An upper wiring 3 made of copper is provided on the entire upper surface of the upper base metal layer 2. An upper solder resist layer 4 is provided on the upper surface of the insulating substrate 1 including the upper wiring 3. An opening 5 is provided in the upper solder resist layer 4 in a portion corresponding to the connection pad (electrode pad) portion of the upper wiring 3.

  A lower base metal layer 6 made of copper or the like is provided on the lower surface of the insulating substrate 1. A lower wiring 7 made of copper is provided on the entire lower surface of the lower base metal layer 6. A lower solder resist layer 8 is provided on the lower surface of the insulating substrate 1 including the lower layer wiring 7. An opening 9 is provided in the lower solder resist layer 8 in a portion corresponding to the connection pad (electrode pad) portion of the lower wiring 7.

  At least a part of the upper wiring 3 including the upper base metal layer 2 and at least a part of the lower wiring 7 including the lower base metal layer 6 are copper provided on the inner wall surface of the through hole 10 provided in the insulating substrate 1. The base metal layer 11a and the copper layer 11b are connected to each other via a vertical conduction portion 11 made of a base metal layer 11a and the copper layer 11b. In this case, the vertical conduction part 11 is filled with a conductive material 12 made of silver paste, copper paste, conductive resin or the like in order to improve the electrical conduction of the vertical wiring. It may be filled or may be a cavity.

  Next, an example of a method for manufacturing this printed wiring board will be described. First, as shown in FIG. 2, the upper layer wiring 3 including the upper base metal layer 2 is formed on the upper surface of the insulating substrate 1, and the lower layer wiring 7 including the lower base metal layer 6 is formed on the lower surface of the insulating substrate 1. At least a part of the upper layer wiring 3 including the base metal layer 2 and at least a part of the lower layer wiring 7 including the lower base metal layer 6 are connected via the vertical conduction part 11 formed in the through hole 10 of the insulating substrate 1. Prepare what was done.

  Next, as shown in FIG. 3, an upper solder resist layer 4 is formed on the upper surface of the insulating substrate 1 including the upper wiring 3 by applying a negative liquid resist by a screen printing method, a spin coating method, or the like. Further, a lower solder resist layer 8 is formed on the lower surface of the insulating substrate 1 including the lower layer wiring 7 by applying a negative liquid resist by a screen printing method, a spin coating method, or the like.

  Next, as shown in FIG. 4, the ink jet head 100 is sequentially moved to the position on each connection pad portion on the upper surface of the upper solder resist layer 4 in the portion corresponding to the connection pad portion of the upper layer wiring 3, and the carbon black ink A light-shielding ink made of a light-shielding pigment ink such as the above is jetted from the inkjet head 100 and applied. By applying the light-shielding ink by the inject head 100, the upper light-shielding layer 13 made of a light-shielding pigment ink such as carbon black ink is formed at a desired position on each connection pad portion.

  Further, for example, by turning over the insulating substrate 1, the carbon black ink or the like is similarly applied to the lower surface of the lower solder resist layer 8 in the portion corresponding to the connection pad portion of the lower layer wiring 7 by applying the light shielding ink by the inkjet head 100. A lower light shielding layer 14 made of light shielding pigment ink is formed.

  Next, as shown in FIG. 5, when exposure is performed by irradiating ultraviolet rays from the upper surface side, the upper solder resist layer 4 in a region other than the upper light shielding layer 13 is cured, and the upper solder resist under the upper light shielding layer 13 is cured. Layer 4 remains uncured. Further, when exposure is performed by irradiating ultraviolet rays from the lower surface side, the lower solder resist layer 8 in a region other than on the lower light shielding layer 13 is cured, and the upper solder resist layer 8 on the lower light shielding layer 14 remains in an uncured state. It becomes.

  Next, when development is performed, the uncured upper solder resist layer 4 under the upper light shielding layer 13 is removed together with the upper light shielding layer 13 thereon, and the uncured lower solder resist layer 8 on the lower light shielding layer 14 is removed. Are removed together with the lower light shielding layer 14 below. As a result, as shown in FIG. 1, an opening 5 is formed in the upper solder resist layer 4 in the portion corresponding to the connection pad portion of the upper wiring 3, and the lower layer in the portion corresponding to the connection pad portion of the lower wiring 7. Openings 9 are formed in the solder resist layer 8.

  As described above, in the resist pattern forming method, since the light shielding layers 13 and 14 are formed on the surfaces of the solder resist layers 4 and 8 by applying the light shielding ink using the inkjet head 100, a dedicated exposure mask is used. Exposure can be performed without using it. Further, since the light shielding layers 13 and 14 are in close contact with the surfaces of the solder resist layers 4 and 8, even if a simple exposure apparatus is used, exposure can be performed with high accuracy.

  Next, the case where the insulating substrate 1 expands and contracts due to the heat history so far and the position variation (dimension variation) of the connection pad portions of the wirings 3 and 7 occurs will be described. For example, when alignment marks are formed at the four corners on the insulating substrate 1, the positions of these alignment marks are detected by pattern recognition using a camera, and these detected position data are set as predetermined position data. If the amount of positional deviation in the X and Y directions is calculated and the light shielding layer forming position by the ink jet printer is corrected based on the calculation result, exposure is easy even if the dimensional variation differs for each insulating substrate 1. This can be done reliably and reliably.

  Here, among the ink jet printers currently on the market, there are high-accuracy ones for printing symbolic marks such as printed wiring boards. Some ink jet printers have, for example, an accuracy of ± 0.05 mm, a resolution of 600 dpi, and a line width printing performance of about 60 μm. In addition, there is a print position correction function based on the alignment mark pattern recognition as described above.

  On the other hand, when the light shielding layers 13 and 14 described above have a circular pattern with a diameter of 0.2 to 0.4 mm, for example, the accuracy is such that the ink jet printer can sufficiently cope with the above. An ink jet printer currently available for forming the light shielding layers 13 and 14 can be easily applied. Further, the correction function of the printing position by pattern recognition can be applied to the correction of the light shielding layer forming position. The light shielding layers 13 and 14 formed of the light shielding pigment ink such as carbon black ink have sufficient light shielding properties even for an exposure amount of 600 mJ / cm 2. Works well as a mask.

  By the way, since the solder resist layers 4 and 8 also have a function as a protective film for the wirings 3 and 7, environmental resistance is required, and the solder resist layers 4 and 8 are formed relatively thick, for example, 30 to 40 μm or more. Therefore, although it is extremely difficult to form the solder resist layers 4 and 8 themselves by applying ink with an ink jet head, the present invention does not apply the solder resist layers themselves with an ink jet head, but uses an ink jet head to block light. Since the ink is applied and the light shielding layer is formed on the solder resist layer, the inkjet head in the currently available inkjet printer can be applied relatively easily.

(Modification)
In the above embodiment, the case where the uncured upper solder resist layer 4 under the upper light-shielding layer 13 is removed together with the upper light-shielding layer 13 thereon by development has been described. The layer 13 may be removed by washing or the like, and then the uncured upper solder resist layer 4 may be removed by development. In this case, it is possible to prevent ink from being mixed into the collected developer.

(Application example 2 to printed wiring boards)
Although the case where the solder resist layers 4 and 8 are formed by applying a liquid resist has been described in the above embodiment, the present invention is not limited to this. For example, as shown in FIG. 6, the solder resist layers 4 and 8 may be formed by laminating a dry film resist. Here, as shown in FIG. 7, the dry film 21 has a carrier film 23 laminated on one surface of a negative dry film resist 22 and a cover film 24 made of transparent polyethylene terephthalate, polyethylene or the like on the other surface. It is commercially available as a three-layer structure.

  For this reason, the dry film resist 22 including the cover film 24 can be laminated on the surface of the object while peeling off the carrier film 23. In this way, as shown in FIG. 6, the upper solder resist layer 4 including the upper cover film 15 is laminated on the upper surface of the insulating substrate 1 including the upper wiring 3. Further, the lower solder resist layer 8 including the lower layer cover film 16 is laminated on the lower surface of the insulating substrate 1 including the lower layer wiring 7.

  Next, on the upper surface of the upper layer cover film 15 in the portion corresponding to the connection pad portion of the upper layer wiring 3, as in the case shown in FIG. An upper light shielding layer 13 made of pigment ink is formed. Similarly, on the lower surface of the lower layer cover film 16 in the portion corresponding to the connection pad portion of the lower layer wiring 7, similarly, the lower layer light shielding layer 14 made of a light shielding pigment ink such as carbon black ink by applying the light shielding ink by the inkjet head 100. Form.

  Next, when exposure is performed by irradiating ultraviolet rays from the upper surface side, the upper solder resist layer 4 in a region other than the upper layer light shielding layer 13 is cured, and the upper solder resist layer 4 under the upper light shielding layer 13 is in an uncured state. Will remain. When exposure is performed by irradiating ultraviolet rays from the lower surface side, the lower solder resist layer 8 in a region other than on the lower light shielding layer 13 is cured, and the upper solder resist layer 4 below the upper light shielding layer 13 remains in an uncured state. It becomes. Next, the upper cover film 15 is peeled off together with the upper light shielding layer 13 thereon. Further, the lower cover film 16 is peeled off together with the lower light shielding layer 14 below.

  Next, when development is performed, the uncured upper solder resist layer 4 is removed, and the uncured lower solder resist layer 8 is removed. As a result, as shown in FIG. 1, an opening 5 is formed in the upper solder resist layer 4 in the portion corresponding to the connection pad portion of the upper wiring 3, and the lower layer in the portion corresponding to the connection pad portion of the lower wiring 7. Openings 9 are formed in the solder resist layer 8.

  In this case, since the light shielding layers 13 and 14 are in close contact with the surfaces of the cover films 15 and 16, even if a simple exposure apparatus is used, the exposure can be performed with high accuracy. Further, as in the case of the above-described embodiment, exposure can be performed easily and reliably without using a dedicated exposure mask and even if the dimensional variation differs for each insulating substrate 1.

(Application example to semiconductor devices)
FIG. 8 shows a cross-sectional view of an example of a semiconductor device provided with a solder resist layer formed by the resist pattern forming method of the present invention. This semiconductor device includes a base plate 31 having a planar shape. The base plate 31 is made of, for example, glass fiber, aramid fiber, liquid crystal fiber or the like impregnated with an epoxy resin, polyimide resin, BT resin, PPE, or the like, an insulating material such as silicon, glass, ceramics, or a single resin, or It is made of a metal material such as copper or aluminum.

  On the upper surface of the base plate 31, the lower surface of a planar rectangular semiconductor structure 32 having a size somewhat smaller than the size of the base plate 31 is bonded via an adhesive layer 32. In this case, the semiconductor structure 32 is generally called a CSP (chip size package) and includes a semiconductor substrate 33 made of planar rectangular silicon or the like. The semiconductor substrate 33 is bonded to the base plate 31 via the adhesive layer 32. An integrated circuit (not shown) having a predetermined function is provided on the upper surface of the semiconductor substrate 33, and a plurality of connection pads 35 made of aluminum metal or the like are provided on the periphery of the upper surface so as to be connected to the integrated circuit.

  An insulating film 36 made of silicon oxide or the like is provided on the upper surface of the semiconductor substrate 33 excluding the central portion of the connection pad 35, and the central portion of the connection pad 35 is exposed through an opening 37 provided in the insulating film 36. Yes. A protective film (insulating film) 38 made of epoxy resin, polyimide resin or the like is provided on the upper surface of the insulating film 36. In this case, an opening 39 is provided in the protective film 38 in a portion corresponding to the opening 37 of the insulating film 36.

  A base metal layer 40 made of copper or the like is provided on the upper surface of the protective film 38. A rewiring 41 made of copper is provided on the entire upper surface of the base metal layer 40. One end of the rewiring 41 including the base metal layer 40 is connected to the connection pad 35 via both openings 37 and 39. A columnar electrode 42 made of copper is provided on the upper surface of the connection pad portion of the rewiring 41. A sealing film 44 made of epoxy resin, polyimide resin or the like is provided on the upper surface of the protective film 38 including the rewiring 41 so that the upper surface is flush with the upper surface of the columnar electrode 42.

  A rectangular frame-shaped insulating layer 44 is provided on the upper surface of the base plate 31 around the semiconductor structure 32 so that the upper surface is substantially flush with the upper surface of the semiconductor structure 32. The insulating layer 44 is made of, for example, a thermosetting resin or a material in which a reinforcing material such as glass fiber or silica filler is dispersed in a thermosetting resin.

  A first upper insulating film 45 is provided on the upper surfaces of the semiconductor structure 32 and the insulating layer 44 with the upper surfaces thereof being flat. The first upper-layer insulating film 45 is generally used as a build-up material used for a build-up substrate. For example, a reinforcing material such as a fiber or a filler in a thermosetting resin such as an epoxy resin or a BT resin. Is contained. In this case, the fiber is glass fiber, aramid fiber, or the like. The filler is a silica filler or a ceramic filler.

  A first base metal layer 46 made of copper or the like is provided on the upper surface of the first upper insulating film 45. A first upper layer rewiring 47 made of copper is provided on the entire upper surface of the first base metal layer 46. One end portion of the first upper layer rewiring 47 including the first base metal layer 46 is connected through an opening 48 provided in the first upper layer insulating film 45 in a portion corresponding to the central portion of the upper surface of the columnar electrode 42. It is connected to the upper surface of the columnar electrode 42.

  On the upper surface of the first upper layer insulating film 45 including the first upper layer rewiring 47, a second upper layer insulating film 49 made of epoxy resin, polyimide resin or the like is provided. A second base metal layer 50 made of copper or the like is provided on the upper surface of the second upper insulating film 49. A second upper layer rewiring 51 made of copper is provided on the entire upper surface of the second base metal layer 50. One end of the second upper layer rewiring 51 including the second base metal layer 50 is an opening provided in the second upper layer insulating film 49 in a portion corresponding to the connection pad portion of the first upper layer rewiring 47. The connection pad portion of the first upper layer rewiring 47 is connected via 52.

  A solder resist layer 53 is provided on the upper surface of the second upper insulating film 49 including the second upper rewiring 51. An opening 54 is provided in the solder resist layer 53 in a portion corresponding to the connection pad (electrode pad) portion of the second upper layer rewiring 51. Solder balls 55 are provided in and above the opening 54 so as to be connected to the connection pad portion of the second upper layer rewiring 51. The plurality of solder balls 55 are arranged in a matrix on the upper surface of the solder resist layer 53.

  By the way, the size of the base plate 31 is made somewhat larger than the size of the semiconductor structure 32 because the arrangement area of the solder balls 55 is changed according to the increase in the number of connection pads 35 on the semiconductor substrate 33. Thus, the size and pitch of the connection pad portion (the portion in the opening 54 of the solder resist layer 53) of the second upper layer rewiring 51 are made larger than the size and pitch of the columnar electrode 42. This is to make it larger.

  For this reason, the connection pad portion of the second upper layer rewiring 51 arranged in a matrix form not only the region corresponding to the semiconductor structure 32 but also the insulating layer 44 provided outside the side surface of the semiconductor structure 32 and It is also disposed on a region corresponding to the external insulating layer 22. That is, among the solder balls 55 arranged in a matrix, at least the outermost solder ball 55 is arranged around the semiconductor structure 32.

  Next, an example of a method for manufacturing this semiconductor device will be described. First, as shown in FIG. 9, the base plate 31 is prepared in such a size that a plurality of the base plates 31 shown in FIG. Next, the adhesive layer 32 bonded to the lower surface of the semiconductor substrate 33 of the semiconductor structure 32 is bonded to a plurality of predetermined locations on the upper surface of the base plate 31.

  Next, a first insulating material 44a is formed on the upper surface of the base plate 31 between the semiconductor structural bodies 32 and outside the semiconductor structural bodies 32 disposed on the outermost periphery by, for example, a screen printing method or a spin coating method. Further, a sheet-like second insulating material 45a is disposed on the upper surface. The first insulating material 44a is a thermosetting resin or a material in which a reinforcing material such as glass fiber or silica filler is dispersed in a thermosetting resin.

  The sheet-like second insulating material 45a is not limited, but is preferably a buildup material. As this buildup material, a silica filler is mixed in a thermosetting resin such as an epoxy resin or a BT resin. Some thermosetting resins are in a semi-cured state. However, as the second insulating material 45a, a glass fiber impregnated with a thermosetting resin such as an epoxy-based resin, and a prepreg material that is in a sheet shape with the thermosetting resin semi-cured, or a filler is not mixed, A material composed only of a thermosetting resin can also be used.

  Next, the first and second insulating materials 44a and 45a are heated and pressurized using a pair of heating and pressing plates 61 and 62 shown in FIG. Then, an insulating layer 44 is formed on the upper surface of the base plate 31 between the semiconductor structural bodies 32 and outside the semiconductor structural body 32 disposed on the outermost periphery, and the first upper layer insulation is formed on the upper surfaces of the semiconductor structural body 32 and the insulating layer 44. A film 45 is formed.

  In this case, the upper surface of the first upper-layer insulating film 45 is pressed by the lower surface of the upper heating / pressing plate 61 and thus becomes a flat surface. Therefore, a polishing step for flattening the upper surface of the first upper insulating film 45 is unnecessary. For this reason, even if the size of the base plate 31 is relatively large, for example, about 500 × 500 mm, the upper surface of the first upper insulating film 45 is flattened at once for the plurality of semiconductor structures 32 arranged thereon. And can be done easily.

  Next, as shown in FIG. 11, an opening 48 is formed in the first upper insulating film 45 at a portion corresponding to the central portion of the upper surface of the columnar electrode 42 by laser processing with laser beam irradiation. Next, as shown in FIG. 12, a first upper layer rewiring 47 including a first base metal layer 46 is formed on the upper surface of the first upper layer insulating film 45. In this case, one end of the first upper layer rewiring 47 including the first base metal layer 46 is connected to the upper surface of the columnar electrode 42 through the opening 48 of the first upper layer insulating film 45.

  Next, a second upper insulating film 49 made of an epoxy resin, a polyimide resin, or the like is formed on the upper surface of the first upper insulating film 45 including the first upper rewiring 47 by a screen printing method, a spin coating method, or the like. Form. In this case, an opening 30 is formed in the second upper insulating film 49 in a portion corresponding to the connection pad portion of the first upper redistribution line 47.

  Next, the second upper layer rewiring 51 including the second base metal layer 50 is formed on the upper surface of the second upper layer insulating film 49. In this case, one end portion of the second upper layer rewiring 51 including the second base metal layer 50 is connected to the connection pad portion of the first upper layer rewiring 47 through the opening 52 of the second upper layer insulating film 449. Connected.

  Next, a solder resist layer 53 is formed on the upper surface of the second upper-layer insulating film 49 including the second upper-layer rewiring 51 by applying a negative liquid resist by a screen printing method, a spin coating method, or the like. Next, light shielding of carbon black ink or the like is performed on the upper surface of the solder resist layer 53 in a portion corresponding to the connection pad portion of the second upper layer rewiring 51 by applying light shielding ink using an inkjet head 100 (not shown). A light shielding layer 63 made of a conductive pigment ink is formed.

  Next, when exposure is performed by irradiating ultraviolet rays from the upper surface side, the solder resist layer 53 in a region other than the region under the light shielding layer 63 is cured, and the solder resist layer 53 under the light shielding layer 63 remains in an uncured state. Next, when development is performed, the uncured solder resist layer 53 under the light shielding layer 63 is removed together with the light shielding layer 63 thereon. As a result, as shown in FIG. 13, an opening 54 is formed in the solder resist layer 53 in a portion corresponding to the connection pad portion of the second upper layer rewiring 51.

  Next, as shown in FIG. 14, solder balls 55 are formed in and above the opening 54 by connecting to the connection pad portion of the second upper layer rewiring 51. Next, as shown in FIG. 15, the solder resist layer 53, the second upper insulating film 49, the first upper insulating film 45, the insulating layer 44, and the base plate 31 are cut between adjacent semiconductor structures 32. Then, a plurality of semiconductor devices shown in FIG. 8 are obtained.

  In this case, since the light shielding layer 63 is in close contact with the surface of the solder resist layer 53, exposure can be performed with high accuracy even if a simple exposure apparatus is used. Further, as in the case of the above-described embodiment, exposure can be performed easily and reliably without using a dedicated exposure mask and even if the dimensional variation differs for each base plate 31 before cutting.

  Next, another example of correcting the light shielding layer forming position by the ink jet head will be described. The size of the base plate 31 in the state shown in FIG. 12 is large enough to obtain a plurality of semiconductor devices shown in FIG. 8 by cutting between the adjacent semiconductor structures 32. Therefore, the base plate 31 is divided into a plurality of small blocks (for example, blocks corresponding to one or a plurality of semiconductor structures 32).

  Then, the position of the connection pad portion of one second upper layer rewiring 51 set in advance in one small block is detected by pattern recognition using a camera, and the detected position data is compared with the predetermined position data set in advance. Then, the amount of positional deviation in the XY directions is calculated, and based on the calculation result, the light shielding layer forming position by the inkjet head for the one small block is corrected. In this case, since the size is small in the small block, the positional deviation can be ignored. The solder resist may be a positive type.

1 is a partial cross-sectional view of an example of a printed wiring board provided with a solder resist layer formed by the resist pattern forming method of the present invention. Sectional drawing of what was prepared initially in an example of the manufacturing method of the printed wiring board shown in FIG. Sectional drawing of the process following FIG. FIG. 4 is a cross-sectional view of a process for forming a light-shielding layer by applying light-shielding ink with an inkjet head following FIG. 3. Sectional drawing of the process following FIG. FIG. 9 is a partial cross-sectional view for explaining another example of a printed wiring board provided with a solder resist layer formed by the resist pattern forming method of the present invention. The perspective view shown in order to demonstrate a dry film. Sectional drawing of an example of the semiconductor device provided with the soldering resist layer formed by the resist pattern formation method of this invention. Sectional drawing of a predetermined | prescribed process in an example of the manufacturing method of the semiconductor device shown in FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. FIG. 15 is a sectional view of a step following FIG. 14.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Insulation board | substrate 3 Upper layer wiring 4 Upper layer soldering resist layer 5 Opening part 7 Lower layer wiring 8 Lower layer soldering resist layer 9 Opening part 11 Vertical conduction part 13 Upper layer light shielding layer 14 Lower layer light shielding layer 15 Upper layer cover film 16 Lower layer cover film 100 Inkjet head

Claims (12)

A resist layer is formed on the substrate, a light shielding ink is applied onto the resist layer by an ink jet head to form a light shielding layer, and the resist layer is exposed and developed through the light shielding layer to form the resist layer. A resist pattern forming method comprising patterning. 2. The invention according to claim 1, wherein the resist layer is a negative type, the substrate has at least one electrode pad portion, and the light shielding layer is formed on the resist layer in a portion corresponding to the electrode pad portion. Then, exposure and development are performed to form an opening in the resist layer in a portion corresponding to the electrode pad portion. 3. The invention according to claim 1, wherein the substrate is a printed wiring board, and the electrode is formed by at least an insulating substrate, an upper layer wiring formed on the insulating substrate, and a part of the upper layer wiring. A resist pattern forming method. 3. The semiconductor device according to claim 1, wherein the substrate includes at least one semiconductor structure having at least a semiconductor substrate and a plurality of external connection electrodes provided on the semiconductor substrate, and a periphery of the semiconductor structure. An insulating layer provided on the insulating layer, at least a part of the upper layer rewiring provided on the insulating layer at least partially electrically connected to the external connection electrode of the semiconductor structure, and the upper layer rewiring A resist pattern forming method, comprising: the electrode pad portion formed by a part of the electrode pad portion. 5. The resist pattern forming method according to claim 1, wherein the resist layer is a solder resist layer. 5. The resist pattern forming method according to claim 1, wherein the light-shielding ink is a light-shielding pigment ink. 5. The resist pattern forming method according to claim 1, wherein the resist layer is formed by applying a liquid resist. 5. The resist pattern forming method according to claim 1, wherein the resist layer is formed by laminating a dry film resist. 9. The resist pattern forming method according to claim 7, wherein the resist layer under the light shielding layer is removed together with the light shielding layer by the development. 8. The resist pattern forming method according to claim 7, wherein the light shielding layer is removed before the development. 9. The invention according to claim 8, wherein a transparent cover film is laminated on the upper surface of the dry film resist, the light shielding layer is formed on the upper surface of the cover film, and then the exposure is performed, and then the cover film Is removed together with the light-shielding layer, and then the development is performed. 5. The invention according to claim 2, wherein the position where the light shielding layer is formed by the ink jet head is corrected according to a deviation amount of the position of the electrode pad on the substrate from a predetermined position. A resist pattern forming method.

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