JP2005129922A5 - - Google Patents

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JP2005129922A5
JP2005129922A5 JP2004289726A JP2004289726A JP2005129922A5 JP 2005129922 A5 JP2005129922 A5 JP 2005129922A5 JP 2004289726 A JP2004289726 A JP 2004289726A JP 2004289726 A JP2004289726 A JP 2004289726A JP 2005129922 A5 JP2005129922 A5 JP 2005129922A5
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Japan
Prior art keywords
conductive layer
manufacturing
contact
insulating layer
conductive
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JP2004289726A
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Japanese (ja)
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JP2005129922A (en
JP4597627B2 (en
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Priority to JP2004289726A priority Critical patent/JP4597627B2/en
Priority claimed from JP2004289726A external-priority patent/JP4597627B2/en
Publication of JP2005129922A publication Critical patent/JP2005129922A/en
Publication of JP2005129922A5 publication Critical patent/JP2005129922A5/ja
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Publication of JP4597627B2 publication Critical patent/JP4597627B2/en
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Expired - Fee Related legal-status Critical Current

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Claims (13)

基板上に絶縁層を形成し、
前記絶縁層に接するように第１の導電層を形成し、
前記第１の導電層に接するように、導電性材料を含む組成物を選択的に吐出して、第２の導電層を形成し、
前記第２の導電層と接しない前記第１の導電層を絶縁化することを特徴とする配線基板の作製方法。 Forming an insulating layer on the substrate;
Wherein in contact with the insulating layer to form a first conductive layer,
A composition containing a conductive material is selectively discharged so as to be in contact with the first conductive layer to form a second conductive layer;
A method for manufacturing a wiring board, wherein the first conductive layer not in contact with the second conductive layer is insulated. 基板上に絶縁層を形成し、
前記絶縁層に接するように第１の導電層を形成し、
前記第１の導電層に接するように、導電性材料を含む組成物を選択的に吐出して、第２の導電層を形成し、
前記第２の導電層と接しない前記第１の導電層をエッチングすることを特徴とする配線基板の作製方法。 Forming an insulating layer on the substrate;
Wherein in contact with the insulating layer to form a first conductive layer,
A composition containing a conductive material is selectively discharged so as to be in contact with the first conductive layer to form a second conductive layer;
A method for manufacturing a wiring board, comprising: etching the first conductive layer that is not in contact with the second conductive layer. 基板上に開口部が設けられた絶縁層を形成し、
前記絶縁層に接するように第１の導電層を形成し、
前記開口部を充填するように、導電性材料を含む組成物を選択的に吐出して、第２の導電層を形成し、
前記第２の導電層と接しない前記第１の導電層を絶縁化することを特徴とする配線基板の作製方法。 Forming an insulating layer with an opening on the substrate;
Wherein in contact with the insulating layer to form a first conductive layer,
A composition containing a conductive material is selectively discharged so as to fill the opening to form a second conductive layer;
A method for manufacturing a wiring board, wherein the first conductive layer not in contact with the second conductive layer is insulated. 基板上に開口部が設けられた絶縁層を形成し、
前記絶縁層に接するように第１の導電層を形成し、
前記開口部を充填するように、導電性材料を含む組成物を選択的に吐出して、第２の導電層を形成し、
前記第２の導電層と接しない前記第１の導電層をエッチングすることを特徴とする配線基板の作製方法。 Forming an insulating layer with an opening on the substrate;
Wherein in contact with the insulating layer to form a first conductive layer,
A composition containing a conductive material is selectively discharged so as to fill the opening to form a second conductive layer;
A method for manufacturing a wiring board, comprising: etching the first conductive layer that is not in contact with the second conductive layer. 請求項１または２において、前記絶縁層を、珪素の酸化物材料又は窒化物材料で形成することを特徴とする配線基板の作製方法。 According to claim 1 or 2, wherein an insulating layer, a method for manufacturing a wiring board, which comprises an oxide or nitride material of silicon. 請求項３または４において、前記絶縁層を、有機材料又は珪素と酸素との結合で骨格構造が形成された材料で形成することを特徴とする配線基板の作製方法。 According to claim 3 or 4, the method for manufacturing a wiring substrate on which the insulating layer, and forming a material skeleton structure is formed by the bond of an organic material or silicon and oxygen. 請求項３または４において、前記絶縁層を、１００ｎｍ〜２μｍの厚さで形成することを特徴とする配線基板の作製方法。 According to claim 3 or 4, wherein an insulating layer, a method for manufacturing a wiring substrate, characterized by a thickness of 100Nm～2myuemu. 請求項１または３において、前記第２の導電層と接しない前記第１の導電層を自然酸化により絶縁化することを特徴とする配線基板の作製方法。4. The method for manufacturing a wiring board according to claim 1, wherein the first conductive layer that is not in contact with the second conductive layer is insulated by natural oxidation. 請求項１乃至８のいずれか一において、前記第１の導電層を、０．０１〜１０ｎｍの厚さで形成することを特徴とする配線基板の作製方法。 In any one of claims 1 to 8, wherein the first conductive layer, a method for manufacturing a wiring substrate, characterized by a thickness of 0.01 to 10. 請求項１乃至９のいずれか一において、前記第１の導電層を、スパッタリング法、蒸着法、ディップ法又はスピンコート法で形成することを特徴とする配線基板の作製方法。 In any one of claims 1 to 9, wherein the first conductive layer, a sputtering method, an evaporation method, a method for manufacturing a wiring substrate, and forming a dip or spin coating. 請求項１乃至１０のいずれか一において、前記第１の導電層を、高融点金属を用いて形成することを特徴とする配線基板の作製方法。The method for manufacturing a wiring board according to claim 1, wherein the first conductive layer is formed using a refractory metal. 請求項１乃至１０のいずれか一において、前記第１の導電層を、チタン、タングステン、クロム、アルミニウム、タンタル、ニッケル、ジルコニウム、ハフニウム、バナジウム、イリジウム、ニオブ、鉛、白金、モリブデン、コバルト又はロジウムを用いて形成することを特徴とする配線基板の作製方法。 In any one of claims 1 to 10, wherein the first conductive layer, titanium, tungsten, chromium, aluminum, tantalum, nickel, zirconium, hafnium, vanadium, iridium, niobium, lead, platinum, molybdenum, cobalt or rhodium the method for manufacturing a wiring board and forming with. 請求項１乃至１２のいずれか一において、前記導電性材料は、銀、金、銅又はインジウム錫酸化物であることを特徴とする配線基板の作製方法。
In any one of claims 1 to 12, wherein the conductive material is silver, gold, a method for manufacturing a wiring substrate, which is a copper or indium tin oxide.
JP2004289726A 2003-10-02 2004-10-01 Wiring board manufacturing method Expired - Fee Related JP4597627B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004289726A JP4597627B2 (en) 2003-10-02 2004-10-01 Wiring board manufacturing method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003344257 2003-10-02
JP2004289726A JP4597627B2 (en) 2003-10-02 2004-10-01 Wiring board manufacturing method

Publications (3)

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JP2005129922A JP2005129922A (en) 2005-05-19
JP2005129922A5 true JP2005129922A5 (en) 2007-11-15
JP4597627B2 JP4597627B2 (en) 2010-12-15

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JP2004289726A Expired - Fee Related JP4597627B2 (en) 2003-10-02 2004-10-01 Wiring board manufacturing method

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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4572814B2 (en) 2005-11-16 2010-11-04 セイコーエプソン株式会社 Active matrix substrate, manufacturing method thereof, electro-optical device, and electronic apparatus
US8293121B2 (en) 2006-09-27 2012-10-23 Samsung Electro-Mechanics Co., Ltd. Method for forming fine wiring
JP2012109581A (en) * 2011-12-19 2012-06-07 Mitsubishi Electric Corp Semiconductor manufacturing method and semiconductor device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06236880A (en) * 1992-12-14 1994-08-23 Oki Electric Ind Co Ltd Forming method of metal wiring
JP2697649B2 (en) * 1994-12-28 1998-01-14 日本電気株式会社 Semiconductor device and manufacturing method thereof
JP4564113B2 (en) * 1998-11-30 2010-10-20 株式会社東芝 Fine particle film forming method
JP2002359347A (en) * 2001-03-28 2002-12-13 Seiko Epson Corp Semiconductor device, its manufacturing method, circuit board, and electronic apparatus

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