JP2005129897A - 半導体装置およびその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 272
- 238000004519 manufacturing process Methods 0.000 title claims description 29
- 239000012790 adhesive layer Substances 0.000 claims abstract description 154
- 239000000155 melt Substances 0.000 claims abstract description 17
- 238000010030 laminating Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims description 35
- 230000015572 biosynthetic process Effects 0.000 claims description 34
- 238000000034 method Methods 0.000 claims description 32
- 239000000463 material Substances 0.000 claims description 10
- 238000007789 sealing Methods 0.000 claims description 5
- 239000000853 adhesive Substances 0.000 description 38
- 230000001070 adhesive effect Effects 0.000 description 38
- 239000010410 layer Substances 0.000 description 34
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 16
- 239000007788 liquid Substances 0.000 description 11
- 229920001342 Bakelite® Polymers 0.000 description 7
- 229920002799 BoPET Polymers 0.000 description 6
- 239000004637 bakelite Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 239000003566 sealing material Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- ORQBXQOJMQIAOY-UHFFFAOYSA-N nobelium Chemical compound [No] ORQBXQOJMQIAOY-UHFFFAOYSA-N 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000002313 adhesive film Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 229920005992 thermoplastic resin Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
Abstract
【解決手段】 半導体装置100は、インターポーザー18上に、素子形成面にセンターパッド23が形成された第一の接着層付き半導体素子16をフェイスアップ実装する工程と、センターパッド23と第一の接着層付き半導体素子16外部の所定箇所とをボンディングワイヤ20で接続する工程と、第一の接着層付き半導体素子16上に、第二の接着層付き半導体素子106を積層する工程と、を含む。第二の接着層付き半導体素子106を積層する工程において、接着層104は、溶融粘度が0.07pa・s以上30pa・s以下となる条件で、第一の接着層付き半導体素子16の素子形成面上に配置される。
【選択図】 図1
Description
本実施の形態において、第一の接着層付き半導体素子16および第二の接着層付き半導体素子106を準備し、第一の接着層付き半導体素子16の上に第二の接着層付き半導体素子106を積層することにより、半導体装置100を製造する。第一の接着層付き半導体素子16および第二の接着層付き半導体素子106の製造手順については後述する。
図5は、第二の接着層付き半導体素子106の製造手順の他の例の一部を示す工程断面図である。
まず、第二の接着層付き半導体素子(106)を以下のようにして製造した。
半導体ウェハ(厚さ約200μm)の素子形成面の裏面全面にステンシル印刷により、液状接着剤(CRP−X4291、住友ベークライト株式会社製)を塗布した。この後、123℃で1時間乾燥することにより、液状接着剤をBステージ化させて接着層を形成した。
それぞれの素子の中心線上に複数の入出力端子が配置された複数の素子が形成された半導体ウェハ(厚さ約200μm)の素子形成面の反対面全面にロールラミネータにより、厚さ75μmのダイボンド用フィルム(DF−402、日立化成工業株式会社製)を貼り付けた。次に、ダイシング用ブレードにより第一の接着層付き半導体素子(7mm×8mm)を個片化した。
まず、PETフィルム上にバーコーターにて液状接着剤(CRP−X4291、住友ベークライト株式会社製)を塗布した。この後、80℃で15分間、次いで120℃で1時間乾燥することにより、液状接着剤層の厚みが149μmであるドライフィルムを得た。
(1) 入出力用端子が半導体素子中央部に一列に配置されている第1の半導体素子(以後センターパッド素子と呼称)上に、予めその裏面に接着剤が供給されている第2の半導体素子(以後積層素子と呼称)を積層し、一つの半導体パッケージに収納する構造とし、センターパッド素子がワイヤボンディングによる金線を介して半導体パッケージ外部と接続することを特徴とする半導体装置の製造方法に関し、積層素子マウント時の接着剤の溶融粘度が30pa・s以下、0.07pa・s以上であることを特徴とする半導体装置の製造方法、
(2) 予め供給される接着剤の厚みが(1)記載のセンターパッド素子上の金線のセンターパッド素子表面からの高さの95%以上300%以下であり、積層素子を積層する際に接着剤がセンターパッド素子上の金線を包み込みつつ固定するとともにセンターパッド素子と積層素子とを接着する半導体装置の製造方法、
(3) (1)記載の金線のセンターパッド素子表面からの高さが25μm以上250μm以下であることを特徴とする半導体装置の製造方法、
(4) (1)から(3)のいずれかに記載の製造方法により製造された半導体装置。
11 半導体基板
12 接着層
16 第一の接着層付き半導体素子
18 インターポーザー
20 ボンディングワイヤ
21 ボンディングワイヤ
23 センターパッド
22 封止材
101 半導体基板
104 接着層
104a 接着剤
106 第二の接着層付き半導体素子
120 ステンシル
122 スキージー
Claims (8)
- 半導体素子上に、接着層を介して部材が積層された半導体装置を製造する方法であって、
基材上に、素子形成面にセンターパッドが形成された前記半導体素子をフェイスアップ実装する工程と、
前記センターパッドと前記半導体素子外部の所定箇所とをボンディングワイヤで接続する工程と、
前記半導体素子上に、前記接着層および前記部材を積層する工程と、
を含み、
前記接着層および前記部材を積層する工程において、前記接着層は、溶融粘度が0.07pa・s以上30pa・s以下となる条件で、前記半導体素子の素子形成面上に配置されることを特徴とする半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記部材の裏面に前記接着層を形成する工程をさらに含み、
前記接着層および前記部材を積層する工程において、前記接着層が裏面に形成された前記部材を、前記半導体素子の素子形成面上に配置することを特徴とする半導体装置の製造方法。 - 請求項1または2に記載の半導体装置の製造方法において、
前記接着層および前記部材を積層する工程において、前記接着層は、前記ボンディングワイヤを封止することを特徴とする半導体装置の製造方法。 - 基材と、
素子形成面にセンターパッドが設けられ、前記基材上にフェイスアップ実装された半導体素子と、
前記半導体素子外部の所定箇所と前記センターパッドとを接続するボンディングワイヤと、
前記半導体素子上に配置された部材と、
前記半導体素子と前記部材との間に設けられ、前記半導体素子と前記部材とを接着するとともに、前記ボンディングワイヤが前記半導体素子の前記素子形成面から離間して位置するように、当該ボンディングワイヤを封止する接着層と、
を含むことを特徴とする半導体装置。 - 請求項4に記載の半導体装置において、
前記半導体素子は、前記素子形成面の中央に一列に配置された複数のセンターパッドを含み、
前記半導体装置は、前記複数のセンターパッドと、前記半導体素子外部の複数の所定箇所とをそれぞれ接続するとともに、前記半導体素子の素子形成面の一辺の縁部上を通過するように構成された複数のボンディングワイヤをさらに含み、
前記接着層は、前記複数のボンディングワイヤ同士が接触しないように、前記複数のボンディングワイヤを封止することを特徴とする半導体装置。 - 請求項4または5に記載の半導体装置において、
前記ボンディングワイヤの前記素子形成面からの高さが、25μm以上250μm以下であることを特徴とする半導体装置。 - 請求項4乃至6いずれかに記載の半導体装置において、
前記接着層の厚さが、前記ボンディングワイヤの前記素子形成面からの高さの95%以上300%以下であることを特徴とする半導体装置。 - 請求項4乃至7いずれかに記載の半導体装置において、
前記半導体素子外部の所定箇所は、前記基材上の箇所であることを特徴とする半導体装置。
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JP2009126980A (ja) * | 2007-11-26 | 2009-06-11 | Sumitomo Bakelite Co Ltd | 液状封止樹脂組成物、半導体装置および半導体装置の製造方法 |
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JP2009126980A (ja) * | 2007-11-26 | 2009-06-11 | Sumitomo Bakelite Co Ltd | 液状封止樹脂組成物、半導体装置および半導体装置の製造方法 |
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