JP2005115657A - General purpose external interface - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a general purpose external interface which can connect an arbitrary external LSI circuit versatilely without incurring increase of circuit space or a CPU load. <P>SOLUTION: This is a general purpose external interface which is carried in a first semiconductor integrated circuit and connects the first semiconductor integrated circuit and a second semiconductor integrated circuit. It is equipped with; an internal bus interface which performs exchange between internal bus of the first semiconductor integrated circuit; an external bus interface which performs exchange between the external bus connecting the first semiconductor integrated circuit and the second semiconductor integrated circuit; a memory which stores an operation pattern of the external bus interface corresponding to an operation mode of the general purpose external interface; a mode register which stores an address of the memory in which the operation pattern of the external bus interface corresponding to a given command; and a sequencer which accesses the memory based on the address of the memory supplied from the mode register corresponding to the command. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a general-purpose external interface that is mounted on a semiconductor integrated circuit and connects the semiconductor integrated circuit to an arbitrary external semiconductor integrated circuit.

  Conventionally, when developing a semiconductor integrated circuit (hereinafter referred to as an LSI), a dedicated external interface may be designed and mounted in accordance with an LSI connected to the outside (hereinafter referred to as an external LSI). Here, the external LSI is various LSIs including a memory, a CPU (Central Processing Unit), an ASIC (Application Specific IC), and the like.

  FIG. 5 is a schematic diagram illustrating an example of an internal configuration of a conventional LSI. As shown in the figure, the LSI 60 includes a CPU 62, a RAM (Random Access Memory) 64, a ROM (Read Only Memory) 66, a timer 68, an interrupt controller 70, a general-purpose I / O (input / output) 72, an external I / F. (Interface) 74 and other internal circuits are provided, and these internal circuits are connected to each other via an internal bus 76.

  The LSI 60 and the external LSI 78 are connected to each other via the external bus 80. In this case, the LSI 60 and the external bus 80 are connected to each other via the external I / F 74, and exchange is performed between the internal bus 76 of the LSI 60 and the external bus 80.

  Further, when a plurality of external LSIs to be connected are assumed, it is often performed to design an external I / F corresponding to each external LSI and mount a function of switching according to the mode. For example, the LSI 82 shown in FIG. 6 is a case where there are two external LSIs to be connected, and includes an external I / F 1 and an external I / F 2 respectively corresponding to the two external LSIs. These two external I / F1 and external I / F2 are switched and used by a multiplexer (MUX) 84 in accordance with a mode switching signal.

  However, as described above, in the configuration in which a plurality of external I / Fs are switched and used depending on the mode, there is a problem that the circuit area overhead increases, which increases the chip area and increases the unit price.

  In addition to the above example, as shown in FIGS. 5 and 6 as general-purpose I / O 72, a general-purpose port is provided in the LSI, and an external bus that connects the LSI and the external LSI is controlled by the CPU. A signal for controlling is also generated.

  However, it is almost impossible to control the general-purpose port according to the external LSI and switch the signal at high speed with the processing capability of the CPU. There was a problem of becoming. In addition, since the signals to be generated have increased in complexity due to the diversification of interfaces, there is a problem that control of general-purpose ports by the CPU becomes increasingly difficult.

  An object of the present invention is to provide a general-purpose external interface that can solve any problems based on the prior art and can connect any external LSI for general-purpose without causing an increase in circuit area or CPU load. is there.

In order to achieve the above object, the present invention is a general-purpose external interface mounted on a first semiconductor integrated circuit for connecting the first semiconductor integrated circuit and the second semiconductor integrated circuit,
Exchanges between an internal bus interface that exchanges data with the internal bus of the first semiconductor integrated circuit and an external bus that connects the first semiconductor integrated circuit and the second semiconductor integrated circuit. An external bus interface, a memory for storing an operation pattern of the external bus interface corresponding to an operation mode of the general-purpose external interface, an internal circuit of the first semiconductor integrated circuit, and the internal bus and the internal bus interface A mode register for storing an address of the memory in which an operation pattern of the external bus interface corresponding to the command given is stored, and an address of the memory supplied from the mode register corresponding to the command A sequencer for accessing the memory; And it provides a generic external interface, characterized in that to obtain.

  Here, it is preferable that the command further includes a command given from the outside of the first semiconductor integrated circuit through the external bus and the external bus interface. Further, it is preferable that the command further includes a command directly given from at least one of an internal circuit of the first semiconductor integrated circuit and an outside of the first semiconductor integrated circuit.

  The memory is preferably used as an internal memory accessed by the internal circuit of the first semiconductor integrated circuit through the internal bus, the internal bus interface, and the sequencer.

  The general-purpose external interface of the present invention is suitable for various external LSIs by appropriately rewriting the address set in the mode register and the operation pattern stored in the memory in response to various commands corresponding to the external LSI. Can respond. In addition, the general-purpose external interface has a smaller circuit scale and a lower unit price than when a plurality of external interfaces are used. Further, since control by the CPU is almost unnecessary, there is an advantage that the load on the CPU does not become heavy unlike a general-purpose port.

  Hereinafter, the general-purpose external interface of the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.

  FIG. 1 is a schematic configuration diagram of an embodiment of a general-purpose external interface according to the present invention. A general-purpose external interface (hereinafter referred to as a general-purpose external I / F) 10 shown in FIG. 1 is an interface circuit that is mounted on the LSI 22 and connects the LSI 22 and an optional external LSI 24. An internal bus I / F 12, an external bus interface (hereinafter referred to as an external bus I / F) 14, a memory 16, a mode register 18, and a sequencer 20 are provided.

  The LSI 22 and the external LSI 24 are connected to each other via an external bus. In this case, the LSI 22 and the external bus are connected to each other via the external bus I / F 14 of the general-purpose external I / F 10. The LSI 22 on which the general-purpose external I / F 10 is mounted is not limited in any way. For example, as shown in FIG. 5, a CPU 62, a RAM 64, a ROM 66, a timer 68, an interrupt controller 70, a general-purpose I / O 72, etc. These internal circuits are connected to each other via an internal bus 76.

  The general-purpose external I / F 10 is set to operate in an operation mode corresponding to the connected external LSI 24. For example, when the external LSI 24 is an SRAM (static RAM), the general-purpose external I / F 10 is set to function as an external interface dedicated to SRAM. Further, when the external LSI 24 is a DRAM (dynamic RAM), it functions as an external interface dedicated to DRAM, and when it is a CPU, it is set to function as an external interface dedicated to CPU.

  Hereinafter, each component of the general-purpose external I / F 10 will be described.

  The internal bus I / F 12 performs exchanges between the general-purpose external I / F 10 and the internal bus. The internal bus I / F 12 is interconnected with the internal bus, and its output signal is input to the mode register 18, the sequencer 20, and the external bus I / F 14.

  The external bus I / F 14 performs exchanges between the general-purpose external I / F 10 and the external bus. The external bus I / F 14 is connected to the external bus, and the output signal is input to the internal bus I / F 12 and the sequencer 20.

  The memory 16 stores an operation pattern of the external bus I / F 14 corresponding to the operation mode of the general-purpose external I / F 10. The memory 16 is mutually connected to the sequencer 20, and its output signal, that is, an operation pattern is input to the external bus I / F 14. The memory 16 is used as a general-purpose internal memory that is accessed by the internal circuit of the LSI 22 via the internal bus, the internal bus I / F 12 and the sequencer 20 when the general-purpose external I / F 10 is not in use. It is also possible.

  The mode register 18 sets (determines) the operation mode of the general-purpose external I / F 10, and the mode register 18 stores the operation pattern of the external bus I / F 14 corresponding to a given command. The address is stored. The output signal of the internal bus I / F 12 is input to the mode register 18, and the output signal, that is, the address, is input to the sequencer 20.

  The sequencer 20 accesses the memory 16 based on the address of the memory 16 supplied from the mode register 18 in response to a given command.

  Note that the commands are various commands including read, write, and the like for the external LSI 24. The command is given from the internal circuit of the LSI 22 via the internal bus and the internal bus I / F 12, and is also given from the outside of the LSI 22 via the external bus and the external bus I / F 14. It is also possible to give directly from outside the LSI 22. When a command given from the internal circuit of the LSI 22 and a command given from the outside of the LSI 22 compete, it is preferable to give priority to the command given from the outside of the LSI 22.

  Next, the operation when the general-purpose external I / F 10 is used will be described with reference to the flowchart shown in FIG.

  When the power is turned on (S1), various operation patterns corresponding to the operation mode of the general-purpose external I / F 10 are written in the memory 16 (S2). The operation pattern data written in the memory 16 is read from, for example, a ROM mounted on the LSI 22 or a ROM connected to the outside of the LSI 22 and is transmitted via the internal bus and the internal bus I / F 12 or the external bus. And given to the sequencer 20 via the external bus I / F 14. Then, the sequencer 20 sequentially writes various given operation patterns to predetermined addresses in the memory 16.

  Subsequently, the address of the memory 16 storing the operation pattern of the external bus I / F 14 corresponding to various commands is set in the mode register 18 (S3). Similarly, address data set in the mode register 18 is read from a ROM mounted on the LSI 22, a ROM connected to the outside of the LSI 22, or the like via the internal bus and the internal bus I / F 12, or Addresses corresponding to various commands are sequentially written to the mode register 18 via the external bus and the external bus I / F 14.

  As described above, when the writing of the operation pattern to the memory 16 and the setting of the address to the mode register 18 are completed, the general-purpose external I / F 10 functions in the same manner as a conventional external interface dedicated to the external LSI 24.

  For example, when a command is given from the internal circuit of the LSI 22 via the internal bus and the internal bus I / F 12 (S4), the address of the memory 16 corresponding to this command is output from the mode register 18. The sequencer 20 accesses the memory 16 based on the address of the memory 16 supplied from the mode register 18, and the operation pattern stored at the address corresponding to the command is output from the memory 16. Accordingly, the external bus I / F 14 operates according to the operation pattern supplied from the memory 16.

  The general-purpose external I / F 10 is used for various external LSIs 24 by appropriately rewriting addresses set in the mode register 18 and operation patterns stored in the memory 16 in response to various commands corresponding to the external LSIs 24. It can correspond to. In addition, the general-purpose external I / F 10 has a smaller circuit scale and a lower unit price than when a plurality of external I / Fs are used. Further, since control by the CPU is almost unnecessary, there is an advantage that the load on the CPU does not become heavy unlike a general-purpose port.

  For example, when a memory device is connected as the external LSI 24, whether it is an SRAM or a DRAM, these memory devices can be connected universally without providing a dedicated external I / F. In addition, since the general-purpose external I / F 10 can be connected to any external LSI 24 in a general-purpose manner, for example, the external LSI 24 is connected to the external LSI 24 whose external bus specifications are not fixed after the specifications are fixed. It is possible to use it.

  Next, a specific example of the general-purpose external interface of the present invention will be described.

  FIG. 3 is a schematic configuration diagram of an embodiment of a general-purpose external interface to which the present invention is applied. This figure shows an internal configuration of a general-purpose external I / F 30 when an SDRAM (synchronous dynamic RAM) is connected as an external LSI. The AHB interface 32, an external bus I / F 34, a memory 36, And a sequencer 40.

  The AHB interface 32 exchanges between the general-purpose external I / F 30 and an AHB bus (Advanced High-Performance Bus) which is an internal bus of an arm processor manufactured by Arm Corp. in the UK. The AHB interface 32 is connected to the AHB bus, and the control signal terminal of the AHB interface 32 is connected to the sequencer 40.

  The AHB interface 32 includes a mode register function in addition to the function of the internal bus I / F. An interrupt input output from the timer is input to the mode register portion in the AHB interface 32. The address is set in the mode register by setting the register located in the address space assigned to the AHB interface 32.

  The external bus I / F 34 performs communication between the general-purpose external I / F 30 and the external bus, and includes four flip-flops 42, 44, 46, and 48 and a three-state buffer 50. In order to avoid the complexity of the drawing, only four flip-flops are conceptually shown, but in actuality, it is assumed that the number of flip-flops corresponding to the number of bits of each signal is provided.

  An output signal from the address terminal of the AHB interface 32 is input to the data input terminal D of the flip-flop 42, and an address strobe supplied from the memory 36 is input to the enable input terminal EN. The data output terminal of the flip-flop 42 is connected to the output terminal MA connected to the external bus.

  An output signal from the data output terminal of the AHB interface 32 is input to the data input terminal D of the flip-flop 44, and an output data strobe supplied from the memory 36 is input to the enable input terminal EN. A signal DQO is output from the data output terminal of the flip-flop 44.

  A signal DQI supplied via a data input / output terminal DQ connected to the external bus is input to the data input terminal D of the flip-flop 46, and the enable input terminal EN is supplied from the memory 36. Input data strobe is input. The signal output from the data output terminal of the flip-flop 46 is input to the data input terminal of the AHB interface 32.

  The signal DQO output from the data output terminal of the flip-flop 44 is input to the 3-state buffer, and the output terminal of the 3-state buffer 50 is connected to the data input / output terminal DQ. The data input terminal D of the flip-flop 46 is also connected to the data input / output terminal DQ. The output data enable supplied from the memory 36 is input to the enable input terminal of the three-state buffer 50.

  Further, signals RAS, CAS, CS, WE, UDQM, and LDQM supplied from the memory 36 are input to the data input terminal of the flip-flop 48, and the output terminal of the flip-flop 48 is an output terminal connected to the external bus. It is connected to RAS, CAS, CS, WE, UDQM and LDQM.

  Subsequently, an output signal from the sequencer 40 is input to the memory 36. An output signal from the memory 36, that is, an operation pattern is input to the sequencer 40 and the four flip-flops 42, 44, 46 and 48. Details of the operation pattern output from the memory 36 will be described later.

  The sequencer 40 receives a control information bit output from the memory 36 and an interrupt input output from the timer. As described above, the sequencer 40 and the control signal terminal of the AHB interface 32 are connected to each other. An output signal from the sequencer 40 is input to the memory 36. The interrupt input is used as a command for instructing an operation mode corresponding to the refresh cycle of the SDRAM.

  A clock is commonly input to clock input terminals of the memory 36, the sequencer 40, and the flip-flops 42, 44, 46, and 48. That is, the memory 36, the sequencer 40, and the flip-flops 42, 44, 46, and 48 operate in synchronization with the clock.

  Next, the operation pattern stored in the memory 36 will be described.

  FIG. 4 is a conceptual diagram of an embodiment showing an operation pattern stored in a memory used in the general-purpose external interface shown in FIG. The operation pattern shown in the figure is for operating the external bus I / F 34 in an operation mode corresponding to the SDRAM, and is output corresponding to the address of the memory 36 output from the mode register (AHB interface 32). This is one operation pattern. This operation pattern is configured by a signal control unit on the MSB side and a control information unit on the LSB side.

  The signal control unit is used as a signal for controlling the operation of the SDRAM and a signal for controlling the timing for buffering the address signal and the data signal of the SDRAM. Signal LDQM, UDQM, WE, CS, CAS, RAS, input data strobe, output data enable, output data strobe, and address strobe shown in FIG. 3 are allocated to each bit of the signal control unit in order from the MSB side. . Each bit of the signal control unit is supplied to the external bus I / F 34.

  An output signal from the address terminal of the AHB interface 32 is held in the flip-flop 42 in synchronization with the clock, and is output from the output terminal MA while the address strobe is ‘1’. Similarly, the output signal from the data output terminal of the AHB interface 32 is held in the flip-flop 44 in synchronization with the clock signal, and is output as the signal DQO when the output data strobe is “1”, and the output data enable is enabled. Data is output from the data input / output terminal DQ to the external bus during the period “1”.

  The signal DQI supplied from the external bus via the data input / output terminal DQ is held in the flip-flop 46 in synchronization with the clock. The input data strobe is supplied to the data input terminal of the AHB interface 32 during the period “1”. The signals LDQM, UDQM, WE, CS, CAS, and RAS input from the memory 36 to the flip-flop 48 are held in the flip-flop 48 in synchronization with the clock, and at the same time, the output terminals LDQM, UDQM, WE, Output from CS, CAS, RAS to external bus.

  The control information part is used as a control information bit including control of the number of loops and command end information. Each bit of the control information part is supplied to the sequencer 40.

  The control of the number of loops is a bit for setting the number of times of reading out the same operation pattern from the same address in the memory 36. For example, when “1” is set as the number of loops, the operation pattern is read only once from the same address in the memory 36 in synchronization with the clock under the control of the sequencer 40. When “5” is set as the number of loops, the same operation pattern is read five times continuously from the same address of the memory 36 every clock in synchronization with the clock.

  The command end information is a bit for setting whether to end or continue a series of processes related to the command. For example, when the command end information is “0”, the operation pattern is read from the next address of the memory 36 in synchronization with the clock under the control of the sequencer 40, and the processing is continued using the next operation pattern. The On the other hand, when the command end information is “1”, the next operation pattern is not read, and a series of processes corresponding to the command is ended.

  Therefore, in this general-purpose external I / F, by combining a plurality of operation patterns stored in the memory 36 corresponding to the command as appropriate, the operation pattern corresponding to this command is a complex operation pattern. Can also be generated.

  Subsequently, the operation of the general-purpose external I / F 30 will be described. It is assumed that an operation pattern corresponding to the SDRAM is stored in the memory 36 in advance, and an address is also set in the mode register (that is, the AHB interface 32).

  In this general-purpose external I / F 30, for example, when a command is given from an internal circuit of the LSI via the internal bus and the AHB interface 32, the address of the memory 36 corresponding to this command is a control signal of the AHB interface (mode register) 32. The signal is output from the terminal and input to the sequencer 40. In the sequencer 40, the address of the memory 36 supplied from the AHB interface 32 is accessed in synchronization with the clock, and the operation pattern corresponding to this command is read from the memory 36.

  Of the operation patterns read from the memory 36, signals LDQM, LUQM, WE, CS, CAS, RAS, input data strobe, output data enable, output data strobe and address strobe are supplied to the external bus I / F 34. Processed as described above. Of the operation patterns read from the memory 36, control information bits are supplied to the sequencer 40. In the sequencer 40, a series of operations corresponding to the command are controlled as described above with reference to the control of the loop count and the command end information which are control information bits.

  When the command end information in the control information bit becomes “1”, the end signal is supplied from the sequencer 40 to the control signal terminal of the AHB interface 32. When the AHB interface 32 receives the end signal, it outputs a ready signal to the internal circuit of the LSI, thereby ending a series of processing corresponding to the command.

  In the case of SDRAM, a refresh operation is necessary. The refresh operation is processed by a mode register in the AHB interface 32 and an interrupt input input to the sequencer 40 directly from the timer. The refresh operation can also be realized by giving an interrupt input as one of the commands similarly to the above operation. That is, it can be similarly realized by writing an operation pattern corresponding to the refresh operation in the memory 36 and setting address information corresponding to this in the mode register (AHB interface 32).

The present invention is basically as described above.
The general external interface of the present invention has been described above in detail. However, the present invention is not limited to the above-described embodiment, and various modifications and changes may be made without departing from the spirit of the present invention. is there.

It is the structure schematic of the general purpose external interface of this invention. It is a flowchart showing operation | movement of the general purpose external interface of this invention. 1 is a schematic configuration diagram of an embodiment of a general-purpose external interface to which the present invention is applied. It is a conceptual diagram of one Embodiment showing the operation | movement pattern memorize | stored in the memory used with the general purpose external interface shown in FIG. It is the schematic of an example showing the internal structure of the conventional LSI. It is the schematic of another example showing the internal structure of the conventional LSI.

Explanation of symbols

10, 30 General-purpose external interface 12 Internal bus interface 14, 34 External bus interface 16, 36 Memory 18 Mode register 20, 40 Sequencer 22, 24, 60, 78, 82 LSI
32 AHB interface 42, 44, 46, 48 Flip-flop 50 3-state buffer 62 CPU
64 RAM
66 ROM
68 Timer 70 Interrupt controller 72 General-purpose I / O
74 External I / F
76 Internal bus 80 External bus 84 Multiplexer

Claims (4)

A general-purpose external interface mounted on the first semiconductor integrated circuit for connecting the first semiconductor integrated circuit and the second semiconductor integrated circuit;
Exchanges between an internal bus interface that exchanges data with the internal bus of the first semiconductor integrated circuit and an external bus that connects the first semiconductor integrated circuit and the second semiconductor integrated circuit. An external bus interface, a memory for storing an operation pattern of the external bus interface corresponding to an operation mode of the general-purpose external interface, an internal circuit of the first semiconductor integrated circuit, and the internal bus and the internal bus interface A mode register for storing an address of the memory in which an operation pattern of the external bus interface corresponding to the command given is stored, and an address of the memory supplied from the mode register corresponding to the command A sequencer for accessing the memory; General purpose external interface, characterized in that to obtain.   The general-purpose external interface according to claim 1, wherein the command further includes a command given from outside the first semiconductor integrated circuit via the external bus and the external bus interface.   The general-purpose external interface according to claim 1, wherein the command further includes a command directly given from at least one of an internal circuit of the first semiconductor integrated circuit and an outside of the first semiconductor integrated circuit.   4. The memory according to claim 1, wherein the memory is used as an internal memory accessed by the internal circuit of the first semiconductor integrated circuit via the internal bus, the internal bus interface, and the sequencer. General-purpose external interface.

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