KR20030023337A - Test mode entry method of semiconductor memory device and disposition of test mode line using it - Google Patents

Abstract

PURPOSE: A test mode entry method of a semiconductor memory device and a layout of a test mode signal line by using the same are provided to freely arrange the layout of the test mode decoding circuit without being restricted by the place adjacent to the address pads. CONSTITUTION: A test mode entry method of a semiconductor memory device for becoming an entry as a test mode with synchronizing a mode register setting(MRS) to assign an initial value during the power-up synchronized with a clock with the mode register setting when a predetermined address value are applied at least two times includes the steps of setting the test mode register setting by synchronizing a pair of specific address values inputted from a plurality of address pads(100) with the predetermined address value and activating the test mode operation by combining each of the pair of specific address values during the test mode entry process.

Description

TEST MODE ENTRY METHOD OF SEMICONDUCTOR MEMORY DEVICE AND DISPOSITION OF TEST MODE LINE USING IT}

The present invention relates to a test mode entry method of a semiconductor memory device and a test mode signal line arrangement using the same, and more particularly, testing through a test mode after chip fabrication of a synchronous DRAM (SDRAM). A semiconductor memory device.

1 shows a test mode entry sequence of the prior art. As shown, on the rising edge of the clock CLK, the command signal CMD, for example, the rasva signal / RAS, the cascade signal / CAS, the chip select bar signal / CS and the write enable bar signal ( / WE) is the 'low' level at the same time mode register settings (hereinafter referred to as MRS) to program data to control the various operating modes of the SDRAM.

In this MRS state, when a specific address, for example, an address value of A7 to A10 is specified, the test mode register setting (hereinafter, referred to as TSR) is performed. When the TSR is executed three times in sequence, the TSET signal is entered while entering the test mode. Occurs. At this time, the test mode TMODE to be entered is determined by decoding a specific address, for example, addresses A0 to A5. Here, the number of test modes that can be selected is 64, which is 2 ⁶ .

Fig. 2 shows the arrangement of the test mode decoding circuit and the signal line in the test mode using the method for entering the test mode.

As shown, a semiconductor device having banks 0 to 3 is provided. An address input pad 10 is disposed between the banks 0 and 1 and an input / output pad 20 is disposed between the banks 2 and 3. A test mode decoding circuit 30 is disposed toward the address input pad 10, and a signal line 40 of a test mode is used to test a peripheral circuit between the banks 0 to 3 from the test mode decoding circuit 30. Is placed. In this case, the reason why the test mode decoding circuit 30 is disposed toward the address input pad 10 is that if the decoding circuit is arranged on the other side, signals from the address input pad 10 must be connected, so that the number of global wirings increases. Because.

However, the area occupied by the global wiring is more important than the area occupied by the transistors of the peripheral circuit as a factor in determining the chip size as the integrated capacity of the memory semiconductor increases. The signal lines 40 from the arranged test mode decoding circuit 30 are concentrated so that the area occupied by the global wiring increases.

Accordingly, an object of the present invention devised to solve the above problems is to determine a test mode with a few decoding addresses, thereby reducing the number of global wirings for the test mode arranged throughout the chip. And the arrangement of the test mode signal line using the same.

1 is a timing diagram for explaining a test mode entry method of a conventional semiconductor memory device.

FIG. 2 is a plan view illustrating signal line arrangement in a test mode using the test mode entry method of FIG. 1; FIG.

3 is a timing diagram for explaining a test mode entry method of the semiconductor memory device of the present invention.

4 is a plan view illustrating a signal line arrangement in a test mode using the test mode entry method of FIG.

Explanation of symbols on the main parts of the drawings

100: address pad

200: input / output pad

300: first test mode decoding circuit

350: address signal line

400: second test mode decoding circuit

500: test mode signal line

The test mode entry method and the test mode signal line arrangement of the semiconductor memory device of the present invention for achieving the above object are synchronized with the mode register setting (MRS) and the mode register setting which specify an initial value at power-up in synchronization with a clock. In the test mode entry method of a semiconductor memory device which is entered into a test mode when a specific address value is applied at least two times, the specific address value is input to two specified address values input from an address pad. And a test mode register setting in synchronization with each other, and activates the test mode by combining the two address values specified at the test mode entry.

In addition, the test mode signal line arrangement using the test mode entry method may include a first decoding circuit receiving two address values adjacent to the address pad, a predetermined interval from the first decoding circuit, and the two address values. And an N-th decoding circuit simultaneously receiving a signal and a signal line accompanying decoded values of the first decoding circuit and the N-th decoding circuit at the test mode entry, respectively, in the semiconductor memory device for testing. Characterized in that the implementation.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

3 is a timing diagram illustrating a test mode entry method of the semiconductor memory device of the present invention, and FIG. 4 is a plan view illustrating an arrangement of test mode signal lines using the test mode entry method of the present invention.

First, as shown in FIG. 3, the command signal CMD, for example, the rasva signal (/ RAS), the cascade signal (/ CAS), the chip select bar signal (/ CS), and the write at the rising edge of the clock CLK. When the enable bar signal / WE is at the 'low' level at the same time, a mode register setting (hereinafter referred to as MRS) for programming data for controlling various operation modes of the SDRAM is performed.

In this MRS state, when a specific address, for example, an address value of A7 to A10 is specified, it becomes a test mode register setting (hereinafter referred to as TSR). When such TSR is executed three times in sequence, it is entered into the test mode. .

Here, the test mode to be entered is determined by decoding the address values of a specific address, for example, A0 and A1. The test mode is performed by synchronizing the address values of the specified A0 and A1 input from the address pad to the clock CLK, respectively. Register setting (hereinafter, TSR) is performed. For each of these TSR commands, a TSET signal is generated for every clock (CLK) indicating that the current external command is a TSR. The address values are combined to activate the operation of the test mode.

For example, if the address value of A0 and A1 is 0, 1 at the first clock, the address value of A0 and A1 is 1, 0 at the second clock, and the address value of A0 and A1 is 0, 0 at the third clock, Upon entry of the mode it activates the operation of the test mode for the specified address value of 011000.

FIG. 4 illustrates an embodiment of a test mode decoding circuit using the test mode entry method of FIG. 3 and arrangement of signal lines in the test mode.

As shown, a semiconductor device having banks 0 to 3 is provided. An address input pad 100 is disposed between the banks 0 and 1, and an input / output pad 200 is disposed between the banks 2 and 3. The first test mode decoding circuit 300 receiving the address values of A0 and A1 is disposed toward the address input pad 100, and has a predetermined interval with the first test mode decoding circuit 300 and the A0 and A1. The second test mode decoding circuit 400 simultaneously receiving the address value of is disposed. Here, in the related art, six address signal lines are used to connect to the test mode decoding circuit. However, since only two address signal lines 350 are used in the present invention, the arrangement of the first and second test mode decoding circuits 300 and 400 may be limited. free.

The signal line 500 of the test mode for testing the peripheral circuits between the banks 0 to 3 through the first and second test mode decoding circuits 300 and 400 is disposed. As shown, the signal lines in the first test mode decoding circuit 300 are placed and tested between banks 0 and 1 and between banks 2 and 3, respectively, and the signal lines in the second test mode decoding circuit 400 are tested. Are tested between bank 0 and bank 2 and between bank 1 and bank 3, respectively. Therefore, the total number of global wirings can be reduced by preventing the concentration of global wiring in the related art.

In the above-described embodiment, the first and second test mode decoding circuits 300 and 400 are disposed, but a plurality of test mode decoding circuits are arranged at regular intervals from the test mode decoding circuit to prevent concentration of global wiring. It may be.

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

According to the test mode entry method of the semiconductor memory device of the present invention and the arrangement of the test mode signal line using the same, the test modes are classified into three hierarchical structures of A0 and A1 address inputs. In comparison, the required number of test mode decoding addresses is smaller. Accordingly, the arrangement of the test mode decoding circuit can be freely arranged without being limited to the vicinity of the address pad.

In addition, since the required test mode decoding circuit can be arranged in each area, there is an effect of reducing the number of global wirings on the address pad side for determining the size of the chip.

Claims (4)

A test mode entry of a semiconductor memory device which is synchronized with a clock and specifies a mode register setting at initial power-up, and enters a test mode when a specific address value is applied at least two times in synchronization with the mode register setting. in the (entry) method, The test mode register setting is performed by synchronizing the two specified address values input from the address pad with the specific address value, respectively, and combining the two specified address values at the test mode entry to perform the operation of the test mode. And a test mode entry method of a semiconductor memory device. The method of claim 1, And said specific address value is set by a combination of four address values from each of said address pads. In the arrangement of test mode signal lines of a semiconductor memory device using the test mode entry method according to claim 1, A first decoding circuit receiving two address values adjacent to the address pad; An N-th decoding circuit having a predetermined interval from the first decoding circuit and simultaneously receiving the two address values; And performing testing by arranging signal lines carrying decoded values of the first decoding circuit and the N-th decoding circuit in the semiconductor memory device at the test mode entry. Layout of test mode signal lines. The method of claim 3, wherein And the N-th decoding circuit is at least one or more decoding circuits having a predetermined interval from each other.