JP2005091316A - Method and device for detecting abnormality for electric circuit - Google Patents

Method and device for detecting abnormality for electric circuit Download PDF

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JP2005091316A
JP2005091316A JP2003328881A JP2003328881A JP2005091316A JP 2005091316 A JP2005091316 A JP 2005091316A JP 2003328881 A JP2003328881 A JP 2003328881A JP 2003328881 A JP2003328881 A JP 2003328881A JP 2005091316 A JP2005091316 A JP 2005091316A
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JP4121923B2 (en
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Hiromi Takada
裕美 高田
Masashi Isoda
昌志 磯田
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Ricoh Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide an abnormality detecting device capable of detecting an abnormality of a plurality of circuits to be inspected with no switching operation or switching means. <P>SOLUTION: An abnormality detecting device 10 comprises a resistance measuring device 13 for measuring electric resistance value of a parallel test circuit 12 where a plurality of test unit circuit parts 16 of the same electric resistance value are connected each other, a judging circuit 18 for judging whether abnormality has occurred at the test unit circuit part 16 based on the resistance value measured with the resistance measuring device, and a display part 19. The judging circuit 18 compares a calculation part 18a for calculating a variation amount of measured resistance values with the resistance measuring device 13, to the calculation result of the calculation part, and to a total tolerance difference α which is a threshold value. When the variation amount is judged to have exceeded that total tolerance difference α, the display part 19 displays that an abnormality has occurred. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

この発明は、電気・電子回路に用いられる複数の部品または回路についての信頼性試験などを同時的に並行して行う方法及び装置に関し、特に、電気的なモニタリングによって異常の発生を検出する異常検出方法及びその装置に関する。   The present invention relates to a method and apparatus for simultaneously performing a reliability test on a plurality of components or circuits used in an electric / electronic circuit in parallel, and in particular, an abnormality detection for detecting the occurrence of an abnormality by electrical monitoring. The present invention relates to a method and an apparatus thereof.

電気・電子回路の検査は、総試験時間短縮のために複数の検査対象回路を同時並行で試験することが多い。信頼性試験など長期にわたる計測が必要な場合は特に顕著である。このように同時的に複数の検査対象がある場合、検査対象に応じた数の計測器、あるいは検査対象と計測器との切替えのための選択手段のいずれかが必要となる。一般的に計測器は高価であるため、検査対象の選択手段を用意する方法が採用されている（例えば、特許文献１及び２参照。）。   In the inspection of electrical / electronic circuits, a plurality of inspection target circuits are often tested simultaneously in order to reduce the total test time. This is particularly noticeable when long-term measurements are required, such as reliability tests. When there are a plurality of inspection objects at the same time, either the number of measuring instruments corresponding to the inspection objects or a selection means for switching between the inspection object and the measuring instrument is required. In general, since measuring instruments are expensive, a method of preparing means for selecting an inspection object is adopted (for example, see Patent Documents 1 and 2).

特許文献１は、図１０に示すように、検査対象回路の抵抗値をモニタリングするための装置の例を示す。検査対象となる各テスト回路１−１〜１−ｎの２つの端子はそれぞれ選択手段２に接続され、該選択手段は抵抗測定器３に接続されている。選択手段２は、コントローラ４の制御下で、抵抗測定器３をテスト回路１−１〜１−ｎに選択的に接続する。従って、選択手段２を設けることで、複数の検査対象回路１−１〜１−ｎを順次切替えてそれぞれの抵抗値を測定することができ、これにより多数の検査対象回路を並行して試験することが可能となる。   Patent Document 1 shows an example of an apparatus for monitoring a resistance value of a circuit to be inspected as shown in FIG. Two terminals of each of the test circuits 1-1 to 1-n to be inspected are connected to the selection unit 2, and the selection unit is connected to the resistance measuring device 3. The selection means 2 selectively connects the resistance measuring device 3 to the test circuits 1-1 to 1-n under the control of the controller 4. Therefore, by providing the selection means 2, it is possible to sequentially switch the plurality of inspection target circuits 1-1 to 1-n and measure the respective resistance values, thereby testing a large number of inspection target circuits in parallel. It becomes possible.

また、特許文献２に記載の装置では、図１１に示すように、各被試験半導体回路１１〜１ｎにそれぞれ抵抗２1〜２n及びスイッチ３1〜３nを直列接続して構成される各単位回路が相互に並列接続されている。この単位回路から成る並列回路には電圧源４と電流計５が接続され、各単位回路の抵抗２1〜２nはそれぞれ独立的に電圧計６に接続されている。各被試験半導体回路１1〜１nの評価時には、電流計５で検出された並列回路の電流が異常値を示すと、単位回路毎における抵抗２1〜２nでの電圧降下が電圧計６で計測され、それぞれの電圧降下と各単位回路毎の抵抗２1〜２nでの電圧降下の正常値とが比較され、この比較結果で異常回路が特定される。この異常回路のスイッチ３1〜３nをオフにした後、引き続き残りの回路のモニタリングが継続される。
特開２００２−１６８９１７号公報 特開２０００−１４７０５９号公報 In the apparatus described in Patent Document 2, as shown in FIG. 11, each of the semiconductor circuits under test 11 to 1n is configured by connecting resistors 2 1 to 2 n and switches 3 1 to 3 n in series. Unit circuits are connected in parallel to each other. A voltage source 4 and an ammeter 5 are connected to the parallel circuit composed of the unit circuits, and the resistors 2 1 to 2 n of each unit circuit are independently connected to the voltmeter 6. At the time of evaluation of each of the semiconductor circuits under test 1 1 to 1 n , if the current of the parallel circuit detected by the ammeter 5 shows an abnormal value, the voltage drop at the resistors 2 1 to 2 n for each unit circuit is changed to the voltmeter 6. The voltage drop is compared with the normal value of the voltage drop at the resistors 2 1 to 2 n for each unit circuit, and the abnormal circuit is specified by the comparison result. After the switches 3 1 to 3 n of the abnormal circuit are turned off, the remaining circuits are continuously monitored.
JP 2002-168917 A JP 2000-147059 A

しかしながら、特許文献１に記載の技術では、１つの計測手段を多数の検査対象回路に選択的に接続するための選択手段が必要となり、自動化のためには選択手段の動作を制御するコントローラが不可欠となる上、制御を受ける選択手段が複雑化し、システム全体が高価にならざるを得ない。   However, the technique described in Patent Document 1 requires a selection means for selectively connecting one measurement means to a large number of circuits to be inspected, and a controller for controlling the operation of the selection means is indispensable for automation. In addition, the selection means to be controlled is complicated, and the entire system has to be expensive.

また、特許文献２に記載の技術では、電圧を計測するための電圧計が単位回路の数分だけ必要か、または１つの電圧計を各抵抗に選択的に接続するための選択手段が必要となるために、システム全体としては高価にならざるを得ない。また自動化のためにスイッチをオフするための自動化回路が必要になる。   Further, in the technique described in Patent Document 2, voltmeters for measuring voltage are required for the number of unit circuits, or selection means for selectively connecting one voltmeter to each resistor is required. Therefore, the whole system must be expensive. Also, an automation circuit for turning off the switch is required for automation.

従って、本発明の目的は、スイッチング操作や切替え手段を用いることなく複数の検査対象回路の異常を検出し得る異常検出方法及び異常検出装置を提供することにある。   Accordingly, an object of the present invention is to provide an abnormality detection method and an abnormality detection apparatus that can detect an abnormality in a plurality of inspection target circuits without using a switching operation or switching means.

請求項１に記載の異常検出方法は、ほぼ等しい電気抵抗値を示す複数の試験単位回路部が互いに接続されてなる並行試験回路の電気抵抗値を測定し、当該測定値に基づいて前記試験単位回路部の異常の発生を検出する方法であって、電気抵抗の測定許容差及び前記試験単位回路部の許容差の和で示される合計許容差αと前記並行試験回路の電気抵抗測定値の変化分とを比較し、前記測定値の変化分が前記合計許容差αを超えると前記試験単位回路部に異常が発生したと判定することを特徴とする、電気回路のための異常検出方法。   The abnormality detection method according to claim 1, wherein an electrical resistance value of a parallel test circuit formed by connecting a plurality of test unit circuit units having substantially the same electrical resistance value is connected to each other, and the test unit is based on the measured value. A method for detecting the occurrence of an abnormality in a circuit unit, wherein a total tolerance α indicated by a sum of a measurement tolerance of electrical resistance and a tolerance of the test unit circuit unit and a change in a measured value of electrical resistance of the parallel test circuit And detecting that an abnormality has occurred in the test unit circuit unit when the change in the measured value exceeds the total tolerance α.

請求項２に記載の異常検出方法は、請求項１に記載の方法において、前記試験単位回路部の全てが正常な状態での前記並行試験回路の第１の合成抵抗値Ｒ0と、ある一つの前記試験単位回路部が異常を生じたときの前記並行試験回路の第２の合成抵抗値Ｒ′0と、前記測定器の許容差及び前記試験単位回路部の許容差の和で示される合計許容差αとの間に次式（１） The abnormality detection method according to claim 2 is the method according to claim 1, wherein the first combined resistance value R 0 of the parallel test circuit when all of the test unit circuit units are normal is one The sum of the second combined resistance value R ′ 0 of the parallel test circuit and the tolerance of the measuring instrument and the tolerance of the test unit circuit when the two test unit circuits are abnormal The following formula (1) between the tolerance α

｜Ｒ0′−Ｒ0｜／（Ｒ0′＋Ｒ0）＞α …（１）
が成り立つように前記試験単位回路部を選定し、前記並行試験回路の電気抵抗値の段階的な変化を検出することにより、前記試験単位回路部の異常の発生を検出することを特徴とする。 | R 0 ′ −R 0 | / (R 0 ′ + R 0 )> α (1)
The test unit circuit section is selected so that the following holds, and the stepwise change in the electrical resistance value of the parallel test circuit is detected, thereby detecting the occurrence of an abnormality in the test unit circuit section.

請求項３に記載の異常検出方法は、請求項１または２に記載の方法において、予め前記各試験単位回路部が異常を生じる前後での前記並行試験回路のそれぞれの抵抗値の変化量を異常であると仮想した前記試験単位回路部の個数に関係付けて求め、前記測定値が変化したとき該測定値の変化分を予め求められた前記各抵抗値の変化量と比較し、この比較に基づいて異常を生じた試験単位回路部の個数を特定することを特徴とする。   The abnormality detection method according to claim 3 is the method according to claim 1 or 2, wherein the amount of change in the resistance value of each of the parallel test circuits before and after each test unit circuit unit is abnormal is abnormal. It is obtained in relation to the number of the test unit circuit sections hypothesized to be, and when the measurement value changes, the change amount of the measurement value is compared with the change amount of each resistance value obtained in advance. Based on this, the number of test unit circuit units having an abnormality is specified.

請求項４に記載の異常検出方法は、請求項１乃至３に記載の方法において、それぞれの前記試験単位回路部は検査対象回路と該検査対象回路に直列に接続された補助抵抗とからなり、前記試験単位回路部毎の合成電気抵抗が等しくなるように、前記各補助抵抗が直列接続される前記各検査対象回路の抵抗値に応じて前記各補助抵抗の抵抗値が選定されることを特徴とする。   The abnormality detection method according to claim 4 is the method according to claims 1 to 3, wherein each of the test unit circuit units includes an inspection target circuit and an auxiliary resistor connected in series to the inspection target circuit. The resistance value of each auxiliary resistor is selected according to the resistance value of each circuit to be inspected to which each auxiliary resistor is connected in series so that the combined electric resistance of each test unit circuit unit is equal. And

請求項５に記載の異常検出方法は、請求項１乃至３に記載の方法において、それぞれの前記試験単位回路部は検査対象回路と該検査対象回路に並列に接続された補助抵抗とからなり、前記試験単位回路部毎の合成電気抵抗が等しくなるように、前記各補助抵抗が並列接続される前記各検査対象回路の抵抗値に応じて前記各補助抵抗が選定されることを特徴とする。   The abnormality detection method according to claim 5 is the method according to claims 1 to 3, wherein each of the test unit circuit units includes an inspection target circuit and an auxiliary resistor connected in parallel to the inspection target circuit. Each auxiliary resistor is selected according to the resistance value of each circuit to be inspected to which each auxiliary resistor is connected in parallel so that the combined electric resistance of each test unit circuit unit becomes equal.

請求項６に記載の異常検出方法は、電気抵抗値を互いに異にする複数の試験単位回路部が互いに接続されてなる並行試験回路の電気抵抗値を測定し、当該測定値に基づいて前記試験単位回路部の異常の発生を検出する方法であって、予め、前記各試験単位回路部が異常を生じる前後での前記並行試験回路のそれぞれの抵抗値の変化量を異常が生じたと仮想した前記試験単位回路部に関係付けて求め、前記測定値が変化したとき該測定値の変化分を予め求められた前記各抵抗値の変化量と比較し、この比較に基づいて異常を生じたのがいずれの前記試験回路部であるかを判定することを特徴とする。   The abnormality detection method according to claim 6, wherein an electrical resistance value of a parallel test circuit in which a plurality of test unit circuit units having different electrical resistance values are connected to each other is measured, and the test is performed based on the measured value. A method for detecting the occurrence of an abnormality in a unit circuit unit, wherein the amount of change in the resistance value of each parallel test circuit before and after each test unit circuit unit is abnormal is assumed to be abnormal It is obtained in relation to the test unit circuit part, and when the measured value changes, the change amount of the measured value is compared with the change amount of each resistance value obtained in advance, and the abnormality is caused based on this comparison. It is characterized by determining which of the test circuit units.

請求項７に記載の異常検出方法は、請求項６に記載の方法において、ある一つの前記試験単位回路部が異常であるときの前記並行試験回路の第２の合成抵抗値Ｒ0′と、前記一つの試験単位回路部に加えて他の一つの前記試験単位回路部が異常を生じたときの前記並行試験回路の第３の合成抵抗値Ｒ0′′と、前記測定器の許容差と前記試験単位回路部の許容差との和で示される合計許容差αとの間に次式（２） The abnormality detection method according to claim 7 is the method according to claim 6, wherein the second combined resistance value R 0 ′ of the parallel test circuit when one of the test unit circuit units is abnormal, A third combined resistance value R 0 ″ of the parallel test circuit when an abnormality occurs in another test unit circuit unit in addition to the one test unit circuit unit; Between the total tolerance α indicated by the sum of the tolerances of the test unit circuit section, the following equation (2)

｜Ｒ0′−Ｒ0′′｜／（Ｒ0′＋Ｒ0′′）＞α …（２）
が成り立つように前記試験単位回路部を選定し、前記並行試験回路の電気抵抗値の段階的な変化を検出することにより、前記試験単位回路部の異常の発生を検出することを特徴とする。 | R 0 ′ −R 0 ′ | / (R 0 ′ + R 0 ′)> α (2)
The test unit circuit section is selected so that the following holds, and the stepwise change in the electrical resistance value of the parallel test circuit is detected, thereby detecting the occurrence of an abnormality in the test unit circuit section.

請求項８に記載の異常検出方法は、請求項６または７に記載の方法において、それぞれの前記試験単位回路部は検査対象回路と該検査対象回路に直列に接続された補助抵抗からなり、前記試験単位回路部毎に重み付を与え、これにより前記各試験単位回路部の合成電気抵抗が段階的に変化するように、前記各補助抵抗が直列接続される前記各検査対象回路の抵抗値に応じて前記各補助抵抗が選定されることを特徴とする。   The abnormality detection method according to claim 8 is the method according to claim 6 or 7, wherein each of the test unit circuit units includes a test target circuit and an auxiliary resistor connected in series to the test target circuit. Weighting is applied to each test unit circuit unit, and thereby the resistance value of each circuit to be inspected to which each auxiliary resistor is connected in series so that the combined electrical resistance of each test unit circuit unit changes stepwise. Each of the auxiliary resistors is selected accordingly.

請求項９に記載の異常検出方法は、請求項６または７に記載の方法において、それぞれの前記試験単位回路部は検査対象回路と該検査対象回路に並列に接続された補助抵抗とからなり、前記試験単位回路部毎に重み付けを与え、これにより前記各試験単位回路部毎の合成電気抵抗が段階的に変化するように、前記各補助抵抗が並列接続される前記各検査対象回路の抵抗値に応じて前記各補助抵抗が選定されることを特徴とする。   The abnormality detection method according to claim 9 is the method according to claim 6 or 7, wherein each of the test unit circuit units includes an inspection target circuit and an auxiliary resistor connected in parallel to the inspection target circuit. Each test unit circuit unit is weighted, and thereby the resistance value of each circuit under test to which each auxiliary resistor is connected in parallel so that the combined electrical resistance of each test unit circuit unit changes stepwise. The auxiliary resistors are selected according to the above.

請求項１０に記載の異常検出方法は、請求項４、５、８または９に記載の方法において、前記試験単位回路部は静電容量を有し、該静電容量の等価抵抗値がこれに接続された前記補助抵抗の抵抗値よりも小さいことを特徴とする。   The abnormality detection method according to a tenth aspect is the method according to the fourth, fifth, eighth, or ninth aspect, wherein the test unit circuit unit has a capacitance, and an equivalent resistance value of the capacitance is equal to this. It is smaller than the resistance value of the connected auxiliary resistor.

請求項１１に記載の異常検出方法は、請求項４、５、８、９または１０に記載の方法において、前記補助抵抗は、前記検査対象回路に比較して充分な耐久性を有することを特徴とする。   An abnormality detection method according to an eleventh aspect is the method according to the fourth, fifth, eighth, ninth or tenth aspect, wherein the auxiliary resistor has sufficient durability compared to the circuit to be inspected. And

請求項１２に記載の異常検出方法は、請求項１または６に記載の方法において、前記試験単位回路部の許容差は、試験温度範囲の抵抗値変化分を含むことを特徴とする。   The abnormality detection method according to a twelfth aspect is the method according to the first or sixth aspect, wherein the tolerance of the test unit circuit unit includes a change in resistance value in a test temperature range.

請求項１３に記載の異常検出方法は、請求項４、５、８または９に記載の方法において、前記試験単位回路部の前記検査対象回路は、回路本体部分と該本体部分から伸び、回路基板に接続される接合部分とを有し、前記接合部分と前記基板との接合部における耐久性は前記回路本体部分におけるそれよりも優れていることを特徴とする。   The abnormality detection method according to claim 13 is the method according to claim 4, 5, 8, or 9, wherein the circuit to be inspected of the test unit circuit portion extends from the circuit body portion and the body portion, and the circuit board. And the durability at the joint between the joint and the substrate is better than that at the circuit body.

請求項１４に記載の異常検出方法は、請求項４、５、８または９に記載の方法において、前記試験単位回路部の前記検査対象回路は、回路本体部分と該本体部分から伸び、回路基板に接続される接合部分とを有し、前記回路本体部分における耐久性は前記接合部分と前記基板との接合部におけるそれよりも優れていることを特徴とする。   The abnormality detection method according to claim 14 is the method according to claim 4, 5, 8, or 9, wherein the circuit to be inspected of the test unit circuit portion extends from the circuit body portion and the body portion, and the circuit board. The circuit body portion is more durable than the joint portion between the joint portion and the substrate.

請求項１５に記載の異常検出装置は、ほぼ等しい電気抵抗値を示す複数の試験単位回路部が互いに接続されてなる並行試験回路の電気抵抗値を測定する抵抗測定器と、メモリと、前記抵抗測定器により測定された抵抗値に基づいて前記試験単位回路部に異常が生じたか否かを判定する判定回路と、表示部とを備える異常検出装置であって、前記各試験単位回路部は相互に並列又は直列に接続され、前記試験単位回路部の全てが正常な状態での前記並行試験回路の第１の合成抵抗値Ｒ0と、ある一つの前記試験単位回路部が異常を生じたときの前記並行試験回路の第２の合成抵抗値Ｒ′0と、前記測定器の許容差及び前記試験単位回路部の許容差の和で示される合計許容差αとの間に次式（１） The abnormality detection device according to claim 15, wherein a resistance measuring instrument that measures an electrical resistance value of a parallel test circuit in which a plurality of test unit circuit portions having substantially equal electrical resistance values are connected to each other, a memory, and the resistance An abnormality detection device comprising: a determination circuit that determines whether or not an abnormality has occurred in the test unit circuit unit based on a resistance value measured by a measuring instrument; and a display unit, wherein the test unit circuit units are mutually connected Are connected in parallel or in series, and when all of the test unit circuit units are in a normal state, the first combined resistance value R 0 of the parallel test circuit and one of the test unit circuit units is abnormal Between the second combined resistance value R ′ 0 of the parallel test circuit and the total tolerance α indicated by the sum of the tolerance of the measuring instrument and the tolerance of the test unit circuit section (1)

｜Ｒ0′−Ｒ0｜／（Ｒ0′＋Ｒ0）＞α …（１）
が成り立ち、前記メモリには、予め、前記各試験単位回路部が異常を生じる前後での前記並行試験回路のそれぞれの電気抵抗値の各変化量が、該変化量を与える異常な試験単位回路の個数に関連して格納されており、前記判定回路は、抵抗測定器による測定抵抗値の変化分と前記メモリに格納された前記各変化量との差分を算出する演算処理部を有し、該演算処理部により求められた前記差分が前記合計許容差α内にあるとき、異常が生じた旨及び当該差分を与えた前記変化量についての前記試験単位回路の個数についての情報を前記表示部に表示させることを特徴とする。 | R 0 ′ −R 0 | / (R 0 ′ + R 0 )> α (1)
In the memory, the amount of change in the electrical resistance value of each of the parallel test circuits before and after the occurrence of an abnormality in each test unit circuit unit is stored in advance in the abnormal test unit circuit that gives the change amount. The determination circuit has an arithmetic processing unit that calculates a difference between a change amount of the measured resistance value by the resistance measuring instrument and each change amount stored in the memory, and When the difference obtained by the arithmetic processing unit is within the total tolerance α, information indicating that an abnormality has occurred and the number of test unit circuits for the amount of change that has given the difference are displayed on the display unit. It is characterized by being displayed.

請求項１６に記載の異常検出装置は、請求項１５に記載の装置において、それぞれの前記試験単位回路部は検査対象回路と該検査対象回路に直列に接続された補助抵抗とからなり、前記試験単位回路部毎の合成電気抵抗が等しくなるように、前記補助抵抗が直列接続される前記各検査対象回路抵抗値に応じて前記各補助抵抗の抵抗値が選定されていることを特徴とする。   The abnormality detection device according to claim 16 is the device according to claim 15, wherein each of the test unit circuit units includes a circuit to be inspected and an auxiliary resistor connected in series to the circuit to be inspected. The resistance value of each auxiliary resistor is selected according to the resistance value of each circuit under test to which the auxiliary resistor is connected in series so that the combined electric resistance of each unit circuit unit is equal.

請求項１７に記載の異常検出装置は、請求項１５に記載の装置において、それぞれの前記試験単位回路部は検査対象回路と該検査対象回路に並列に接続された補助抵抗とからなり、前記試験単位回路部毎の合成電気抵抗が等しくなるように、前記各補助抵抗が並列接続される前記各検査対象回路の抵抗値に応じて前記各補助抵抗が選定されていることを特徴とする。   The abnormality detection device according to claim 17 is the device according to claim 15, wherein each of the test unit circuit units includes a test target circuit and an auxiliary resistor connected in parallel to the test target circuit. Each auxiliary resistor is selected according to the resistance value of each circuit to be inspected to which each auxiliary resistor is connected in parallel so that the combined electric resistance of each unit circuit unit is equal.

請求項１８に記載の異常検出装置は、電気抵抗値を互いに異にする複数の試験単位回路部が互いに接続されてなる並行試験回路の電気抵抗値を測定する抵抗測定器と、メモリと、前記抵抗測定器により測定された抵抗値に基づいて前記試験単位回路部に異常が生じたか否かを判定する判定回路と、表示部とを備える異常検出装置であって、前記各試験単位回路部は相互に並列又は直列に接続され、ある一つの前記試験単位回路部が異常であるときの前記並行試験回路の第２の合成抵抗値Ｒ0′と、前記一つの試験単位回路部に加えて他の一つの前記試験単位回路部が異常を生じたときの前記並行試験回路の第３の合成抵抗値Ｒ0′′と、前記測定器の許容差と前記試験単位回路部の許容差との和で示される合計許容差αとの間に次式（２） The abnormality detection device according to claim 18, wherein a resistance measuring instrument for measuring an electrical resistance value of a parallel test circuit in which a plurality of test unit circuit portions having different electrical resistance values are connected to each other, a memory, and the memory An abnormality detection device comprising a determination circuit for determining whether an abnormality has occurred in the test unit circuit unit based on a resistance value measured by a resistance measuring instrument, and a display unit, wherein each test unit circuit unit is A second combined resistance value R 0 ′ of the parallel test circuit when one of the test unit circuit units is abnormal when connected in parallel or in series with each other, and in addition to the one test unit circuit unit The third combined resistance value R 0 ″ of the parallel test circuit when an abnormality occurs in one of the test unit circuit units, and the sum of the tolerance of the measuring instrument and the tolerance of the test unit circuit unit (2) between the total tolerance α indicated by

｜Ｒ0′−Ｒ0′′｜／（Ｒ0′＋Ｒ0′′）＞α …（２）
が成り立ち、前記メモリには、予め、前記各試験単位回路部が異常を生じる前後での前記並行試験回路のそれぞれの電気抵抗値の各変化量が、該変化量を与える異常な試験単位回路を特定する情報に関連して格納されており、前記判定回路は、前記抵抗測定器による測定抵抗値の変化分と前記メモリに格納された前記各変化量との差分を算出する演算処理部を有し、該演算処理部により求められた前記差分が前記合計許容差α内にあるとき、異常が生じた旨及び当該差分を与えた前記変化量についての前記試験単位回路部を特定する情報を前記表示部に表示させることを特徴とする。 | R 0 ′ −R 0 ′ | / (R 0 ′ + R 0 ′)> α (2)
In the memory, an abnormal test unit circuit in which each change amount of each electrical resistance value of the parallel test circuit before and after each test unit circuit unit is abnormal is given an abnormal amount. The determination circuit has an arithmetic processing unit that calculates a difference between a change amount of the resistance value measured by the resistance measuring instrument and each change amount stored in the memory. When the difference obtained by the arithmetic processing unit is within the total tolerance α, information specifying that the test unit circuit unit is informed that an abnormality has occurred and the amount of change that gave the difference It is characterized by being displayed on a display unit.

請求項１９に記載の異常検出装置は、請求項１８に記載の装置において、それぞれの前記試験単位回路部は検査対象回路と該検査対象回路に直列に接続された補助抵抗とからなり、前記試験単位回路部毎に重みを与え、これにより前記各試験単位回路部の合成電気抵抗が段階的に変化するように、前記各補助抵抗が直列接続される前記各検査対象回路抵抗値に応じて前記各補助抵抗の抵抗値が選定されていることを特徴とする。   The abnormality detection apparatus according to claim 19 is the apparatus according to claim 18, wherein each of the test unit circuit units includes a circuit to be inspected and an auxiliary resistor connected in series to the circuit to be inspected. Weight is given to each unit circuit unit, and the auxiliary resistance is connected in series so that the combined electric resistance of each test unit circuit unit changes stepwise, according to each circuit resistance value to be inspected The resistance value of each auxiliary resistor is selected.

請求項２０に記載の異常検出装置は、請求項１８に記載の装置において、それぞれの前記試験単位回路部は検査対象回路と該検査対象回路に並列に接続された補助抵抗とからなり、前記試験単位回路部毎に重みを与え、これにより前記各試験単位回路部の合成電気抵抗が段階的に変化するように、前記各補助抵抗が並列接続される前記各検査対象回路抵抗値に応じて前記各補助抵抗の抵抗値が選定されていることを特徴とする。   The abnormality detection device according to claim 20 is the device according to claim 18, wherein each of the test unit circuit units includes a test target circuit and an auxiliary resistor connected in parallel to the test target circuit. Weight is given to each unit circuit unit, and the auxiliary resistances are connected in parallel so that the combined electric resistance of each test unit circuit unit changes stepwise, according to each circuit resistance value to be inspected The resistance value of each auxiliary resistor is selected.

請求項２１に記載の異常検出装置は、請求項１６、１７、１９または２０に記載の装置において、前記試験単位回路部は静電容量を有し、該静電容量の等価抵抗値がこれに接続された前記補助抵抗の抵抗値よりも小さいことを特徴とする。   An abnormality detection device according to a twenty-first aspect is the device according to the sixteenth, seventeenth, nineteenth, or twenty-first aspect, wherein the test unit circuit section has a capacitance, and an equivalent resistance value of the capacitance is equal to this. It is smaller than the resistance value of the connected auxiliary resistor.

請求項１に記載の方法によれば、互いに並列または直列に接続された複数の試験単位回路部で構成される並行試験回路の電気抵抗値の変化分が閾値である合計許容差αを超えたとき前記試験単位回路部に異常が生じたと判定されることから、スイッチング操作や切替え手段を用いることなく複数の試験単位回路部のいずれかに異常が発生したことを検出することができる。   According to the method of claim 1, the change in the electrical resistance value of the parallel test circuit composed of a plurality of test unit circuit units connected in parallel or in series with each other exceeds the total tolerance α that is a threshold value. Since it is determined that an abnormality has occurred in the test unit circuit unit, it is possible to detect that an abnormality has occurred in any of the plurality of test unit circuit units without using a switching operation or switching means.

請求項２に記載の方法によれば、総ての試験単位回路部が正常な状態での並行試験回路の第１の合成抵抗値Ｒ0と、ある一つの前記試験単位回路部が異常を生じたときの前記並行試験回路の第２の合成抵抗値Ｒ′0と、前記測定器の許容差及び前記試験単位回路部の許容差の和で示される合計許容差αとの間に式（１）が成り立つように前記試験単位回路部を選定することにより、各試験単位回路部の異常毎に前記並行試験回路の電気抵抗値を段階的に変化させることができるので、この段階的な抵抗変化を検出することにより、各試験単位回路部の異常を確実に検出することができる。 According to the method of claim 2, the first combined resistance value R 0 of the parallel test circuit in a state where all the test unit circuit units are normal, and an abnormality occurs in one of the test unit circuit units. (1) between the second combined resistance value R ′ 0 of the parallel test circuit and the total tolerance α indicated by the sum of the tolerance of the measuring instrument and the tolerance of the test unit circuit section. ) Is selected so that the electrical resistance value of the parallel test circuit can be changed step by step for each abnormality of each test unit circuit portion. By detecting this, it is possible to reliably detect an abnormality in each test unit circuit unit.

請求項３に記載の方法によれば、予め各試験単位回路部が異常を生じる前後での並行試験回路のそれぞれの抵抗値の変化量を異常であると仮想した試験単位回路部の個数に関係付けて求めておき、測定値が変化したとき該測定値の変化分を予め求められた前記各抵抗値の変化量と比較することにより、異常を生じた試験単位回路部の個数を知ることができる。   According to the method of claim 3, the amount of change in the resistance value of each parallel test circuit before and after each test unit circuit unit is abnormal is related to the number of test unit circuit units hypothesized to be abnormal. In addition, when the measured value changes, it is possible to know the number of test unit circuit units in which an abnormality has occurred by comparing the amount of change in the measured value with the amount of change in each resistance value obtained in advance. it can.

請求項４及び５に記載の方法によれば、検査対象回路と、該検査対象回路に直列又は並列に接続される補助抵抗とで試験単位回路部を構成することにより、補助抵抗の抵抗値をこれが接続された検査対象回路の抵抗値に応じて、各試験単位回路部の合成電気抵抗が互いに等しく設定することができ、これにより、検査対象回路の抵抗値のばらつきの如何に拘わらず、誤り無く異常を検出することができる。   According to the method of claim 4 and 5, the resistance value of the auxiliary resistor is obtained by configuring the test unit circuit unit with the circuit to be inspected and the auxiliary resistor connected in series or in parallel with the circuit to be inspected. Depending on the resistance value of the circuit to be inspected to which it is connected, the combined electrical resistance of each test unit circuit unit can be set equal to each other. Abnormality can be detected.

請求項６に記載の方法によれば、並行試験回路の電気抵抗の測定値が変化したときに、該測定値の変化分を予め求められた各試験単位回路部が異常であるときの並行試験回路のそれぞれの抵抗値の変化量と比較することにより、スイッチング操作や切替え手段を用いることなく、試験単位回路部の異常の発生を検出することができ、しかも異常がいずれの試験単位回路部で生じたかを特定することができる。   According to the method of claim 6, when the measurement value of the electrical resistance of the parallel test circuit changes, the parallel test when each test unit circuit unit for which the change of the measurement value is obtained in advance is abnormal By comparing with the amount of change in the resistance value of each circuit, the occurrence of an abnormality in the test unit circuit unit can be detected without using a switching operation or switching means, and the abnormality is detected in any test unit circuit unit. It can be identified whether it has occurred.

請求項７に記載の方法によれば、ある一つの試験単位回路部が異常であるときの並行試験回路の第２の合成抵抗値Ｒ0′と、前記一つの試験単位回路部に加えて他の一つの試験単位回路部が異常を生じたときの並行試験回路の第３の合成抵抗値Ｒ0′′と、前記測定器の許容差と前記試験単位回路部の許容差との和で示される合計許容差αとの間に式（２）が成り立つように前記試験単位回路部を選定することにより、各試験単位回路部の異常の発生毎に前記並行試験回路の電気抵抗値を段階的に変化させることができるので、この段階的な抵抗変化を検出することにより、各試験単位回路部の異常の発生を確実に検出することができると共に、異常がいずれの試験単位回路部で生じたかを確実に検出することができる。 According to the method of claim 7, the second combined resistance value R 0 ′ of the parallel test circuit when a certain test unit circuit unit is abnormal, and other in addition to the one test unit circuit unit The third combined resistance value R 0 ″ of the parallel test circuit when one of the test unit circuit units has an abnormality, and the sum of the tolerance of the measuring instrument and the tolerance of the test unit circuit unit By selecting the test unit circuit unit so that the formula (2) holds between the total tolerance α and the total tolerance α, the electrical resistance value of the parallel test circuit is stepwise for each occurrence of abnormality in each test unit circuit unit. By detecting this stepwise change in resistance, it is possible to reliably detect the occurrence of an abnormality in each test unit circuit unit, and in which test unit circuit unit the abnormality occurred. Can be reliably detected.

請求項８及び９に記載の方法によれば、検査対象回路と、該検査対象回路に直列または並列に接続される補助抵抗とで試験単位回路部を構成し、補助抵抗の抵抗値をこれが接続された検査対象回路の抵抗値に応じて選択することにより、各試験単位回路部のそれぞれに重み付を与えることができるので、検査対象回路の抵抗値のばらつきの如何に拘わらず、各試験単位回路部の合成電気抵抗を各検査対象回路の異常の発生毎に段階的に変化させることができ、これにより検査対象回路の抵抗値のばらつきに拘わらず、該検査対象回路の異常の発生を検出することができ、あるいはいずれの試験単位回路に異常が生じたかを知ることができる。   According to the method of claims 8 and 9, the test unit circuit unit is configured by the circuit to be inspected and the auxiliary resistor connected in series or in parallel to the circuit to be inspected, and the resistance value of the auxiliary resistor is connected to this. By selecting according to the resistance value of the circuit to be inspected, each test unit circuit unit can be weighted, so that each test unit is independent of the variation in the resistance value of the circuit to be inspected. The combined electrical resistance of the circuit section can be changed step by step for each abnormality of the circuit to be inspected, so that the occurrence of abnormality in the circuit to be inspected can be detected regardless of variations in the resistance value of the circuit to be inspected. Or which test unit circuit is abnormal can be known.

請求項１０に記載の方法によれば、試験回路部に静電容量を適用することができ、この場合、静電容量の等価抵抗値がこれに接続される補助抵抗の抵抗値よりも小さくなるように該補助抵抗の抵抗値を設定することにより、静電容量の異常の検出を正確に行うことができる。   According to the method of claim 10, the capacitance can be applied to the test circuit unit, and in this case, the equivalent resistance value of the capacitance is smaller than the resistance value of the auxiliary resistor connected thereto. By setting the resistance value of the auxiliary resistor as described above, it is possible to accurately detect an abnormality in capacitance.

請求項１１に記載の方法によれば、検査対象回路に比較して充分な耐久性を有する補助抵抗を用いることにより、この補助抵抗の異常による誤判定を確実に防止することができる。   According to the method of the eleventh aspect, by using the auxiliary resistor having sufficient durability as compared with the circuit to be inspected, it is possible to reliably prevent the erroneous determination due to the abnormality of the auxiliary resistor.

請求項１２に記載の方法によれば、試験単位回路に温度変化を与える加速試験などにおいても、試験単位回路の温度変化に伴う抵抗値変化が予め考慮されていることから、この温度変化に起因する抵抗値変化による誤検出を確実に防止することができる。   According to the method of claim 12, since the resistance value change accompanying the temperature change of the test unit circuit is taken into consideration in an accelerated test or the like that gives a temperature change to the test unit circuit, it is caused by this temperature change. It is possible to reliably prevent erroneous detection due to a change in resistance value.

請求項１３に記載の方法によれば、回路基板への接続部となる検査対象回路の接合部分は、その回路本体部分よりも耐久性が優れていることから、前記接合部分での劣化などによる誤判定が確実に防止でき、回路本体部分の正確な評価が可能となる。   According to the method of claim 13, since the joint portion of the circuit to be inspected that becomes the connection portion to the circuit board has better durability than the circuit main body portion, the joint portion is deteriorated. An erroneous determination can be reliably prevented, and an accurate evaluation of the circuit body can be performed.

請求項１４に記載の方法によれば、検査対象回路の回路本体部分は回路基板への接続部となる接合部分よりも耐久性が優れていることから、前記回路本体部に代えて前記接合部分での異常の発生を確実に検出することができるので、前記回路本体部の評価に代えて前記接合部分での評価が可能となる。   According to the method of claim 14, the circuit body portion of the circuit to be inspected is more durable than the joint portion serving as the connection portion to the circuit board. Therefore, the joint portion is replaced with the circuit body portion. Therefore, it is possible to reliably detect the occurrence of an abnormality at the joint portion, so that the evaluation at the joint portion can be performed instead of the evaluation of the circuit body portion.

請求項１５に記載の装置によれば、総ての試験単位回路部が正常な状態での並行試験回路の第１の合成抵抗値Ｒ0と、ある一つの前記試験単位回路部が異常を生じたときの前記並行試験回路の第２の合成抵抗値Ｒ′0と、前記測定器の許容差及び前記試験単位回路部の許容差の和で示される合計許容差αとの間に式（１）が成り立つように前記試験単位回路部が選定され、判定回路が抵抗測定器による測定抵抗値の変化分とメモリに格納された各抵抗値の変化量との差分を算出し、求められた前記差分と前記合計許容差αとの比較により、スイッチング操作や切替え手段を用いることなく、試験単位回路部の異常の発生を検出することができ、しかも異常を生じた試験単位回路部の個数を知ることができる。 According to the apparatus of claim 15, the first combined resistance value R 0 of the parallel test circuit in a state where all the test unit circuit units are normal, and an abnormality occurs in one of the test unit circuit units. (1) between the second combined resistance value R ′ 0 of the parallel test circuit and the total tolerance α indicated by the sum of the tolerance of the measuring instrument and the tolerance of the test unit circuit section. The test unit circuit unit is selected such that the determination unit calculates the difference between the amount of change in the resistance value measured by the resistance measuring instrument and the amount of change in each resistance value stored in the memory. By comparing the difference with the total tolerance α, it is possible to detect the occurrence of an abnormality in the test unit circuit unit without using a switching operation or switching means, and to know the number of test unit circuit units in which an abnormality has occurred. be able to.

請求項１６及び１７に記載の発明によれば、検査対象回路と、該検査対象回路に並列または直列接続される補助抵抗とで試験単位回路部を構成し、補助抵抗の抵抗値をこれが接続された検査対象回路の抵抗値に応じて選択することにより、各試験単位回路部の合成電気抵抗が段階的に変化するようにそれぞれに重み付を与えることができるので、検査対象回路の抵抗値のばらつきの如何に拘わらず、異常の発生を検出することができる。   According to the sixteenth and seventeenth aspects of the present invention, the test unit circuit unit is configured by the circuit to be inspected and the auxiliary resistor connected in parallel or in series with the circuit to be inspected, and the resistance value of the auxiliary resistor is connected thereto. By selecting according to the resistance value of the circuit to be inspected, weighting can be given to each of the test unit circuit units so that the combined electric resistance of each test unit circuit portion changes stepwise. The occurrence of abnormality can be detected regardless of the variation.

請求項１８に記載の発明によれば、ある一つの前記試験単位回路部が異常であるときの前記並行試験回路の第２の合成抵抗値Ｒ0′と、前記一つの試験単位回路部に加えて他の一つの前記試験単位回路部が異常を生じたときの前記並行試験回路の第３の合成抵抗値Ｒ0′′と、前記測定器の許容差と前記試験単位回路部の許容差との和で示される合計許容差αとの間に式（２）が成り立つように前記試験単位回路部が選定され、判定回路が前記抵抗測定器による測定抵抗値の変化分とメモリに格納された前記各抵抗値の変化量との差分を算出し、求められた前記差分と前記合計許容差αとの比較により、スイッチング操作や切替え手段を用いることなく、試験単位回路部の異常の発生を検出することができ、しかもいずれの試験単位回路部が異常を生じたのかを知ることができる。 According to the invention of claim 18, in addition to the second combined resistance value R 0 ′ of the parallel test circuit when one of the test unit circuit units is abnormal, in addition to the one test unit circuit unit A third combined resistance value R 0 ″ of the parallel test circuit when another one of the test unit circuit units is abnormal, a tolerance of the measuring instrument, and a tolerance of the test unit circuit unit, The test unit circuit unit is selected so that the expression (2) is established between the total tolerance α and the sum tolerance α, and a determination circuit is stored in the memory and the change in the resistance value measured by the resistance measuring instrument. The difference between each change in resistance value is calculated, and the occurrence of an abnormality in the test unit circuit unit is detected without using a switching operation or switching means by comparing the obtained difference with the total tolerance α. In addition, any test unit circuit section is different. You can know what happened.

請求項１９及び２０に記載の発明によれば、検査対象回路と、該検査対象回路に並列または直列接続される補助抵抗とで試験単位回路部を構成し、補助抵抗の抵抗値をこれが接続された検査対象回路の抵抗値に応じて選択することにより、各試験単位回路部の合成電気抵抗が段階的に変化するようにそれぞれに重み付を与えることができるので、検査対象回路の抵抗値のばらつきの如何に拘わらず、異常の発生を検出することができる。   According to the inventions of claims 19 and 20, the test unit circuit unit is configured by the circuit to be inspected and the auxiliary resistor connected in parallel or in series with the circuit to be inspected, and the resistance value of the auxiliary resistor is connected to this. By selecting according to the resistance value of the circuit to be inspected, weighting can be given to each of the test unit circuit units so that the combined electric resistance of each test unit circuit portion changes stepwise. The occurrence of abnormality can be detected regardless of the variation.

請求項２１に記載の装置によれば、試験回路部に静電容量を適用することができ、この場合、静電容量の等価抵抗値がこれに接続される補助抵抗の抵抗値よりも小さくなるように該補助抵抗の抵抗値を設定することにより、異常の発生を正確に検出し、いずれの試験単位回路に異常が生じたかを正確に知ることができる。   According to the device of the twenty-first aspect, the capacitance can be applied to the test circuit unit. In this case, the equivalent resistance value of the capacitance is smaller than the resistance value of the auxiliary resistor connected thereto. Thus, by setting the resistance value of the auxiliary resistor, it is possible to accurately detect the occurrence of an abnormality and to know exactly which test unit circuit has an abnormality.

本発明の方法によれば、複数の測定手段や選択手段を用いることなく、またスイッチ切替による作業を伴うことなく、試験単位回路の異常の発生を検出することができる。   According to the method of the present invention, it is possible to detect the occurrence of an abnormality in a test unit circuit without using a plurality of measuring means and selecting means, and without accompanying work by switching a switch.

また、本発明の方法によれば、複数の測定手段や選択手段を用いることなく、またスイッチ切替による作業を伴うことなく、試験単位回路部の異常の発生を検出することができ、しかも異常がいずれの試験単位回路部で生じたかを知ることができる。   In addition, according to the method of the present invention, it is possible to detect the occurrence of an abnormality in the test unit circuit unit without using a plurality of measurement means and selection means, and without performing work by switching, and there is an abnormality. It is possible to know in which test unit circuit unit the error occurred.

また、本発明の装置によれば、本発明の方法を比較的容易且つ安価に実施することができ、試験単位回路の異常の発生を正確に検出することができる。   Further, according to the apparatus of the present invention, the method of the present invention can be implemented relatively easily and inexpensively, and the occurrence of an abnormality in the test unit circuit can be accurately detected.

また、本発明の装置によれば、本発明の方法を比較的容易且つ安価に実施することができ、試験単位回路部の異常の発生を正確に検出することができ、しかも異常がいずれの試験単位回路部で生じたかを正確に知ることができる。   Further, according to the apparatus of the present invention, the method of the present invention can be carried out relatively easily and inexpensively, the occurrence of an abnormality in the test unit circuit unit can be accurately detected, and any abnormality is detected. It is possible to know exactly what has occurred in the unit circuit section.

本発明が特徴とするところは、図示の実施例に沿っての以下の説明により、さらに明らかとなろう。   The features of the present invention will become more apparent from the following description along with the illustrated embodiments.

図１は本発明に係る異常検出方法を実施する異常検出装置を概略的に示すブロック図である。   FIG. 1 is a block diagram schematically showing an abnormality detection apparatus for implementing an abnormality detection method according to the present invention.

本発明に係る異常検出装置１０は、試験対象である複数の検査対象回路１１（１１−１〜１１−ｎ）を含む並行試験回路１２の両端子１２ａ、１２ａの間の電気抵抗値を測定する抵抗測定器１３と、該抵抗測定器により得られた抵抗値データを処理する例えばパーソナルコンピュータのような情報処理装置１４とを備える。   The abnormality detection apparatus 10 according to the present invention measures an electrical resistance value between both terminals 12a and 12a of a parallel test circuit 12 including a plurality of test target circuits 11 (11-1 to 11-n) which are test targets. A resistance measuring device 13 and an information processing device 14 such as a personal computer for processing resistance value data obtained by the resistance measuring device are provided.

各検査対象回路１１（１１−１〜１１−ｎ）は、正常時に規定のほぼ等しい抵抗値を持ち、異常時に断線や回路の抵抗値が急激に上昇する回路、または逆に正常な状態が開放状態で、故障などによって導通状態に至る回路である。具体的には、抵抗体の回路基板へのはんだ付けの接合部分や半導体回路内の導体部分などである。   Each inspection object circuit 11 (11-1 to 11-n) has a resistance value that is almost equal to a normal value when it is normal, and a circuit in which the disconnection or the resistance value of the circuit rapidly increases when it is abnormal, or conversely, a normal state is opened. In this state, the circuit reaches a conductive state due to a failure or the like. Specifically, a soldering joint portion of a resistor to a circuit board, a conductor portion in a semiconductor circuit, or the like.

各検査対象回路１１（１１−１〜１１−ｎ）には、図１に示す例では、それぞれに直列に補助抵抗１５（１５−１〜１５−ｎ）が接続されている。互いに直列接続された各検査対象回路１１（１１−１〜１１−ｎ）及び補助抵抗１５（１５−１〜１５−ｎ）は、試験単位回路部１６を構成し、該試験単位回路部の並列接続により並行試験回路１２が構成されている。   In the example illustrated in FIG. 1, auxiliary resistors 15 (15-1 to 15-n) are connected in series to the respective inspection target circuits 11 (11-1 to 11-n). The test target circuits 11 (11-1 to 11-n) and the auxiliary resistors 15 (15-1 to 15-n) connected in series constitute a test unit circuit unit 16, and the test unit circuit units are connected in parallel. A parallel test circuit 12 is configured by the connection.

補助抵抗１５（１５−１〜１５−ｎ）は、抵抗値の製造誤差が同一の、例えば５％の許容差で製造された抵抗体の中から、各検査対象回路１１（１１−１〜１１−ｎ）の抵抗値のばらつきに応じて、それぞれの試験単位回路部１６での合成が等しくなるように、選択されたものが使用される。このような検査対象回路１１（１１−１〜１１−ｎ）の各補助抵抗１５（１５−１〜１５−ｎ）は、該補助抵抗の劣化による検出結果の誤りを防止するために、検査対象回路１１（１１−１〜１１−ｎ）に比較して充分に優れた耐久性を持つものが使用される。   The auxiliary resistor 15 (15-1 to 15-n) has the same manufacturing error in resistance value, for example, a resistor manufactured with a tolerance of 5%. The selected one is used so that the synthesis in each test unit circuit unit 16 becomes equal according to the variation in the resistance value of -n). The auxiliary resistors 15 (15-1 to 15-n) of the inspection target circuit 11 (11-1 to 11-n) are inspected in order to prevent erroneous detection results due to deterioration of the auxiliary resistors. Those having sufficiently superior durability compared to the circuit 11 (11-1 to 11-n) are used.

従って、全ての検査対象回路１１（１１−１〜１１−ｎ）が正常な状態では、各試験単位回路部１６の合成抵抗は等しく保持され、この試験単位回路部１６の合成抵抗の変化は、検査対象回路１１（１１−１〜１１−ｎ）の異常で生じると考えることができる。   Therefore, when all the test target circuits 11 (11-1 to 11-n) are in a normal state, the combined resistance of each test unit circuit unit 16 is kept equal, and the change in the combined resistance of the test unit circuit unit 16 is It can be considered that the abnormality occurs in the inspection target circuit 11 (11-1 to 11-n).

また、並行試験回路１２の各試験単位回路部１６の全てが正常な状態での並行試験回路１２の第１の合成抵抗値Ｒ0と、ある一つの試験単位回路部１６が異常を生じたときの並行試験回路１２の第２の合成抵抗値Ｒ′0と、測定器１３の許容差及び試験単位回路部１６の許容差の和で示される合計許容差αとの間に次式（１） Also, when the first combined resistance value R 0 of the parallel test circuit 12 in a state where all the test unit circuit units 16 of the parallel test circuit 12 are normal and an abnormality occurs in one test unit circuit unit 16 Between the second combined resistance value R ′ 0 of the parallel test circuit 12 and the total tolerance α indicated by the sum of the tolerance of the measuring instrument 13 and the tolerance of the test unit circuit section 16 (1)

｜Ｒ0′−Ｒ0｜／（Ｒ0′＋Ｒ0）＞α …（１）
が成り立つように、設定されている。 | R 0 ′ −R 0 | / (R 0 ′ + R 0 )> α (1)
Is set to hold.

式（１）は、並行試験回路１２のうちの任意の一つの試験単位回路部１６が異常を生じたとき、すなわち任意の一つの試験単位回路部１６の検査対象回路１１（１１−１〜１１−ｎ）に異常が生じた場合に成り立つ。   Expression (1) is obtained when any one of the test unit circuit units 16 in the parallel test circuit 12 has an abnormality, that is, the test target circuit 11 (11-1 to 11-11) of any one test unit circuit unit 16. This holds when an abnormality occurs in -n).

試験単位回路部１６を並列接続して構成された並行試験回路１２の端子間すなわち並行試験回路１２の抵抗を測定する抵抗測定器１３からの出力は、情報処理装置１４に出力される。情報処理装置１４は、メモリ１７と、抵抗測定器１３からの測定データに基づいて試験単位回路部１６に異常が生じたか否かを判定する判定回路１８と、該判定回路により異常が生じたと判定されたとき異常がある旨を表示するための例えば液晶表示板を有する表示部１９とを備える。抵抗測定器１３として、測定値を記録紙等に連続的あるいは定期的に記録できる抵抗測定器を用いることが望ましい。情報処理装置１４として、パーソナルコンピュータを利用することができる。   An output from the resistance measuring device 13 that measures the resistance of the parallel test circuit 12 between the terminals of the parallel test circuit 12 configured by connecting the test unit circuit units 16 in parallel, is output to the information processing device 14. The information processing device 14 determines whether an abnormality has occurred in the test unit circuit unit 16 based on the measurement data from the memory 17, the resistance measuring device 13, and determines that an abnormality has occurred by the determination circuit. A display unit 19 having, for example, a liquid crystal display panel for displaying that there is an abnormality. As the resistance measuring device 13, it is desirable to use a resistance measuring device capable of recording measured values continuously or periodically on recording paper or the like. As the information processing apparatus 14, a personal computer can be used.

情報処理装置１４のメモリ１７には、並行試験回路１２を構成する各試験単位回路部１６の検査対象回路１１（１１−１〜１１−ｎ）のそれぞれが異常を生じた場合における並行試験回路１２の電気抵抗値に関するデータの一つとして、判定回路１８による比較のための閾値が格納されている。この閾値として、前記合計許容差αが格納されている。また、メモリ１７には、後述するように抵抗測定器１３からの測定抵抗値についてのデータが逐次格納される。   In the memory 17 of the information processing apparatus 14, the parallel test circuit 12 in the case where each of the test target circuits 11 (11-1 to 11-n) of the test unit circuit units 16 constituting the parallel test circuit 12 is abnormal. As one of the data relating to the electrical resistance value, a threshold value for comparison by the determination circuit 18 is stored. The total tolerance α is stored as this threshold. Further, as will be described later, the memory 17 sequentially stores data on the measured resistance value from the resistance measuring device 13.

判定回路１８は、抵抗測定器１３からの測定抵抗値の変化分を算出する演算処理部１８ａと、出力部１８ｂとを有する。演算処理部１８ａは、また、求めた測定抵抗値の変化分とメモリ１７に格納された合計許容差αとを比較する。この演算処理部１８ａでの比較結果により測定抵抗値の変化分が合計許容差αを超えると、判定回路１８は、その出力部１８ｂから表示部１９に異常発生信号を出力する。   The determination circuit 18 includes an arithmetic processing unit 18a that calculates a change in the measured resistance value from the resistance measuring device 13, and an output unit 18b. The arithmetic processing unit 18 a also compares the obtained change in the measured resistance value with the total tolerance α stored in the memory 17. If the change in the measured resistance value exceeds the total tolerance α as a result of the comparison in the arithmetic processing unit 18a, the determination circuit 18 outputs an abnormality occurrence signal from the output unit 18b to the display unit 19.

図２は、並行試験回路１２の全ての検査対象回路１１（１１−１〜１１−ｎ）が正常な状態からそのうちのある一つの検査対象回路１１−１〜１１−ｎが異常を生じた状態に変移したときの並行試験回路１２の合成抵抗値の変化を示すグラフである。グラフの横軸は時間（ｔ）を示し、その縦軸は抵抗値（ｒ）を示す。   FIG. 2 shows a state where all the inspection target circuits 11 (11-1 to 11-n) of the parallel test circuit 12 are in a normal state, and one of the inspection target circuits 11-1 to 11-n is abnormal. It is a graph which shows the change of the synthetic | combination resistance value of the parallel test circuit 12 when changing to. The horizontal axis of the graph represents time (t), and the vertical axis represents the resistance value (r).

図２に示す例では、並行試験回路１２の各検査対象回路１１（１１−１〜１１−ｎ）が正常な状態では、並行試験回路１２の合成抵抗抵抗値は比較的低い値Ａを示すが、一つの検査対象回路１１、例えば検査対象回路１１−１が異常を示すと、該検査対象回路の異常によって並行試験回路１２の合成抵抗値は抵抗値Ａよりも高い値Ｂを示す。   In the example shown in FIG. 2, the combined resistance resistance value of the parallel test circuit 12 shows a relatively low value A when each circuit under test 11 (11-1 to 11-n) of the parallel test circuit 12 is normal. When one inspection target circuit 11, for example, the inspection target circuit 11-1 shows an abnormality, the combined resistance value of the parallel test circuit 12 shows a value B higher than the resistance value A due to the abnormality of the inspection target circuit.

このような検査対象回路１１（１１−１〜１１−ｎ）の異常の前後での並行試験回路１２の抵抗値の変化（Ｂ−Ａ）は、新たに異常を生じる検査対象回路１１（１１−１〜１１−ｎ）の個数に応じて増大する。しかも、前記した式（１）に示した条件を満たすように各補助抵抗１５（１５−１〜１５−ｎ）の値を設定することにより、検査対象回路１１（１１−１〜１１−ｎ）のいずれの異常によっても、図２に示すように、検査対象回路１１（１１−１〜１１−ｎ）の異常発生前後で並行試験回路１２に、異常を生じた検査対象回路１１（１１−１〜１１−ｎ）の個数に応じて、合計許容差αを超える階段状の明確な抵抗値変化が得られる。   The change (B-A) in the resistance value of the parallel test circuit 12 before and after the abnormality of the inspection target circuit 11 (11-1 to 11-n) is a new inspection target circuit 11 (11- 1 to 11-n). In addition, by setting the value of each auxiliary resistor 15 (15-1 to 15-n) so as to satisfy the condition shown in the above-described equation (1), the circuit under test 11 (11-1 to 11-n) 2, as shown in FIG. 2, the inspection target circuit 11 (11-1 in which the abnormality has occurred in the parallel test circuit 12 before and after the occurrence of the abnormality of the inspection target circuit 11 (11-1 to 11-n). Depending on the number of ˜11−n), a stepwise clear change in resistance value exceeding the total tolerance α is obtained.

情報処理装置１４は、前記したように、並行試験回路１２の抵抗値の入力を受けると、それぞれの抵抗値をメモリ１７に格納し、該メモリ内の抵抗値データから、判定回路１８が抵抗値の変化量を検出し、この変化量がメモリ１７に格納された閾値である合計許容差αを超えると表示部１９に異常が生じた旨を表示する。   As described above, when receiving the resistance value input of the parallel test circuit 12, the information processing device 14 stores each resistance value in the memory 17, and the determination circuit 18 determines the resistance value from the resistance value data in the memory. When the amount of change exceeds the total tolerance α, which is a threshold value stored in the memory 17, a message indicating that an abnormality has occurred is displayed on the display unit 19.

従って、従来のような複数の測定手段や選択手段を用いることなく、またスイッチ切替による作業を伴うことなく、試験単位回路の異常の発生を検出することができる。   Therefore, it is possible to detect the occurrence of an abnormality in the test unit circuit without using a plurality of measurement means and selection means as in the prior art, and without involving work by switching.

メモリ１７に格納されるデータとして、総ての検査対象回路１１（１１−１〜１１−ｎ）が正常である場合から、並行試験回路１２を構成する検査対象回路１１（１１−１〜１１−ｎ）が順次異常を生じ、結果的にそれらの総てが異常を生じた場合における並行試験回路１２の抵抗値の各変化量についてのデータを、各変化量を求めるに際し異常が生じていると仮想した検査対象回路１１（１１−１〜１１−ｎ）の個数に関連付けて格納することができる。   As data stored in the memory 17, since all the inspection target circuits 11 (11-1 to 11-n) are normal, the inspection target circuits 11 (11-1 to 11-constituting the parallel test circuit 12 are used. n) When an abnormality occurs sequentially, and as a result, when all the abnormality occurs, an abnormality occurs when the data about each change amount of the resistance value of the parallel test circuit 12 is calculated. The number of virtual inspection target circuits 11 (11-1 to 11-n) can be stored in association with each other.

この場合、判定回路１８の演算処理部１８ａは、メモリ１７に格納された前記抵抗値の総ての変化量と、抵抗測定器１３からの抵抗測定値の変化分との差分を演算し、求められた差分が合計許容差α内にあるとき、この差分を与えた当該変化量に対応する異常な検査対象回路１１（１１−１〜１１−ｎ）の個数についての情報をメモリ１７から読み出し、個数についての情報信号を異常情報信号と共に表示部１９に供給する。従って、表示部１９には異常の発生と共に、異常を生じた検査対象回路１１（１１−１〜１１−ｎ）の個数についての情報が表示されることから、検査対象回路１１（１１−１〜１１−ｎ）の異常の発生及び異常を生じた検査対象回路１１（１１−１〜１１−ｎ）の個数を知ることができる。   In this case, the arithmetic processing unit 18a of the determination circuit 18 calculates and finds the difference between the total change amount of the resistance value stored in the memory 17 and the change amount of the resistance measurement value from the resistance measuring device 13. When the obtained difference is within the total tolerance α, information on the number of abnormal test target circuits 11 (11-1 to 11-n) corresponding to the change amount giving the difference is read from the memory 17, The information signal about the number is supplied to the display unit 19 together with the abnormal information signal. Therefore, since information on the number of inspection target circuits 11 (11-1 to 11-n) having an abnormality is displayed on the display unit 19 along with the occurrence of the abnormality, the inspection target circuit 11 (11-1 to 11-1 to 11-1 to 11-n) is displayed. It is possible to know the occurrence of the abnormality 11-n) and the number of the inspection target circuits 11 (11-1 to 11-n) in which the abnormality has occurred.

前記した異常検出装置１０では、並行試験回路１２を構成する各試験単位回路部１６の検査対象回路１１（１１−１〜１１−ｎ）の例えば断線による異常によって、図２に示すように、並行試験回路１２の抵抗値が階段状に変化することから、異常を生じる検査対象回路１１の数が２個、３個…と増加するに従い、異常が発生した時点で抵抗値は順次階段状に値が変化する。この階段状に変化した時点が並行試験回路１２のいずれかの試験単位回路部１６の寿命を示す。   In the abnormality detection apparatus 10 described above, as shown in FIG. 2, the parallel test circuit 11 includes a parallel test circuit 12 due to an abnormality caused by, for example, disconnection of the test target circuit 11 (11-1 to 11-n). Since the resistance value of the test circuit 12 changes in a staircase pattern, the resistance value sequentially increases in a staircase pattern when the abnormality occurs as the number of test target circuits 11 that cause an abnormality increases to 2, 3,. Changes. The point of time when the step changes is the life of one of the test unit circuit units 16 of the parallel test circuit 12.

従って、異常検出装置１０を用いた並行試験回路１２のモニタリング試験により、並行試験回路１２の抵抗値の階段状の変化を読み取り、この変化した時点を順次記録していくことで、例えば寿命診断に用いられるワイブル解析などが可能になる。   Therefore, by reading the stepwise change in the resistance value of the parallel test circuit 12 by the monitoring test of the parallel test circuit 12 using the abnormality detection device 10, and sequentially recording the time points of the change, for example, for life diagnosis. The Weibull analysis used can be performed.

また、並行試験回路１２の抵抗値が変化した時点間の時間を測定することで、異常が生じた時間または温度サイクル試験でのサイクル数を測定することができる。   Further, by measuring the time between the time points when the resistance value of the parallel test circuit 12 changes, it is possible to measure the time when the abnormality occurred or the number of cycles in the temperature cycle test.

前記したように、試験単位回路部１６毎の異常を明確に判定する上で、総ての検査対象回路１１（１１−１〜１１−ｎ）が正常な状態で各試験単位回路部１６が等しい抵抗値を示すように、しかも前記式（１）を満たすように、各検査対象回路１１（１１−１〜１１−ｎ）の抵抗値のばらつきに応じて適正な抵抗値を示す補助抵抗１５（１５−１〜１５−ｎ）が選定される。このような補助抵抗１５（１５−１〜１５−ｎ）を用いることにより、検査対象回路１１（１１−１〜１１−ｎ）の抵抗値のばらつきの如何に拘わらず、各検査対象回路１１（１１−１〜１１−ｎ）の異常を検出することができる。   As described above, when the abnormality for each test unit circuit unit 16 is clearly determined, each test unit circuit unit 16 is equal in a state where all the test target circuits 11 (11-1 to 11-n) are normal. The auxiliary resistor 15 (showing an appropriate resistance value according to the variation in the resistance value of each circuit under test 11 (11-1 to 11-n) so as to show the resistance value and to satisfy the equation (1). 15-1 to 15-n) are selected. By using such auxiliary resistors 15 (15-1 to 15-n), regardless of variations in resistance values of the inspection target circuits 11 (11-1 to 11-n), each inspection target circuit 11 ( 11-1 to 11-n) can be detected.

しかしながら、検査対象回路１１（１１−１〜１１−ｎ）が相互にほぼ等しい抵抗値を示し、かつ検査対象回路１１（１１−１〜１１−ｎ）のみで式（１）が満たされる場合、図３に示すように、検査対象回路１１（１１−１〜１１−ｎ）のみで各試験単位回路部１６を構成し、補助抵抗１５（１５−１〜１５−ｎ）を不要とすることができる。   However, when the test target circuits 11 (11-1 to 11-n) exhibit substantially equal resistance values and the formula (1) is satisfied only by the test target circuits 11 (11-1 to 11-n), As shown in FIG. 3, each test unit circuit unit 16 is configured only by the circuit under test 11 (11-1 to 11-n), and the auxiliary resistor 15 (15-1 to 15-n) is unnecessary. it can.

また、図１及び図３に示した例では、試験単位回路部１６を相互に並列接続した例を示したが、図４に示すように、互いに等しい抵抗値を示す各試験単位回路部１６を相互に直列接続することができる。図４の例では、各検査対象回路１１（１１−１〜１１−ｎ）に補助抵抗１５（１５−１〜１５−ｎ）が並列に接続されて各試験単位回路部１６が構成されている。   In the example shown in FIGS. 1 and 3, the test unit circuit units 16 are connected in parallel to each other. However, as shown in FIG. 4, the test unit circuit units 16 having the same resistance value are connected to each other. They can be connected in series with each other. In the example of FIG. 4, each test unit circuit unit 16 is configured by connecting the auxiliary resistors 15 (15-1 to 15-n) in parallel to the circuits to be tested 11 (11-1 to 11-n). .

図４に示す例では、例えば検査対象回路１１（１１−１〜１１−ｎ）が、前記したと同様に、例えば正常時に抵抗値を持ち、異常時に断線状態になるような回路である場合、異常を生じた検査対象回路１１（１１−１〜１１−ｎ）の抵抗値は上昇する。具体的には、完全に断線するような故障を生じる検査対象回路１１（１１−１〜１１−ｎ）が用いられた場合、正常な状態の試験単位回路部１６の抵抗値は、検査対象回路１１（１１−１〜１１−ｎ）とこれに並列接続された補助抵抗１５（１５−１〜１５−ｎ）との並列回路の抵抗値となるが、異常を生じた試験単位回路部１６では、断線によって検査対象回路１１（１１−１〜１１−ｎ）が失われたものと等しくなるために、補助抵抗１５（１５−１〜１５−ｎ）の抵抗値と等しくなる。   In the example shown in FIG. 4, for example, when the circuit to be inspected 11 (11-1 to 11-n) is a circuit that has a resistance value in a normal state and is in a disconnected state in an abnormal state, for example, The resistance value of the inspection target circuit 11 (11-1 to 11-n) in which the abnormality has occurred increases. Specifically, when the test target circuit 11 (11-1 to 11-n) that causes a failure that is completely disconnected is used, the resistance value of the test unit circuit unit 16 in a normal state is the test target circuit. 11 (11-1 to 11-n) and auxiliary resistance 15 (15-1 to 15-n) connected in parallel to the resistance value of the parallel circuit. Since the circuit under test 11 (11-1 to 11-n) is lost due to disconnection, it becomes equal to the resistance value of the auxiliary resistor 15 (15-1 to 15-n).

従って、互いに直列接続された試験単位回路部１６からなる並行試験回路１２の両端子１２ａ、１２ａ間の電気抵抗値を情報処理装置１４でモニタリングすることにより、並行試験回路１１の検査対象回路１１（１１−１〜１１−ｎ）の異常の発生あるいは異常を生じた個数を知ることができる。   Therefore, by monitoring the electrical resistance value between the terminals 12a and 12a of the parallel test circuit 12 including the test unit circuit units 16 connected in series with each other by the information processing device 14, the test target circuit 11 ( It is possible to know the occurrence of the abnormality 11-1 to 11-n) or the number of the abnormality.

また、互いに直列接続された試験単位回路部１６からなる並行試験回路１２の場合においても、式（１）を満たすように補助抵抗１５（１５−１〜１５−ｎ）を選択することにより、異常発生時の並行試験回路１２の抵抗値を階段状に明確に変化させることができる。   Further, even in the case of the parallel test circuit 12 including the test unit circuit units 16 connected in series with each other, by selecting the auxiliary resistor 15 (15-1 to 15-n) so as to satisfy the formula (1), an abnormality is caused. The resistance value of the parallel test circuit 12 at the time of occurrence can be clearly changed stepwise.

図５は、検査対象回路１１（１１−１〜１１−ｎ）の一例を示す概略図である。図５には、回路基板２０の配線に接続された電気抵抗器２１からなる検査対象回路１１と、回路基板２０上で電気抵抗器２１に接続された表面実装用抵抗体２２からなる補助抵抗１５とで構成される試験単位回路部１６が示されている。   FIG. 5 is a schematic diagram illustrating an example of the inspection target circuit 11 (11-1 to 11-n). In FIG. 5, a test target circuit 11 including an electrical resistor 21 connected to the wiring of the circuit board 20 and an auxiliary resistor 15 including a surface mounting resistor 22 connected to the electrical resistor 21 on the circuit board 20 are illustrated. A test unit circuit unit 16 is shown.

このような試験単位回路部１６が温度サイクル試験を受けるとき、補助抵抗１５は熱応力を生じ難く、検査対象回路１１に比較して充分に長い寿命を持つものが用いられる。この点で、表面実装用抵抗体２２は、１．０ｍｍ×０．５ｍｍの大きさのものを用いることが望ましい。このサイズの表面実装用抵抗体２２は、このタイプで最も小型であることから、熱膨張の影響を受け難く、長寿命である。表面実装用抵抗体２２に代えて、リード線を有するタイプの抵抗体あるいは回路基板２０と同一の熱線膨張係数を有する抵抗体を用いることができる。   When such a test unit circuit section 16 undergoes a temperature cycle test, the auxiliary resistor 15 is less likely to generate thermal stress and has a sufficiently long life compared to the circuit under test 11. In this respect, it is desirable to use a surface mounting resistor 22 having a size of 1.0 mm × 0.5 mm. Since the surface mounting resistor 22 of this size is the smallest in this type, it is hardly affected by thermal expansion and has a long life. Instead of the surface mounting resistor 22, a resistor having a lead wire or a resistor having the same thermal expansion coefficient as the circuit board 20 can be used.

また、各試験単位回路部１６の前記許容差が試験温度範囲の抵抗値変化分を含むように、その抵抗値が選定される。このような温度変化による抵抗値変化分を考慮することにより、試験単位回路部１６の正常及び異常時における並行試験回路１２の抵抗値変化量に温度変化の誤差を超える差分を生じさせることができる。   Further, the resistance value is selected so that the tolerance of each test unit circuit unit 16 includes a change in the resistance value in the test temperature range. By taking into account such a change in resistance value due to a temperature change, a difference exceeding the temperature change error can be generated in the resistance value change amount of the parallel test circuit 12 when the test unit circuit unit 16 is normal or abnormal. .

検査対象回路１１である電気抵抗器２１の異常の有無を確実に検出するために、補助抵抗１５である表面実装用抵抗体２２は電気抵抗器２１よりも耐久性に優れ、長寿命を示すものが用いられる。   In order to reliably detect the presence or absence of an abnormality in the electrical resistor 21 that is the circuit to be inspected 11, the surface mounting resistor 22 that is the auxiliary resistor 15 is more durable than the electrical resistor 21 and exhibits a long life. Is used.

また、電気抵抗器２１が、図５に示すように、抵抗器本体２１ａと、該抵抗器本体から伸長する一対のリード端子２１ｂとからなり、該リード端子が回路基板２０の配線への接合部分２１ｃで回路基板２０に接続されているとき、抵抗器本体２１ａの耐久性の試験では、接合部分２１ｃに抵抗器本体２１ａの耐久性よりも高い耐久性が要求される。例えば、高湿度における抵抗器本体２１ａの耐久性試験の場合、イオンマイグレーション等によるリード端子に関連する短絡が発生しない程度に接合部２１ｃを近傍の配線部と十分に離された位置に設けることで、接合部分２１ｃでの耐湿性を高めて該接合部分での耐久性を抵抗器本体２１ａのそれよりも高めることができる。   Further, as shown in FIG. 5, the electrical resistor 21 includes a resistor main body 21 a and a pair of lead terminals 21 b extending from the resistor main body, and the lead terminals are joined portions to the wiring of the circuit board 20. When connected to the circuit board 20 at 21c, in the durability test of the resistor main body 21a, durability higher than the durability of the resistor main body 21a is required for the joint portion 21c. For example, in the case of a durability test of the resistor main body 21a in high humidity, by providing the joint portion 21c at a position sufficiently separated from the nearby wiring portion to such an extent that a short circuit related to the lead terminal due to ion migration or the like does not occur. The moisture resistance at the joint portion 21c can be increased, and the durability at the joint portion can be increased more than that of the resistor body 21a.

他方、電気抵抗器２１の接合部分２１ｃの高温試験の場合、接合部分２１ｃに比較して抵抗器本体２１ａにより高い耐久性が要求される。この場合、検査対象回路１１に、試験温度範囲が動作温度範囲となるような抵抗器本体２１ａを有する電気抵抗器２１が選定される。   On the other hand, in the case of a high-temperature test of the joint portion 21c of the electrical resistor 21, higher durability is required for the resistor body 21a than the joint portion 21c. In this case, an electrical resistor 21 having a resistor main body 21a whose test temperature range is the operating temperature range is selected as the inspection target circuit 11.

前記した検査対象回路１１（１１−１〜１１−ｎ）を静電容量を有する回路で構成することができる。この回路は、正常な状態が開放状態で、故障などによって導通状態に至る回路例の一つである。   The inspection target circuit 11 (11-1 to 11-n) can be configured by a circuit having a capacitance. This circuit is one of circuit examples in which a normal state is an open state and a conductive state is brought about by a failure or the like.

検査対象回路１１（１１−１〜１１−ｎ）がコンデンサなどの静電容量を持つ素子で構成される場合、検査対象回路１１（１１−１〜１１−ｎ）は、正常状態では、直流電源を有する抵抗測定器に対しては断線状態を示す。しかしながら、抵抗測定器１３に、例えばＬＣＲメータのように交流で計測する計器を用いることにより、静電容量の等価直列抵抗を計測することができる。このような静電容量は、短絡のような異常を生じると、その等価抵抗値が急激に低下する。   When the inspection target circuit 11 (11-1 to 11-n) is configured by an element having a capacitance such as a capacitor, the inspection target circuit 11 (11-1 to 11-n) is a DC power supply in a normal state. For a resistance measuring instrument having However, the equivalent series resistance of the electrostatic capacitance can be measured by using an instrument that measures the resistance with the alternating current such as an LCR meter. When an abnormality such as a short circuit occurs in such a capacitance, the equivalent resistance value rapidly decreases.

従って、電気抵抗器２１のような抵抗素子からなる検査対象回路１１とは逆に、静電容量を有する検査対象回路１１（１１−１〜１１−ｎ）からなる並行試験回路１２では、各検査対象回路１１が正常時には比較的高い抵抗値を示し、いずれかの検査対象回路１１（１１−１〜１１−ｎ）に異常が生じると、並行試験回路１２の抵抗値は急激に低下する。そのため、この抵抗値の変化を情報処理装置１４で処理することにより、電気抵抗器２１を有する検査対象回路１１（１１−１〜１１−ｎ）におけると同様に、検査対象回路１１（１１−１〜１１−ｎ）の異常の発生及びその個数を検出することができる。   Therefore, in contrast to the test target circuit 11 made of a resistance element such as the electrical resistor 21, the parallel test circuit 12 made of the test target circuit 11 (11-1 to 11-n) having capacitance has each test. When the target circuit 11 is normal, it exhibits a relatively high resistance value, and when an abnormality occurs in any of the inspection target circuits 11 (11-1 to 11-n), the resistance value of the parallel test circuit 12 rapidly decreases. Therefore, by processing the change in the resistance value by the information processing device 14, as in the inspection target circuit 11 (11-1 to 11-n) having the electrical resistor 21, the inspection target circuit 11 (11-1). The occurrence and number of abnormalities of ˜11-n) can be detected.

検査対象回路１１（１１−１〜１１−ｎ）が静電容量を有する場合、各検査対象回路１１の等価直列抵抗値がこれに接続される補助抵抗１５（１５−１〜１５−ｎ）の抵抗値よりも充分に小さくなり、各試験単位回路部１６の合成抵抗値が等しくなり、しかも式（１）を満たすように、各補助抵抗１５（１５−１〜１５−ｎ）が選定される。   When the test target circuit 11 (11-1 to 11-n) has a capacitance, the equivalent series resistance value of each test target circuit 11 is the auxiliary resistor 15 (15-1 to 15-n) connected thereto. Each auxiliary resistor 15 (15-1 to 15-n) is selected so as to be sufficiently smaller than the resistance value, the combined resistance value of each test unit circuit unit 16 becomes equal, and the expression (1) is satisfied. .

図６は本発明に係る他の異常検出方法を実施する他の異常検出装置を概略的に示すブロック図である。   FIG. 6 is a block diagram schematically showing another abnormality detection apparatus for implementing another abnormality detection method according to the present invention.

図６に示す異常検出装置１１０は、実施例１におけると同様な複数の検査対象回路１１（１１−１〜１１−ｎ）を含む並行試験回路１１２の両端子１２ａ、１２ａの間の電気抵抗値を測定する抵抗測定器１３と、該抵抗測定器により得られた抵抗値データを処理するパーソナルコンピュータのような情報処理装置１４とを備える。   The abnormality detection apparatus 110 shown in FIG. 6 has an electrical resistance value between both terminals 12a and 12a of a parallel test circuit 112 including a plurality of test target circuits 11 (11-1 to 11-n) similar to that in the first embodiment. A resistance measuring device 13 for measuring the resistance value, and an information processing device 14 such as a personal computer for processing resistance value data obtained by the resistance measuring device.

各検査対象回路１１（１１−１〜１１−ｎ）は、正常時に互いに異なる抵抗値を持ち、異常時に断線や回路の抵抗値が急激に上昇する前記したと同様な抵抗回路である。この抵抗回路に代えて、実施例２でも、正常な状態が開放状態で、故障などによって導通状態に至る前記した静電回路を適用することができるが、以下では、検査対象回路１１が抵抗体である例に沿って説明する。   Each of the inspection target circuits 11 (11-1 to 11-n) is a resistance circuit similar to that described above, which has a resistance value different from each other at the normal time, and the resistance value of the disconnection or the circuit rapidly increases at the time of the abnormality. In place of this resistance circuit, the electrostatic circuit described in the second embodiment can be applied in which the normal state is an open state and becomes conductive due to a failure or the like. It demonstrates along the example which is.

各検査対象回路１１（１１−１〜１１−ｎ）は、図１に示した例におけると同様に、それぞれに直列に補助抵抗１５（１５−１〜１５−ｎ）が接続されている。互いに直列接続された各検査対象回路１１（１１−１〜１１−ｎ）及び補助抵抗１５（１５−１〜１５−ｎ）は、試験単位回路部１１６を構成し、該試験単位回路部の並列接続により並行試験回路１１２が構成されている。しかしながら、試験単位回路部１１６はそれぞれ異なる抵抗値を示すように、各補助抵抗１５（１５−１〜１５−ｎ）が選定されている点で、実施例１と異なる。   Each inspection target circuit 11 (11-1 to 11-n) is connected to an auxiliary resistor 15 (15-1 to 15-n) in series as in the example shown in FIG. The test target circuits 11 (11-1 to 11-n) and the auxiliary resistors 15 (15-1 to 15-n) connected in series constitute a test unit circuit unit 116, and the test unit circuit units are connected in parallel. The parallel test circuit 112 is configured by the connection. However, the test unit circuit unit 116 is different from the first embodiment in that each auxiliary resistor 15 (15-1 to 15-n) is selected so as to show different resistance values.

すなわち、全ての検査対象回路１１（１１−１〜１１−ｎ）が正常な状態では、各試験単位回路部１１６の合成抵抗は相互に異なるように、各検査対象回路１１（１１−１〜１１−ｎ）の抵抗値に応じて選定されている。   That is, when all the test target circuits 11 (11-1 to 11-n) are in a normal state, the test target circuits 11 (11-1 to 11-11) are different so that the combined resistances of the test unit circuit units 116 are different from each other. -N) is selected according to the resistance value.

また、並行試験回路１１２の各試験単位回路部１１６のうち、ある一つの試験単位回路部１１６が異常であるときの並行試験回路１１２の第２の合成抵抗値Ｒ0′と、一つの前記試験単位回路部１１６に加えて他の一つの試験単位回路部１１６が異常を生じたときの並行試験回路１１２の第３の合成抵抗値Ｒ0′′と、測定器１３の許容差と試験単位回路部１１６の許容差との和で示される合計許容差αとの間に次式（２） Further, among the test unit circuit units 116 of the parallel test circuit 112, the second combined resistance value R 0 ′ of the parallel test circuit 112 when one test unit circuit unit 116 is abnormal, and the one test The third combined resistance value R 0 ″ of the parallel test circuit 112 when an abnormality occurs in the other test unit circuit unit 116 in addition to the unit circuit unit 116, the tolerance of the measuring instrument 13, and the test unit circuit Between the total tolerance α indicated by the sum of the tolerance of the unit 116 and the following expression (2)

｜Ｒ0′−Ｒ0′′｜／（Ｒ0′＋Ｒ0′′）＞α …（２）
が成り立つように、設定されている。 | R 0 ′ −R 0 ′ | / (R 0 ′ + R 0 ′)> α (2)
Is set to hold.

式（２）は、並行試験回路１１２のうちの任意の一つの試験単位回路部１１６が異常を生じたとき、すなわち任意の一つの試験単位回路部１１６の検査対象回路１１（１１−１〜１１−ｎ）に異常が生じた場合に成り立つ。   Expression (2) is obtained when any one of the test unit circuit units 116 of the parallel test circuits 112 has an abnormality, that is, the inspection target circuit 11 (11-1 to 11-11) of any one test unit circuit unit 116. This holds when an abnormality occurs in -n).

試験単位回路部１１６の抵抗値が相互に異なり、しかも式（２）を満足するように、検査対象回路１１（１１−１〜１１−ｎ）の抵抗値に応じて、該各検査対象回路１１に接続される補助抵抗１５（１５−１〜１５−ｎ）の抵抗値を選定することで、並行試験回路１１２の抵抗値は、異常を生じる試験単位回路部１１６に応じて、異常を生じる前後での並行試験回路１１２の抵抗値変化量が異なる。そのため、情報処理装置１４で並行試験回路１２の抵抗変化量を検知することにより、後述するように、異常を起こした試験単位回路部１１６すなわち異常を起こした検査対象回路１１（１１−１〜１１−ｎ）を知ることができる。   In accordance with the resistance values of the test target circuits 11 (11-1 to 11-n), the test target circuit sections 116 have different resistance values from each other and satisfy Expression (2). By selecting the resistance value of the auxiliary resistor 15 (15-1 to 15-n) connected to the resistance value of the parallel test circuit 112, the resistance value of the parallel test circuit 112 depends on the test unit circuit unit 116 that causes the abnormality. The amount of change in resistance value of the parallel test circuit 112 is different. Therefore, by detecting the resistance change amount of the parallel test circuit 12 by the information processing device 14, as will be described later, the test unit circuit unit 116 that has caused an abnormality, that is, the inspection target circuit 11 that has caused the abnormality (11-1 to 11-11) -N) can be known.

検査対象回路１１（１１−１〜１１−ｎ）の一つに異常が生じると、並行試験回路１１２の抵抗値は、図２に示した例におけると同様に、変化する（Ａ−Ｂ）。この抵抗値の変化について、説明の簡素化のために、補助抵抗１５（１５−１〜１５−ｎ）が用いられない場合に沿って説明する。   When an abnormality occurs in one of the inspection target circuits 11 (11-1 to 11-n), the resistance value of the parallel test circuit 112 changes (AB) as in the example shown in FIG. The change in the resistance value will be described along the case where the auxiliary resistor 15 (15-1 to 15-n) is not used for the sake of simplification.

例えば検査対象回路１１−１に異常が生じる前後での並行試験回路１１２の合成抵抗値の変化を考えると、この検査対象回路１１−１に異常が生じる前、すなわち総ての検査対象回路１１（１１−１〜１１−ｎ）が正常であるときの並行試験回路１１２の合成抵抗値Ｒ0は、図８に示すように、異常を生じる前の正常な検査対象回路１１−１の抵抗値Ｒxと、該検査対象回路１１−１が異常になった後の並行試験回路１１２′の合成抵抗値Ｒ0′との並列合成抵抗で示される。 For example, considering the change in the combined resistance value of the parallel test circuit 112 before and after an abnormality occurs in the inspection target circuit 11-1, before the abnormality occurs in the inspection target circuit 11-1, that is, all the inspection target circuits 11 ( The combined resistance value R 0 of the parallel test circuit 112 when 11-1 to 11-n) is normal is, as shown in FIG. 8, the resistance value R of the normal inspection target circuit 11-1 before the abnormality occurs. It is indicated by a parallel combined resistance of x and a combined resistance value R 0 ′ of the parallel test circuit 112 ′ after the inspection target circuit 11-1 becomes abnormal.

従って、総ての検査対象回路１１（１１−１〜１１−ｎ）が正常であるときの並行試験回路１１２の合成抵抗値Ｒ0と、一つの検査対象回路１１（１１−１〜１１−ｎ）が異常を生じたときの並行試験回路１１２′の合成抵抗値Ｒ0′とを用いて、次式（３）から異常をじた検査対象回路１１の正常（１１−１〜１１−ｎ）な抵抗値Ｒxを求めることができる。 Therefore, the combined resistance value R 0 of the parallel test circuit 112 when all the test target circuits 11 (11-1 to 11-n) are normal and one test target circuit 11 (11-1 to 11-n). ) Is normal (11-1 to 11-n) of the circuit 11 to be inspected from the following equation (3) using the combined resistance value R 0 ′ of the parallel test circuit 112 ′ when the abnormality occurs. A simple resistance value R x can be obtained.

Ｒx ＝Ｒ0′・Ｒ0 ／（Ｒ0′−Ｒ0） …（３）
各検査対象回路１１（１１−１〜１１−ｎ）の抵抗値、すなわち補助抵抗１５が設けられている場合には検査対象回路１１（１１−１〜１１−ｎ）と補助抵抗１５（１５−１〜１５−ｎ）とから成る各試験単位回路部１１６の抵抗値は、相互に異なるように設定されていることから、基本的には、この抵抗値すなわち並行試験回路１１２の抵抗値の変化量を算出することができ、この変化量と後述するメモリ１７に格納された並行試験回路１１２の各抵抗変化量との比較により、いずれの検査対象回路１１（１１−１〜１１−ｎ）が異常を生じたかを知ることができる。以下、並行試験回路１１２に抵抗値変化が生じる毎に、前記したと同様な手順によって、順次異常を生じた検査対象回路１１（１１−１〜１１−ｎ）を特定することができる。 R x = R 0 '· R 0 / (R 0' -R 0) ... (3)
When the resistance value of each of the inspection target circuits 11 (11-1 to 11-n), that is, the auxiliary resistance 15 is provided, the inspection target circuit 11 (11-1 to 11-n) and the auxiliary resistance 15 (15- 1 to 15-n), the resistance values of the test unit circuit sections 116 are set to be different from each other. Therefore, basically, the resistance value, that is, the resistance value of the parallel test circuit 112 is changed. The amount of change can be calculated, and by comparing this change amount with each resistance change amount of the parallel test circuit 112 stored in the memory 17 to be described later, which circuit to be inspected 11 (11-1 to 11-n) It is possible to know whether an abnormality has occurred. Hereinafter, each time the resistance value changes in the parallel test circuit 112, the test target circuits 11 (11-1 to 11-n) in which the abnormality is sequentially generated can be specified by the same procedure as described above.

図９に示すように、各試験単位回路部１１６を検査対象回路１１（１１−１〜１１−ｎ）と補助抵抗１５（１５−１〜１５−ｎ）との並列回路で構成し、試験単位回路部１１６を相互に直列接続することによって並行試験回路１１２を構成することができる。この場合においても、各試験単位回路部１１６の抵抗値が相互に異なりかつ式（２）を満たすように、補助抵抗１５（１５−１〜１５−ｎ）が選定される。   As shown in FIG. 9, each test unit circuit unit 116 is constituted by a parallel circuit of a circuit under test 11 (11-1 to 11-n) and an auxiliary resistor 15 (15-1 to 15-n). The parallel test circuit 112 can be configured by connecting the circuit units 116 in series with each other. Also in this case, the auxiliary resistors 15 (15-1 to 15-n) are selected so that the resistance values of the test unit circuit units 116 are different from each other and satisfy the equation (2).

図９に示した並行試験回路１１２では、例えば一つの検査対象回路１１−１が断線による異常を生じると、該検査対象回路を含む一つの試験単位回路部１１６の抵抗値は、補助抵抗１５−１との合成抵抗値から該補助抵抗１５−１の抵抗値に変化する。すなわち、異常を生じる検査対象回路１１−１を含む試験単位回路部１１６の異常を生じる前の抵抗値Ｒxと、その補助抵抗１５−１の抵抗値ｒXと、異常を生じる前後での検査対象回路１１−１を含む試験単位回路部１１６の抵抗変化量とは、次式（４）で示される関係を有する。 In the parallel test circuit 112 shown in FIG. 9, for example, when one inspection target circuit 11-1 is abnormal due to disconnection, the resistance value of one test unit circuit unit 116 including the inspection target circuit is the auxiliary resistance 15- 1 to the resistance value of the auxiliary resistor 15-1. That is, the resistance value R x before causing abnormal test unit circuit section 116 including a circuit under test 11-1 caused an anomaly, and the resistance value r X of the auxiliary resistor 15-1, resulting in abnormal inspection before and after The resistance change amount of the test unit circuit unit 116 including the target circuit 11-1 has a relationship represented by the following expression (4).

ＲIX＝ｒx 2／（Ｒx＋ｒX） … （４）
従って、式（４）の演算処理により、異常を生じた試験単位回路部１１６を特定することができる。 R IX = r x 2 / (R x + r x ) (4)
Therefore, the test unit circuit unit 116 in which an abnormality has occurred can be specified by the arithmetic processing of the equation (4).

再び図６を参照するに、異常検出装置１１０のメモリ１７には、予め、各試験単位回路部１１６の検査対象回路１１（１１−１〜１１−ｎ）が異常を生じる前後での並行試験回路１１２のそれぞれの電気抵抗値の各変化量が、該変化量を与える異常な検査対象回路１１（１１−１〜１１−ｎ）を含む試験単位回路１１６を特定する情報に関連して格納されており、判定回路１８は、抵抗測定器１３による測定抵抗値の変化分とメモリ１７に格納された前記各変化量との差分を算出する演算処理部１８ａを有し、該演算処理部により求められた前記差分が前記合計許容差α内にあるとき、異常が生じた旨及び当該差分を与えた前記変化量についての前記試験単位回路部を特定する情報を前記表示部に表示させる。   Referring again to FIG. 6, the memory 17 of the abnormality detection device 110 stores, in advance, a parallel test circuit before and after the test target circuit 11 (11-1 to 11-n) of each test unit circuit unit 116 has an abnormality. Each change amount of each of the electrical resistance values 112 is stored in association with information specifying the test unit circuit 116 including the abnormal test target circuit 11 (11-1 to 11-n) that gives the change amount. The determination circuit 18 includes an arithmetic processing unit 18a that calculates a difference between a change amount of the measured resistance value by the resistance measuring device 13 and each of the change amounts stored in the memory 17, and is obtained by the arithmetic processing unit. When the difference is within the total tolerance α, information indicating that an abnormality has occurred and information specifying the test unit circuit unit for the amount of change giving the difference are displayed on the display unit.

すなわち、図６あるいは図８に示す例では、演算処理部１８ａは式（３）を実行し、図９に示す例では演算処理部１８ａは式（４）を実行することにより、並行試験回路１２の抵抗値変化から異常を生じた検査対象回路１１（１１−１〜１１−ｎ）を特定するための抵抗値を求め、この値をメモリ１７に格納された抵抗値データと比較することにより、異常を生じた検査対象回路１１（１１−１〜１１−ｎ）を特定し、その情報を出力部１８ｂから表示部１９に出力する。   That is, in the example shown in FIG. 6 or FIG. 8, the arithmetic processing unit 18a executes the expression (3), and in the example shown in FIG. 9, the arithmetic processing part 18a executes the expression (4). By obtaining a resistance value for specifying the inspection target circuit 11 (11-1 to 11-n) in which an abnormality has occurred from the change in the resistance value, and comparing this value with the resistance value data stored in the memory 17, The inspection target circuit 11 (11-1 to 11-n) in which an abnormality has occurred is specified, and the information is output from the output unit 18b to the display unit 19.

また、メモリ１７に、それぞれの検査対象回路１１（１１−１〜１１−ｎ）が単独で異常を生じた場合から総ての検査対象回路１１に異常を生じた場合まで、異常を生じる各検査対象回路１１（１１−１〜１１−ｎ）の総ての組み合わせにおいて、それぞれの異常発生前後に対応した並行試験回路１２の抵抗値の変化量のデータを格納することができる。この場合、演算処理部１８ａの演算処理により求めた並行試験回路１２の抵抗値の変化量をメモリ１７に予め格納された並行試験回路１２の変化量データと比較することにより、異常を生じる複数の検査対象回路１１（１１−１〜１１−ｎ）をも特定することができる。   Further, in the memory 17, each inspection that causes an abnormality from when each of the inspection target circuits 11 (11-1 to 11-n) has an abnormality to when all the inspection target circuits 11 have an abnormality. In all combinations of the target circuits 11 (11-1 to 11-n), it is possible to store data on the amount of change in the resistance value of the parallel test circuit 12 before and after the occurrence of each abnormality. In this case, the change amount of the resistance value of the parallel test circuit 12 obtained by the calculation process of the calculation processing unit 18a is compared with the change amount data of the parallel test circuit 12 stored in the memory 17 in advance, thereby generating a plurality of abnormalities. The inspection target circuit 11 (11-1 to 11-n) can also be specified.

実施例２においても、各試験単位回路部１１６の前記許容差は試験温度範囲の抵抗値変化分を含むように考慮され、補助抵抗１５（１５−１〜１５−ｎ）は、検査対象回路１１（１１−１〜１１−ｎ）に比較して充分な耐久性を有するものが用いられる。   Also in the second embodiment, the tolerance of each test unit circuit unit 116 is considered to include a change in resistance value in the test temperature range, and the auxiliary resistor 15 (15-1 to 15-n) is included in the circuit under test 11. Those having sufficient durability compared to (11-1 to 11-n) are used.

また、実施例１におけると同様、検査対象回路１１（１１−１〜１１−ｎ）に、実施例１で示したと同様な表面実装用抵抗体２２のような抵抗回路あるいは補助抵抗１５（１５−１〜１５−ｎ）の抵抗値よりも充分に小さな等価抵抗値を示す静電容量を適用することができる。   Further, as in the first embodiment, the circuit under test 11 (11-1 to 11-n) is provided with a resistor circuit such as the surface mounting resistor 22 similar to that shown in the first embodiment or the auxiliary resistor 15 (15- A capacitance showing an equivalent resistance value sufficiently smaller than the resistance value of 1 to 15-n) can be applied.

本発明に係る検出方法を実施する検出装置を概略的に示すブロック図である。It is a block diagram which shows roughly the detection apparatus which implements the detection method which concerns on this invention. 本発明に係る検出装置の抵抗測定器により測定される並行試験回路の抵抗変化の一例を示すグラフである。It is a graph which shows an example of resistance change of the parallel test circuit measured by the resistance measuring device of the detection apparatus which concerns on this invention. 図１に示した並行試験回路の他の例を示すブロック図である。FIG. 3 is a block diagram illustrating another example of the parallel test circuit illustrated in FIG. 1. 図１に示した並行試験回路のさらに他の例を示すブロック図である。FIG. 6 is a block diagram illustrating still another example of the parallel test circuit illustrated in FIG. 1. 試験単位回路部の一例を示す概略図である。It is the schematic which shows an example of a test unit circuit part. 本発明に係る他の検出方法を実施する検出装置を概略的に示すブロック図である。It is a block diagram which shows roughly the detection apparatus which implements the other detection method which concerns on this invention. 異常を生じる前の並行試験回路と、異常を生じた検査対象回路及び該検査対象回路を含む並行試験回路との等価関係を示すブロック図である。It is a block diagram which shows the equivalent relationship of the parallel test circuit before producing abnormality, the test object circuit which produced abnormality, and the parallel test circuit containing this test object circuit. 図６に示した検出装置における並行試験回路の他の例を示すブロック図である。It is a block diagram which shows the other example of the parallel test circuit in the detection apparatus shown in FIG. 図６に示した検出装置における並行試験回路のさらに他の例を示すブロック図である。It is a block diagram which shows the further another example of the parallel test circuit in the detection apparatus shown in FIG. 従来の検出装置を示すブロック図である。It is a block diagram which shows the conventional detection apparatus. 従来の他の検出装置を示すブロック図である。It is a block diagram which shows the other conventional detection apparatus.

符号の説明Explanation of symbols

１０、１１０ 異常検出装置
１１（１１−１〜１１−ｎ） 検査対象回路
１２、１１２ 並行試験回路
１３ 抵抗測定器
１５（１５−１〜１５−ｎ） 補助抵抗
１６、１１６ 試験単位回路部
１７ メモリ
１８ 判定回路
１８ａ 演算処理部
１８ｂ 出力部
１９ 表示部
２０ 回路基板
２１ａ 回路本体部分（抵抗器本体）
２１ｃ 接合部分 DESCRIPTION OF SYMBOLS 10, 110 Abnormality detection apparatus 11 (11-1 to 11-n) Test object circuit 12, 112 Parallel test circuit 13 Resistance measuring device 15 (15-1 to 15-n) Auxiliary resistance 16, 116 Test unit circuit part 17 Memory 18 judgment circuit 18a arithmetic processing unit 18b output unit 19 display unit 20 circuit board 21a circuit body part (resistor body)
21c Joint part

Claims (21)

ほぼ等しい電気抵抗値を示す複数の試験単位回路部が互いに接続されてなる並行試験回路の電気抵抗値を測定し、当該測定値に基づいて前記試験単位回路部の異常の発生を検出する方法であって、電気抵抗の測定許容差及び前記試験単位回路部の許容差の和で示される合計許容差αと前記並行試験回路の電気抵抗測定値の変化分とを比較し、前記測定値の変化分が前記合計許容差αを超えると前記試験単位回路部に異常が発生したと判定することを特徴とする、電気回路のための異常検出方法。   A method of measuring an electrical resistance value of a parallel test circuit in which a plurality of test unit circuit units having substantially the same electrical resistance value are connected to each other, and detecting the occurrence of an abnormality in the test unit circuit unit based on the measured value The total tolerance α indicated by the sum of the tolerance of the electrical resistance and the tolerance of the test unit circuit unit is compared with the change in the measured electrical resistance of the parallel test circuit, and the change in the measured value An abnormality detection method for an electric circuit, wherein when the minute exceeds the total tolerance α, it is determined that an abnormality has occurred in the test unit circuit unit. 前記試験単位回路部の全てが正常な状態での前記並行試験回路の第１の合成抵抗値Ｒ0と、ある一つの前記試験単位回路部が異常を生じたときの前記並行試験回路の第２の合成抵抗値Ｒ′0と、前記測定器の許容差及び前記試験単位回路部の許容差の和で示される合計許容差αとの間に次式
｜Ｒ0′−Ｒ0｜／（Ｒ0′＋Ｒ0）＞α
が成り立つように前記試験単位回路部を選定し、前記並行試験回路の電気抵抗値の段階的な変化を検出することにより、前記試験単位回路部の異常の発生を検出することを特徴とする請求項１に記載の異常検出方法。 The first combined resistance value R 0 of the parallel test circuit when all of the test unit circuit units are normal, and the second of the parallel test circuit when an abnormality occurs in one of the test unit circuit units. Between the combined resistance value R ′ 0 and the total tolerance α indicated by the sum of the tolerance of the measuring instrument and the tolerance of the test unit circuit section:
| R 0 ′ −R 0 | / (R 0 ′ + R 0 )> α
The test unit circuit unit is selected so that the following holds, and the occurrence of an abnormality in the test unit circuit unit is detected by detecting a step change in the electrical resistance value of the parallel test circuit. Item 6. The abnormality detection method according to Item 1. 予め、前記各試験単位回路部が異常を生じる前後での前記並行試験回路のそれぞれの抵抗値の変化量を異常であると仮想した前記試験単位回路部の個数に関係付けて求め、前記測定値が変化したとき該測定値の変化分を予め求められた前記各抵抗値の変化量と比較し、この比較に基づいて異常を生じた試験単位回路部の個数を特定することを特徴とする請求項１または２に記載の異常検出方法。   In advance, the amount of change in the resistance value of each parallel test circuit before and after each test unit circuit unit is abnormal is obtained in relation to the number of test unit circuit units that are assumed to be abnormal, and the measured value The amount of change in the measured value is compared with the amount of change in the respective resistance values obtained in advance, and the number of test unit circuit portions having an abnormality is specified based on the comparison. Item 3. An abnormality detection method according to Item 1 or 2. それぞれの前記試験単位回路部は検査対象回路と該検査対象回路に直列に接続された補助抵抗とからなり、前記試験単位回路部毎の合成電気抵抗が等しくなるように、前記各補助抵抗が直列接続される前記各検査対象回路の抵抗値に応じて前記各補助抵抗の抵抗値が選定されることを特徴とする請求項１乃至３のいずれか一つに記載の異常検出方法。   Each of the test unit circuit units includes a circuit to be inspected and an auxiliary resistor connected in series to the circuit to be inspected, and the auxiliary resistors are connected in series so that the combined electric resistances of the test unit circuit units are equal. 4. The abnormality detection method according to claim 1, wherein a resistance value of each auxiliary resistor is selected according to a resistance value of each circuit to be inspected to be connected. それぞれの前記試験単位回路部は検査対象回路と該検査対象回路に並列に接続された補助抵抗とからなり、前記試験単位回路部毎の合成電気抵抗が等しくなるように、前記各補助抵抗が並列接続される前記各検査対象回路の抵抗値に応じて前記各補助抵抗が選定されることを特徴とする請求項１乃至３のいずれか一つに記載の異常検出方法。   Each of the test unit circuit units includes a circuit to be inspected and an auxiliary resistor connected in parallel to the circuit to be inspected, and the auxiliary resistors are connected in parallel so that the combined electric resistance of each test unit circuit unit is equal. 4. The abnormality detection method according to claim 1, wherein each auxiliary resistor is selected according to a resistance value of each circuit to be inspected to be connected. 電気抵抗値を互いに異にする複数の試験単位回路部が互いに接続されてなる並行試験回路の電気抵抗値を測定し、当該測定値に基づいて前記試験単位回路部の異常の発生を検出する方法であって、予め、前記各試験単位回路部が異常を生じる前後での前記並行試験回路のそれぞれの抵抗値の変化量を異常が生じたと仮想した前記試験単位回路部に関係付けて求め、前記測定値が変化したとき該測定値の変化分を予め求められた前記各抵抗値の変化量と比較し、この比較に基づいて異常を生じたのがいずれの前記試験回路部であるかを判定することを特徴とする、電気回路のための異常検出方法。   A method of measuring an electrical resistance value of a parallel test circuit in which a plurality of test unit circuit units having different electrical resistance values are connected to each other, and detecting occurrence of an abnormality in the test unit circuit unit based on the measured value Then, in advance, the amount of change in the resistance value of each of the parallel test circuits before and after each test unit circuit unit is abnormal is obtained in relation to the test unit circuit unit hypothesized that the abnormality has occurred, When the measured value changes, the amount of change in the measured value is compared with the amount of change in each resistance value obtained in advance, and based on this comparison, it is determined which test circuit unit caused the abnormality. An anomaly detection method for an electrical circuit, characterized by: ある一つの前記試験単位回路部が異常であるときの前記並行試験回路の第２の合成抵抗値Ｒ0′と、前記一つの試験単位回路部に加えて他の一つの前記試験単位回路部が異常を生じたときの前記並行試験回路の第３の合成抵抗値Ｒ0′′と、前記測定器の許容差と前記試験単位回路部の許容差との和で示される合計許容差αとの間に次式
｜Ｒ0′−Ｒ0′′｜／（Ｒ0′＋Ｒ0′′）＞α
が成り立つように前記試験単位回路部を選定し、前記並行試験回路の電気抵抗値の段階的な変化を検出することにより、前記試験単位回路部の異常の発生を検出することを特徴とする請求項６に記載の異常検出方法。 A second combined resistance value R 0 ′ of the parallel test circuit when one of the test unit circuit units is abnormal, and another test unit circuit unit in addition to the one test unit circuit unit A third combined resistance value R 0 ″ of the parallel test circuit when an abnormality occurs, and a total tolerance α indicated by the sum of the tolerance of the measuring instrument and the tolerance of the test unit circuit section The following formula
| R 0 ′ −R 0 ′ | / (R 0 ′ + R 0 ′)> α
The test unit circuit unit is selected so that the following holds, and the occurrence of an abnormality in the test unit circuit unit is detected by detecting a step change in the electrical resistance value of the parallel test circuit. Item 7. The abnormality detection method according to Item 6. それぞれの前記試験単位回路部は検査対象回路と該検査対象回路に直列に接続された補助抵抗からなり、前記試験単位回路部毎に重み付を与え、これにより前記各試験単位回路部の合成電気抵抗が段階的に変化するように、前記各補助抵抗が直列接続される前記各検査対象回路の抵抗値に応じて前記各補助抵抗が選定されることを特徴とする請求項６または７に記載の異常検出方法。   Each of the test unit circuit units includes a test target circuit and an auxiliary resistor connected in series to the test target circuit, and gives weight to each test unit circuit unit. 8. The auxiliary resistors according to claim 6 or 7, wherein the auxiliary resistors are selected in accordance with a resistance value of each circuit to be inspected to which the auxiliary resistors are connected in series so that the resistance changes stepwise. Anomaly detection method. それぞれの前記試験単位回路部は検査対象回路と該検査対象回路に並列に接続された補助抵抗とからなり、前記試験単位回路部毎に重み付けを与え、これにより前記各試験単位回路部毎の合成電気抵抗が段階的に変化するように、前記各補助抵抗が並列接続される前記各検査対象回路の抵抗値に応じて前記各補助抵抗が選定されることを特徴とする請求項６または７に記載の異常検出方法。   Each of the test unit circuit units includes a test target circuit and an auxiliary resistor connected in parallel to the test target circuit, and assigns a weight to each test unit circuit unit, thereby combining each test unit circuit unit. 8. The auxiliary resistances according to claim 6 or 7, wherein the auxiliary resistances are selected according to a resistance value of each of the circuits to be inspected to which the auxiliary resistances are connected in parallel so that the electric resistance changes stepwise. The abnormality detection method described. 前記試験単位回路部は静電容量を有し、該静電容量の等価抵抗値がこれに接続された前記補助抵抗の抵抗値よりも小さいことを特徴とする請求項４、５、８または９のいずれか一つに記載の異常検出方法。   The test unit circuit unit has a capacitance, and an equivalent resistance value of the capacitance is smaller than a resistance value of the auxiliary resistor connected thereto. The abnormality detection method according to any one of the above. 前記補助抵抗は、前記検査対象回路に比較して充分な耐久性を有することを特徴とする請求項４、５、８、９または１０のいずれか一つに記載の異常検出方法。   The abnormality detection method according to claim 4, wherein the auxiliary resistor has sufficient durability as compared with the circuit to be inspected. 前記試験単位回路部の前記許容差は、試験温度範囲の抵抗値変化分を含む請求項１または６に記載の異常検出方法。   The abnormality detection method according to claim 1, wherein the tolerance of the test unit circuit unit includes a change in resistance value in a test temperature range. 前記試験単位回路部の前記検査対象回路は、回路本体部分と該本体部分から伸び、回路基板に接続される接合部分とを有し、前記接合部分と前記基板との接合部における耐久性は前記回路本体部分におけるそれよりも優れていることを特徴とする請求項４、５、８または９のいずれか一つに記載の異常検出方法。   The test target circuit of the test unit circuit portion includes a circuit body portion and a joint portion that extends from the body portion and is connected to a circuit board, and durability at the joint portion between the joint portion and the substrate is 10. The abnormality detection method according to claim 4, wherein the abnormality detection method is superior to that in the circuit body portion. 前記試験単位回路部の前記検査対象回路は、回路本体部分と該本体部分から伸び、回路基板に接続される接合部分とを有し、前記回路本体部分における耐久性は前記接合部分と前記基板との接合部におけるそれよりも優れていることを特徴とする請求項４、５、８または９のいずれか一つに記載の異常検出方法。   The test target circuit of the test unit circuit portion includes a circuit body portion and a joint portion that extends from the body portion and is connected to a circuit board. The durability of the circuit body portion includes the joint portion and the substrate. The abnormality detection method according to any one of claims 4, 5, 8 and 9, wherein the abnormality detection method is superior to that in the joint portion. ほぼ等しい電気抵抗値を示す複数の試験単位回路部が互いに接続されてなる並行試験回路の電気抵抗値を測定する抵抗測定器と、メモリと、前記抵抗測定器により測定された抵抗値に基づいて前記試験単位回路部に異常が生じたか否かを判定する判定回路と、表示部とを備える異常検出装置であって、前記各試験単位回路部は相互に並列又は直列に接続され、前記試験単位回路部の全てが正常な状態での前記並行試験回路の第１の合成抵抗値Ｒ0と、ある一つの前記試験単位回路部が異常を生じたときの前記並行試験回路の第２の合成抵抗値Ｒ′0と、前記測定器の許容差及び前記試験単位回路部の許容差の和で示される合計許容差αとの間に次式
｜Ｒ0′−Ｒ0｜／（Ｒ0′＋Ｒ0）＞α
が成り立ち、前記メモリには、予め、前記各試験単位回路部が異常を生じる前後での前記並行試験回路のそれぞれの電気抵抗値の各変化量が、該変化量を与える異常な試験単位回路の個数に関連して格納されており、前記判定回路は、抵抗測定器による測定抵抗値の変化分と前記メモリに格納された前記各変化量との差分を算出する演算処理部を有し、該演算処理部により求められた前記差分が前記合計許容差α内にあるとき、異常が生じた旨及び当該差分を与えた前記変化量についての前記試験単位回路の個数についての情報を前記表示部に表示させることを特徴とする、電気回路のための異常検出装置。 Based on a resistance measuring device that measures the electrical resistance value of a parallel test circuit in which a plurality of test unit circuit portions that exhibit substantially the same electrical resistance value are connected to each other, a memory, and the resistance value measured by the resistance measuring device An abnormality detection device comprising a determination circuit for determining whether an abnormality has occurred in the test unit circuit unit and a display unit, wherein the test unit circuit units are connected to each other in parallel or in series, and the test unit The first combined resistance value R 0 of the parallel test circuit when all of the circuit units are normal, and the second combined resistance of the parallel test circuit when an abnormality occurs in one of the test unit circuit units Between the value R ′ 0 and the total tolerance α indicated by the sum of the tolerance of the measuring instrument and the tolerance of the test unit circuit section,
| R 0 ′ −R 0 | / (R 0 ′ + R 0 )> α
In the memory, the amount of change in the electrical resistance value of each of the parallel test circuits before and after the occurrence of an abnormality in each test unit circuit unit is stored in advance in the abnormal test unit circuit that gives the change amount. The determination circuit has an arithmetic processing unit that calculates a difference between a change amount of the measured resistance value by the resistance measuring instrument and each change amount stored in the memory, and When the difference obtained by the arithmetic processing unit is within the total tolerance α, information indicating that an abnormality has occurred and the number of test unit circuits for the amount of change that has given the difference are displayed on the display unit. An abnormality detection device for an electric circuit, characterized by displaying. それぞれの前記試験単位回路部は検査対象回路と該検査対象回路に直列に接続された補助抵抗とからなり、前記試験単位回路部毎の合成電気抵抗が等しくなるように、前記補助抵抗が直列接続される前記各検査対象回路抵抗値に応じて前記各補助抵抗の抵抗値が選定されていることを特徴とする請求項１５に記載の異常検出装置。   Each of the test unit circuit units includes a circuit to be inspected and an auxiliary resistor connected in series to the circuit to be inspected, and the auxiliary resistors are connected in series so that the combined electric resistance of each test unit circuit unit is equal. The abnormality detection device according to claim 15, wherein a resistance value of each auxiliary resistor is selected according to the resistance value of each circuit to be inspected. それぞれの前記試験単位回路部は検査対象回路と該検査対象回路に並列に接続された補助抵抗とからなり、前記試験単位回路部毎の合成電気抵抗が等しくなるように、前記各補助抵抗が並列接続される前記各検査対象回路の抵抗値に応じて前記各補助抵抗が選定されていることを特徴とする請求項１５に記載の異常検出装置。   Each of the test unit circuit units includes a circuit to be inspected and an auxiliary resistor connected in parallel to the circuit to be inspected, and the auxiliary resistors are connected in parallel so that the combined electric resistance of each test unit circuit unit is equal. The abnormality detection device according to claim 15, wherein each auxiliary resistor is selected according to a resistance value of each circuit to be inspected to be connected. 電気抵抗値を互いに異にする複数の試験単位回路部が互いに接続されてなる並行試験回路の電気抵抗値を測定する抵抗測定器と、メモリと、前記抵抗測定器により測定された抵抗値に基づいて前記試験単位回路部に異常が生じた否かを判定する判定回路と、表示部とを備える異常検出装置であって、前記各試験単位回路部は相互に並列又は直列に接続され、ある一つの前記試験単位回路部が異常であるときの前記並行試験回路の第２の合成抵抗値Ｒ0′と、前記一つの試験単位回路部に加えて他の一つの前記試験単位回路部が異常を生じたときの前記並行試験回路の第３の合成抵抗値Ｒ0′′と、前記測定器の許容差と前記試験単位回路部の許容差との和で示される合計許容差αとの間に次式
｜Ｒ0′−Ｒ0′′｜／（Ｒ0′＋Ｒ0′′）＞α
が成り立ち、前記メモリには、予め、前記各試験単位回路部が異常を生じる前後での前記並行試験回路のそれぞれの電気抵抗値の各変化量が、該変化量を与える異常な試験単位回路を特定する情報に関連して格納されており、前記判定回路は、前記抵抗測定器による測定抵抗値の変化分と前記メモリに格納された前記各変化量との差分を算出する演算処理部を有し、該演算処理部により求められた前記差分が前記合計許容差α内にあるとき、異常が生じた旨及び当該差分を与えた前記変化量についての前記試験単位回路部を特定する情報を前記表示部に表示させることを特徴とする、電気回路のための異常検出装置。 Based on a resistance measuring device for measuring the electrical resistance value of a parallel test circuit in which a plurality of test unit circuit portions having different electrical resistance values are connected to each other, a memory, and the resistance value measured by the resistance measuring device An abnormality detection device comprising a determination circuit for determining whether an abnormality has occurred in the test unit circuit unit and a display unit, wherein each test unit circuit unit is connected in parallel or in series with each other. The second combined resistance value R 0 ′ of the parallel test circuit when one of the test unit circuit units is abnormal, and another one of the test unit circuit units is abnormal in addition to the one test unit circuit unit. Between the third combined resistance value R 0 ″ of the parallel test circuit when it occurs and the total tolerance α, which is indicated by the sum of the tolerance of the measuring instrument and the tolerance of the test unit circuit section. Next formula
| R 0 ′ −R 0 ′ | / (R 0 ′ + R 0 ′)> α
In the memory, an abnormal test unit circuit in which each change amount of each electrical resistance value of the parallel test circuit before and after each test unit circuit unit is abnormal is given an abnormal amount. The determination circuit has an arithmetic processing unit that calculates a difference between a change amount of the resistance value measured by the resistance measuring instrument and each change amount stored in the memory. When the difference obtained by the arithmetic processing unit is within the total tolerance α, information specifying that the test unit circuit unit is informed that an abnormality has occurred and the amount of change that gave the difference An abnormality detecting device for an electric circuit, characterized by being displayed on a display unit. それぞれの前記試験単位回路部は検査対象回路と該検査対象回路に直列に接続された補助抵抗とからなり、前記試験単位回路部毎に重みを与え、これにより前記各試験単位回路部の合成電気抵抗が段階的に変化するように、前記各補助抵抗が直列接続される前記各検査対象回路抵抗値に応じて前記各補助抵抗の抵抗値が選定されていることを特徴とする請求項１８に記載の異常検出装置。   Each of the test unit circuit units includes a circuit to be inspected and an auxiliary resistor connected in series to the circuit to be inspected, and assigns a weight to each test unit circuit unit. The resistance value of each auxiliary resistor is selected according to the resistance value of each circuit under test to which the auxiliary resistors are connected in series so that the resistance changes stepwise. The abnormality detection device described. それぞれの前記試験単位回路部は検査対象回路と該検査対象回路に並列に接続された補助抵抗とからなり、前記試験単位回路部毎に重みを与え、これにより前記各試験単位回路部の合成電気抵抗が段階的に変化するように、前記各補助抵抗が並列接続される前記各検査対象回路抵抗値に応じて前記各補助抵抗の抵抗値が選定されていることを特徴とする請求項１８に記載の異常検出装置。   Each of the test unit circuit units includes a circuit to be inspected and an auxiliary resistor connected in parallel to the circuit to be inspected, and assigns a weight to each test unit circuit unit. 19. The resistance value of each auxiliary resistor is selected in accordance with the resistance value of each circuit under test to which the auxiliary resistors are connected in parallel so that the resistance changes stepwise. The abnormality detection device described. 前記試験単位回路部は静電容量を有し、該静電容量の等価抵抗値がこれに接続された前記補助抵抗の抵抗値よりも小さいことを特徴とする請求項１６、１７、１９または２０のいずれか一つに記載の異常検出装置。   21. The test unit circuit portion has a capacitance, and an equivalent resistance value of the capacitance is smaller than a resistance value of the auxiliary resistor connected thereto. The abnormality detection device according to any one of the above.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008089680A (en) * 2006-09-29 2008-04-17 Brother Ind Ltd Image forming apparatus and inspecting method therefor
JP2017040629A (en) * 2015-08-21 2017-02-23 学校法人 芝浦工業大学 Electronic component testing device and electronic component testing method
CN113715767A (en) * 2020-05-25 2021-11-30 华晨宝马汽车有限公司 Device for detecting vehicle glass breakage and vehicle

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008089680A (en) * 2006-09-29 2008-04-17 Brother Ind Ltd Image forming apparatus and inspecting method therefor
JP2017040629A (en) * 2015-08-21 2017-02-23 学校法人 芝浦工業大学 Electronic component testing device and electronic component testing method
CN113715767A (en) * 2020-05-25 2021-11-30 华晨宝马汽车有限公司 Device for detecting vehicle glass breakage and vehicle

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