JP2005072419A - 電子部品封止用基板およびそれを用いた電子装置の製造方法 - Google Patents
電子部品封止用基板およびそれを用いた電子装置の製造方法 Download PDFInfo
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- JP2005072419A JP2005072419A JP2003302417A JP2003302417A JP2005072419A JP 2005072419 A JP2005072419 A JP 2005072419A JP 2003302417 A JP2003302417 A JP 2003302417A JP 2003302417 A JP2003302417 A JP 2003302417A JP 2005072419 A JP2005072419 A JP 2005072419A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Micromachines (AREA)
- Wire Bonding (AREA)
Abstract
【解決手段】 一方主面から他方主面または側面に導出された配線導体2が形成された絶縁基板1と、絶縁基板1の一方主面に形成された、配線導体2と接続された接続パッド3と、絶縁基板1の一方主面に、接続パッド3を取り囲むようにして接合された枠部材4と、接続パッド3上に形成された枠部材4と同じ高さの接続端子5と、絶縁基板1中にインダクタ12として形成された導体パターンから成り、半導体基板7の主面に微小電子機械機構8およびこれに接続された電極9が形成された電子部品10が、電極9が接続端子5に接合されるとともに半導体基板7の主面を枠部材4の主面に接合されることによって、枠部材4の内側に微小電子機械機構8が気密封止されている。
【選択図】 図1
Description
2:配線導体
3:接続パッド
4:枠部材
5:接続端子
6:電子部品封止用基板
6a:電子部品封止領域
6b:電子部品封止用基板
7:半導体基板
8:微小電子機械機構
9:電極
10:電子部品
10a:電子部品領域
10b:電子部品
12:インダクタ
Claims (3)
- 一方主面から他方主面または側面に導出された配線導体が形成された絶縁基板と、該絶縁基板の前記一方主面に形成された、前記配線導体と電気的に接続された接続パッドと、前記絶縁基板の前記一方主面に、前記接続パッドを取り囲むようにして接合された枠部材と、前記接続パッド上に形成された、前記枠部材と同じ高さの接続端子と、前記絶縁基板中に形成されたインダクタとしての導体パターンから成り、半導体基板の主面に微小電子機械機構およびこれに電気的に接続された電極が形成されて成る電子部品が、前記電極が前記接続端子に接合されるとともに前記半導体基板の前記主面が前記枠部材の主面に接合されることによって、前記枠部材の内側に前記電子部品の前記微小電子機械機構が気密封止されていることを特徴とする電子部品封止用基板。
- 前記接続パッドおよび前記接続端子が内側に形成された前記枠部材が多数個縦横に配列形成されていることを特徴とする請求項1記載の電子部品封止用基板。
- 半導体基板の主面に、微小電子機械機構およびこれに電気的に接続された電極が形成されて成る電子部品領域を多数個縦横に配列形成した電子部品を準備する工程と、一方主面から他方主面または側面に導出された配線導体が形成された絶縁基板と、該絶縁基板の前記一方主面に形成された、前記配線導体と電気的に接続された接続パッドと、前記絶縁基板の前記一方主面に前記接続パッドを取り囲むようにして接合された枠部材と、前記接続パッド上に形成された、前記枠部材と同じ高さの接続端子とから成る電子部品封止領域を多数個前記電子部品の前記電子部品領域に対応させて配列形成した電子部品封止用基板を準備する工程と、前記電子部品における前記電極を前記接続端子に接合するとともに、前記微小電子機械機構の周囲の前記半導体基板の前記主面を前記枠部材の主面に接合して、前記微小電子機械機構を前記枠部材の内側に気密封止する工程と、互いに接合された前記電子部品および前記電子部品封止用基板を前記電子部品封止領域毎に分割して、前記電子部品封止領域に前記電子部品領域が接合されて成る個々の電子装置を得る工程とを具備することを特徴とする電子装置の製造方法。
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JP2003302417A JP4268480B2 (ja) | 2003-08-27 | 2003-08-27 | 電子部品封止用基板およびそれを用いた電子装置 |
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Cited By (10)
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WO2007058280A1 (ja) * | 2005-11-16 | 2007-05-24 | Kyocera Corporation | 電子部品封止用基板および複数個取り形態の電子部品封止用基板、並びに電子部品封止用基板を用いた電子装置および電子装置の製造方法 |
JP2007149879A (ja) * | 2005-11-25 | 2007-06-14 | Kyocera Corp | 電子部品封止用基板およびそれを用いた電子装置、電子装置の製造方法 |
WO2007074846A1 (ja) * | 2005-12-26 | 2007-07-05 | Kyocera Corporation | 微小電子機械装置およびその製造方法 |
JP2008211806A (ja) * | 2008-03-06 | 2008-09-11 | Seiko Epson Corp | 半導体装置、半導体装置の製造方法、電子部品、回路基板及び電子機器 |
US8004077B2 (en) | 2005-06-08 | 2011-08-23 | Seiko Epson Corporation | Interconnection of land section to wiring layers at center of external connection terminals in semiconductor device and manufacturing thereof |
JP2011182468A (ja) * | 2011-06-09 | 2011-09-15 | Seiko Epson Corp | 半導体装置、半導体装置の製造方法、電子部品、回路基板及び電子機器 |
JP2011211746A (ja) * | 2011-06-09 | 2011-10-20 | Seiko Epson Corp | 半導体装置、半導体装置の製造方法、電子部品、回路基板及び電子機器 |
JP2013080923A (ja) * | 2011-09-30 | 2013-05-02 | General Electric Co <Ge> | 向上した熱散逸能力を有する3d集積電子デバイス構造 |
JP2019071583A (ja) * | 2017-10-11 | 2019-05-09 | 株式会社大真空 | Mems発振器 |
JP2019083440A (ja) * | 2017-10-31 | 2019-05-30 | 株式会社大真空 | Mems発振器 |
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2003
- 2003-08-27 JP JP2003302417A patent/JP4268480B2/ja not_active Expired - Fee Related
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US10361144B2 (en) | 2005-06-08 | 2019-07-23 | Advanced Interconnect Systems Limited | Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus |
US10727166B2 (en) | 2005-06-08 | 2020-07-28 | Advanced Interconnect Systems Limited | Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus |
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US8012864B2 (en) | 2005-06-08 | 2011-09-06 | Seiko Epson Corporation | Manufacturing method for interconnection having stress-absorbing layer between the semiconductor substrate and the external connection terminal |
US8004077B2 (en) | 2005-06-08 | 2011-08-23 | Seiko Epson Corporation | Interconnection of land section to wiring layers at center of external connection terminals in semiconductor device and manufacturing thereof |
US10312182B2 (en) | 2005-06-08 | 2019-06-04 | Advanced Interconnect Systems Limited | Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus |
US10262923B2 (en) | 2005-06-08 | 2019-04-16 | Advanced Interconnect Systems Limited | Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus |
KR100998499B1 (ko) | 2005-11-16 | 2010-12-06 | 쿄세라 코포레이션 | 전자 부품 밀봉용 기판, 복수개 분할 형태의 전자 부품밀봉용 기판, 전자 부품 밀봉용 기판을 사용한 전자 장치,및 전자 장치의 제조 방법 |
WO2007058280A1 (ja) * | 2005-11-16 | 2007-05-24 | Kyocera Corporation | 電子部品封止用基板および複数個取り形態の電子部品封止用基板、並びに電子部品封止用基板を用いた電子装置および電子装置の製造方法 |
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JP2007149879A (ja) * | 2005-11-25 | 2007-06-14 | Kyocera Corp | 電子部品封止用基板およびそれを用いた電子装置、電子装置の製造方法 |
US8008739B2 (en) | 2005-12-26 | 2011-08-30 | Kyocera Corporation | Microelectromechanical apparatus and method for producing the same |
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JP2008211806A (ja) * | 2008-03-06 | 2008-09-11 | Seiko Epson Corp | 半導体装置、半導体装置の製造方法、電子部品、回路基板及び電子機器 |
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JP2011182468A (ja) * | 2011-06-09 | 2011-09-15 | Seiko Epson Corp | 半導体装置、半導体装置の製造方法、電子部品、回路基板及び電子機器 |
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JP2019083440A (ja) * | 2017-10-31 | 2019-05-30 | 株式会社大真空 | Mems発振器 |
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