JP2005061927A - Circuit inspection device, semiconductor integrated circuit, and memory macrocell - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit inspection device, a semiconductor integrated circuit, and a memory macrocell, for circumventing a memory macrocell from stopping propagation of scan data in scan pass testing using a simple circuit. <P>SOLUTION: This circuit inspection device 10 comprises scan FFs 11-15, a selector 16, and signal lines for together connecting respective regions. The scan FFs 11-15 are disposed in parallel with the memory macrocell 20. Signal lines L1-L5 severally branch off to be connected to D terminals of the FFs 11-15, and a clock signal CLK, a write-enable signal WEN, a chip select signal CEN, an input data signal DI, and an address signal A are inputted into the scan FFs 11-15 via the signal lines L1 to L5, respectively. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a circuit inspection device, a semiconductor integrated circuit, and a memory macro cell, and more particularly to a circuit inspection device, a semiconductor integrated circuit, and a memory macro cell for inspecting a failure of a peripheral circuit of a memory by a scan path test.

Conventionally, a scan path test method has been used as a method for inspecting a failure of an integrated circuit.
In the scan path test method, first, in an integrated circuit composed of, for example, a combinational circuit (a circuit that does not include a flip-flop inside) and a sequential circuit (a circuit that includes a flip-flop inside), a flip-flop in the integrated circuit is used. A scan path is created by concatenating the groups like a shift register. Next, a test signal is input from an external terminal of the scan path, and an operation result of the integrated circuit is read out through a flip-flop formed as a shift register to check whether the integrated circuit functions normally.

FIG. 4 is a diagram illustrating an example of a scan path test apparatus in the prior art.
In FIG. 4, eight flip-flops connected to each circuit are serially connected between the input of the scan-in signal (SCAN IN) and the output of the scan-out signal (SCAN OUT).
When a scan clock signal (SCAN CLK) is input to each flip-flop, data from one scan-in signal input side (hereinafter referred to as the previous stage) flip-flop is transferred to one scan-out signal output side (hereinafter referred to as the subsequent stage). Shift to flip-flop. However, the flip-flop on the most scan-in signal input side (hereinafter referred to as the first stage) outputs the input scan-in signal to the subsequent flip-flop, and the flip-flop on the output side of the scan-out signal (hereinafter referred to as the last stage). Outputs data from the previous stage as a scan-out signal.
A comparison circuit (not shown) extracts a scan-out signal from the test apparatus and compares the extracted scan-out signal with the scan-in signal to determine whether or not a failure has occurred in the integrated circuit.

As one of the prior arts using such a scan path test method, there is a testability design support system disclosed in Patent Document 1.
In Patent Document 1, the failure detection rate around the ROM / RAM is improved by using a scan path test method.

Further, in the semiconductor integrated circuit disclosed in Patent Document 2, the circuit configuration is such that the RAM macro is bypassed in the scan test mode, so that writing / reading to the memory cells in the RAM macro is performed during the scan path test. It was possible to omit the processing and facilitate the test pattern of the integrated circuit.
JP 2000-227463 A Japanese Patent Laid-Open No. 10-160801

As shown in FIG. 4, in general, in the scan path test, the data set in the scan FF (flip-flop) circuit is passed to the next-stage scan FF circuit, thereby realizing a fault detection test for the combinational circuit between them. Was.
FIG. 5 is a diagram illustrating an example of an integrated circuit in which failure detection is difficult by the scan path test method.
In this way, when there is a circuit that prevents the propagation of data between the scan FF circuit and the scan FF circuit (FF not supporting scan, macro cell such as memory / CPU, floating signal line, etc.) There was a problem that it was difficult to detect failures in the scan path test.

In ASIC-LSI, as the circuit scale increases, the opportunity to use the memory BIST circuit for the purpose of facilitating the test of the built-in ROM / RAM is increasing.
A memory BIST (Built in Self Test) circuit generally provided by an EDA vendor does not have a capability of detecting a failure of the memory BIST circuit itself, and detects a failure by a scan path test.
FIG. 6 is a diagram illustrating another example of an integrated circuit in which failure detection is difficult by the scan path test method.
In the integrated circuit of FIG. 6, the memory BIST input control circuit and the memory are connected via a selector. The branch of the memory data output and the output of the memory BIST input control circuit are connected to the memory BIST output comparison circuit.
When the BIST enable signal (bist_en) is enabled, the memory BIST input control circuit executes reading and writing to the memory in synchronization with the input BIST clock signal (bist_clk) according to a built-in inspection algorithm.
The memory BIST output comparison circuit compares the data read from the memory with the data written in the memory by the memory BIST input control circuit, determines whether or not they match, and outputs the determination result.
As shown in FIG. 6, it is difficult to detect the failure of the integrated circuit by using the scan path test method in the area before and after the memory cell and in the connection portion between the memory BIST input control circuit and the memory BIST output comparison circuit. there were. In some cases, a circuit such as a multiplexer or a decoder that cannot detect a failure in the scan path test is arranged.
In this case, there has been a problem that failure detection of the memory BIST circuit cannot be sufficiently performed in a scan path test by ATPG (Automatic Test Pattern Generator: automatic test pattern generation tool).
As a result, if the failure detection is not sufficient, a defect cannot be detected in the shipping test. In order to sufficiently detect the failure of the memory BIST circuit, some measures must be taken on the user side, which is a burden on the user.

  Further, in Patent Document 1, there is a possibility that the clock timing adjustment becomes complicated due to the control using the reverse phase clock.

  Further, as in Patent Document 2, if the circuits in the front and rear stages of the memory macro cell are complicated by simply bypassing, there is a possibility that the failure detection rate is difficult to increase.

  The present invention has been made in view of the above problems, and a circuit inspection device, a semiconductor integrated circuit, and a memory that can prevent the propagation of scan data in a memory macro cell during a scan path test with a simple circuit An object is to provide a macro cell.

  In order to achieve such an object, according to the present invention, a scan path including two or more flip-flops connected in cascade is provided, and input signals respectively input to the memory via one or more input signal lines are Input to two or more flip-flops via a signal line branched from the input signal line, and input a test pattern signal to one of the two or more flip-flops connected in cascade. And the test pattern signal is outputted from the flip-flop at the other end.

  Further, according to the present invention, one of the two or more flip-flops is connected to a signal line branched from an input signal line of an input data signal written to the memory among the input signals to the memory and branched. An input data signal input via a signal line is output.

In addition, according to the present invention, it further comprises a selector connected to the output of the data signal from one of the two or more flip-flops and the output of the data signal from the memory,
The selector selectively outputs one of a data signal from one of two or more flip-flops and a data signal from a memory.

  In addition, according to the present invention, a memory to which each input signal is input via one or more input signal lines connected, a circuit inspection device for inspecting a failure of the semiconductor integrated circuit, and a memory via the input signal line A semiconductor integrated circuit having a memory BIST input control circuit for outputting each input signal and a memory BIST output comparison circuit for inspecting data output from the memory, wherein the circuit inspection apparatus has two or more flip-flops connected in cascade Each of the input signals is input to two or more flip-flops via a signal line branched from one or more input signal lines, and two or more flip-flops connected in cascade are provided. The test pattern signal is input to the flip-flop at one end, and the test pattern signal is output from the flip-flop at the other end. .

  Further, according to the present invention, one of the two or more flip-flops is connected to a signal line branched from an input signal line of an input data signal written to the memory among the input signals to the memory and branched. An input data signal input via a signal line is output.

  According to the present invention, there is further provided a selector to which an output of the data signal from one of the two or more flip-flops and an output of the data signal from the memory are connected, and the selector includes the two or more flip-flops. One of the data signal from one of the memory and the data signal from the memory is selectively output.

  Further, according to the present invention, the selector selects an output of a data signal from the memory as an input, and outputs it to the memory BIST output comparison circuit.

  According to the present invention, there is provided a memory macrocell having a memory to which each input signal is input via one or more connected input signal lines, and a circuit inspection device for inspecting a failure of the semiconductor integrated circuit, The circuit inspection apparatus includes a scan path in which two or more flip-flops are cascaded, and each input signal is input to two or more flip-flops via a signal line branched from one or more input signal lines. Of two or more flip-flops connected in cascade, a test pattern signal is input to one end flip-flop, and a test pattern signal is output from the other end flip-flop.

  According to the present invention, it is possible to prevent the propagation of scan data in a memory macro cell during a scan path test with a simple circuit.

A circuit inspection apparatus according to an embodiment of the present invention is a test apparatus that tests whether or not a memory macrocell peripheral circuit has a failure by a scan path test, and executes a test using a scan target FF connected in parallel to the memory macrocell. is there.
The circuit inspection apparatus in the present embodiment can be mounted on OA equipment, AV equipment, communication equipment, PC related equipment, or the like.

FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit in Embodiment 1 of the present invention. Hereinafter, the configuration and operation of the semiconductor integrated circuit in this embodiment will be described with reference to FIG.
The semiconductor integrated circuit includes a circuit inspection device 10 and a memory macrocell 20 (for example, a circuit including a RAM).
The circuit inspection apparatus 10 includes scan flip-flops (hereinafter referred to as scan FFs) 11 to 15, a selector 16, and signal lines that connect the respective parts.
The scan FFs 11 to 15 are arranged in parallel with the memory macro cell 20.

The clock signal CLK, the write enable signal WEN, the chip select signal CEN, the input data signal DI, and the address signal A are respectively sent to the signal lines L1, L2, L3, and L4 by signal input means (not shown) that outputs each signal. , L5, and input to the memory macrocell 20.
The signal lines L1, L2, L3, L4, and L5 are branched and connected to the D terminals of the scan FFs 11, 12, 13, 14, and 15, respectively. The clock signal CLK, the write enable signal WEN, and the chip select signal CEN, input data signal DI, and address signal A are input to scan FFs 11, 12, 13, 14, and 15 via signal lines L1, L2, L3, L4, and L5, respectively.

  Further, scan FFs 11 to 15 are cascade-connected in order between an input of a scan-in signal SCAN IN that is a test signal for a scan path test and an output of a scan-out signal SCAN OUT. Hereinafter, the input side of the scan-in signal SCAN IN is the front stage, and the output side of the scan-out signal SCAN OUT is the rear stage. The scan signal output terminal SO of each scan FF is connected to the scan signal input terminal SI of the next-stage (next one-stage) scan FF. However, the scan signal input terminal SI of the scan FF 11 is connected to the input line of the scan-in signal SCAN IN, and the scan signal output terminal SO of the scan FF 15 is connected to the output line of the scan-out signal SCAN OUT.

The scan clock signals SCAN CLK are input to the scan FFs 11 to 15 through signal lines, respectively.
Each scan FF shifts the signal to the next scan FF in synchronization with the input scan clock signal SCAN CLK, and the scan FF 15 finally outputs a scan-out signal SCAN OUT.
With the scan-out signal SCAN OUT, the values of the scan FFs 11 to 15 are input to a memory macrocell control circuit (not shown) via signal lines. The memory macrocell control circuit performs a scan path test of each signal input to the memory macrocell 20 based on the input values of the scan FFs 11 to 15.

  Further, the scan FF 14 outputs the input data signal DI input to the D terminal from the Q terminal.

The selector 16 receives the output data signal DO of the memory macrocell 20, the output of the scan FF 14 (output data signal from the Q terminal), and the scan operation switching signal SCAN EN via each signal line.
The data output (signal line of the output data signal DO) of the memory macrocell 20 has the same width as the data input (signal line of the input data signal DI).
The selector 16 controls to selectively output the output of the scan FF 14 to which the data input DI is input and the output of the memory macrocell (output data signal DO) in response to the scan operation switching signal SCAN EN input. The selector 16 selects the output of the memory macrocell 20 in the normal state, and selects the output of the scan FF 14 in the scan mode (when the SCAN EN is input). As a result, the input data signal DI can be output to the next-stage scan FF (not shown), for example, without going through the memory macrocell 20 during the scan path test.

  The outputs of the other scan FFs (scan FFs 11 to 13) may not be connected anywhere, and may be connected to other memory macrocells (not shown).

Hereinafter, the case where the circuit inspection apparatus 10 is incorporated in an ASIC (Application Specific Integrated Circuit) will be described.
In this case, an input terminal of the scan-in signal SCAN IN and an output terminal of the scan-out signal SCAN OUT of the circuit inspection device 10 in a scan chain created by cascading flip-flops as in FIG. Connect. That is, the input terminal of the scan-in signal SCAN IN of the circuit inspection apparatus 10 is connected to the scan signal output terminal SO of the flip-flop of the scan chain in the ASIC, and the scan signal input terminal SI of the flip-flop next to that flip-flop. Further, the output terminal of the scan-out signal SCAN OUT of the circuit inspection apparatus 10 is connected.

  The circuit inspection device 10 uses the same scan chain as the interrupted scan chain as the scan clock signal SCAN CLK and the scan operation switching signal SCAN EN. As a result, the circuit inspection apparatus 10 functions as a part of a normal scan chain.

  In the present embodiment, a memory macro cell is taken as an example of an inspection target of the circuit inspection apparatus 10, but it can also be applied to cells such as a CPU and a DSP.

  As described above, according to the present embodiment, each input signal to the memory macro cell 20 is directly taken into the scan FFs 11 to 15, so that it is easy to detect a location where failure is difficult to detect in the scan path test of the memory macro cell control circuit. It is possible to detect.

In addition, according to the present embodiment, the selector 16 switches the output of the scan FF 14 with the output of the memory macro cell 20, so that a scan path test of a circuit (such as a comparator of the memory BIST circuit) that receives the output of the memory macro cell 20 is performed. This makes it possible to easily detect a location where failure is difficult to detect.
As a result, the outflow of defective integrated circuits to the market can be reduced, and the trouble of manually creating test patterns for locations where failure is difficult to detect in a scan path test can be saved. In addition, since it is not necessary to add a manually created pattern for the location, the test cost can be reduced.

  Hereinafter, unless otherwise specified, the configuration and operation of the second embodiment of the present invention are the same as those of the first embodiment.

FIG. 2 is a diagram showing a configuration of a semiconductor integrated circuit according to the second embodiment of the present invention.
As shown in FIG. 2, the semiconductor integrated circuit includes a circuit inspection device 10, a memory macrocell 20, a memory BIST input control circuit 30, a selector 40, and a memory BIST output comparison circuit 50. Is done.

In the semiconductor integrated circuit of FIG. 2, the memory BIST input control circuit 30 and the memory macrocell 20 are connected via a selector 40.
When the BIST enable signal (bist_en) is enabled, the memory BIST input control circuit 30 reads / writes to / from the memory macrocell 20 according to the built-in inspection algorithm in synchronization with the input BIST clock signal (bist_clk). To do.
The selector 40 selects either the clock signal CLK, the write enable signal WEN, the chip select signal CEN, the input data signal DI, and the address signal A from the normal control signal and from the memory BIST input control circuit 30. Thus, the data is output to the memory macro cell 20 via the signal lines L1 to L5, respectively.

  The signal lines L2 to L5 branch to output the write enable signal WEN, the chip select signal CEN, the input data signal DI, and the address signal A to the D terminals of the scan FFs 12 to 15, respectively.

The scan FFs 12 to 15 are cascaded in order between the input of the scan-in signal SCAN IN, which is a test signal for the scan path test, and the output of the scan-out signal SCAN OUT.
The scan clock signals SCAN CLK are input to the scan FFs 13 to 15 through signal lines, respectively.
Since the memory data input (DI) and the data output (DO) generally have the same data width, they are connected to the same scan FF (scan FF 14) as shown in FIG.

The selector 16 receives the output data signal DO of the memory macrocell 20, the output of the scan FF 14 (output data signal from the Q terminal), and the scan operation switching signal SCAN EN via each signal line.
The selector 16 controls to selectively output the output of the scan FF 14 to which the data input DI is input and the output of the memory macrocell (output data signal DO) in response to the scan operation switching signal SCAN EN input.
Normally, the selector 16 selects the output of the memory macrocell 20. At this time, the selector 16 outputs the output data DO from the memory macrocell 20 to the memory BIST output comparison circuit 50.
In the scan mode (SCAN EN input), the selector 16 selects the output of the scan FF 14. Thus, the selector 16 can output the input data signal DI to the next-stage scan FF (not shown), for example, without going through the memory macrocell 20 during the scan path test.

The memory BIST output comparison circuit 50 includes a result comparison unit 51 and a result determination unit 52.
The result comparison unit 51 is connected to the branch of the signal line of the output data signal DO from the selector 16 and the output of the memory BIST input control circuit 30.
The result comparison unit 51 compares the output data DO read from the memory macrocell 20 via the selector 16 with the data output from the memory BIST input control circuit 30 and written in the memory macrocell 20, and determines whether or not they match. Determine.
The determination result output unit 52 outputs the determination result by the result comparison unit 51.

  As described above, according to the present embodiment, since the circuit inspection apparatus 10 is preliminarily incorporated in the semiconductor integrated circuit (memory BIST circuit), there is no need for the user to be aware of the circuit inspection apparatus 10, and the circuit is renewed. It is possible to save the trouble of the user who installs the inspection apparatus.

  Further, according to the present embodiment, since the lines of the data input DI and the data output DO are connected to the same scan FF (scan FF 14), compared to the case where separate scan FFs are connected to DI and DO, The number of scan FFs to be installed can be reduced without degrading the controllability and observability of the scan path test.

  Further, according to the present embodiment, the failure detection rate of the memory BIST input control circuit 30 is improved, and the failure of the memory BIST input control circuit 30 can be easily detected. As a result, the possibility of correctly determining the failure of the memory macro cell 20 is increased, and the outflow of the failed memory macro cell 20 to the market can be reduced.

  Hereinafter, unless otherwise specified, the configuration and operation of the third embodiment of the present invention are the same as those of the first embodiment.

FIG. 3 is a diagram showing the configuration of the memory macrocell 20 according to the third embodiment of the present invention.
As shown in FIG. 3, the memory macrocell 20 includes a circuit inspection device 10, a memory 21 (for example, a RAM), and a signal line that connects each part.
The circuit inspection apparatus 10 includes scan FFs 12 to 15, a selector 16, and signal lines that connect the respective parts.
The scan FFs 12 to 15 are arranged in parallel in the memory 21.

The clock signal CLK, the write enable signal WEN, the chip select signal CEN, the input data signal DI, and the address signal A are input to the memory 21 through signal lines L1, L2, L3, L4, and L5, respectively.
The signal lines L2, L3, L4, and L5 are branched and connected to the D terminals of the scan FFs 12, 13, 14, and 15, respectively, and a write enable signal WEN, a chip select signal CEN, an input data signal DI, and The address signal A is input to the scan FFs 12, 13, 14, and 15 through signal lines L2, L3, L4, and L5, respectively.

  Further, scan FFs 12 to 15 are cascade-connected in order between an input of a scan-in signal SCAN IN which is a test signal for a scan path test and an output of a scan-out signal SCAN OUT.

The scan clock signals SCAN CLK are input to the scan FFs 12 to 15 through signal lines, respectively.
Each scan FF shifts the signal to the next scan FF in synchronization with the input scan clock signal SCAN CLK, and the scan FF 15 finally outputs a scan-out signal SCAN OUT.
With the scan-out signal SCAN OUT, the values of the scan FFs 12 to 15 are input to a memory macrocell control circuit (not shown) via signal lines. The memory macrocell control circuit executes a scan path test of each signal input to the memory 21 based on the input values of the respective scan FFs 12 to 15.

  Further, the scan FF 14 outputs the input data signal DI input to the D terminal from the Q terminal.

The selector 16 receives the output data signal DO of the memory 21, the output of the scan FF 14 (output data signal from the Q terminal), and the scan operation switching signal SCAN EN via each signal line.
The data output of the memory 21 (signal line of the output data signal DO) has the same width as the data input (signal line of the input data signal DI). The selector 16 controls to selectively output the output of the scan FF 14 to which the data input DI is input and the output of the memory macrocell (output data signal DO) in response to the scan operation switching signal SCAN EN input. The selector 16 selects the output of the memory 21 in the normal mode, and selects the output of the scan FF 14 in the scan mode.
The outputs of the other scan FFs (scan FFs 12 and 13) may not be connected anywhere and may be connected to other memory macrocells (not shown).

  As described above, according to the present embodiment, since the circuit inspection apparatus 10 is built in the memory macrocell 20 in advance, even if the memory BIST circuit provided by the EDA vendor does not have a countermeasure for failure detection, the user The circuit inspection device 10 can be incorporated without being conscious on the side, and it is possible to save the trouble of the user who installs the circuit inspection device again.

  The above-described embodiment is an example of a preferred embodiment of the present invention. The embodiment of the present invention is not limited to this embodiment, and various modifications may be made without departing from the scope of the present invention. Is possible.

It is a figure which shows the structure of the semiconductor integrated circuit in Example 1 of this invention. It is a figure which shows the structure of the semiconductor integrated circuit in Example 2 of this invention. It is a figure which shows the structure of the memory macrocell in Example 3 of this invention. It is a figure which shows an example of the test apparatus of the scan path in a prior art. It is a figure which shows the example of the integrated circuit whose failure detection is difficult by a scan path test method. It is a figure which shows the other example of the integrated circuit whose failure detection is difficult by the scan path test method.

Explanation of symbols

10 Circuit inspection equipment 11-15 Scan FF
16, 40 Selector 20 Memory macrocell 21 Memory 30 Memory BIST input control circuit 50 Memory BIST output comparison circuit 51 Result comparison unit 52 Judgment result output unit L1-L5 Signal line

Claims (8)

It has a scan path configured by cascading two or more flip-flops,
Input signals respectively input to the memory via one or more input signal lines are respectively input to the two or more flip-flops via signal lines branched from the input signal lines,
A test pattern signal is input to one of the two or more cascaded flip-flops, the input signal is shifted, and the test pattern signal is output from the other flip-flop. A circuit inspection apparatus. One of the two or more flip-flops is
Of the input signals to the memory, the input data signal written to the memory is connected to a signal line branched from an input signal line, and an input data signal inputted through the branched signal line is output. The circuit inspection apparatus according to claim 1. A selector connected to the output of the data signal from one of the two or more flip-flops and the output of the data signal from the memory;
3. The circuit inspection apparatus according to claim 2, wherein the selector selectively outputs one of a data signal from one of the two or more flip-flops and a data signal from the memory. A memory in which each input signal is input via one or more input signal lines connected thereto, a circuit inspection device for inspecting a failure of a semiconductor integrated circuit, and each input signal to the memory via the input signal line A semiconductor integrated circuit having a memory BIST input control circuit for output and a memory BIST output comparison circuit for inspecting data output from the memory,
The circuit inspection apparatus includes:
It has a scan path configured by cascading two or more flip-flops,
Each of the input signals is input to the two or more flip-flops via a signal line branched from the one or more input signal lines,
A test pattern signal is input to a flip-flop at one end of the two or more cascade-connected flip-flops, and the test pattern signal is output from a flip-flop at the other end. . One of the two or more flip-flops is
Of the input signals to the memory, the input data signal written to the memory is connected to a signal line branched from an input signal line, and an input data signal inputted through the branched signal line is output. The semiconductor integrated circuit according to claim 4. A selector connected to the output of the data signal from one of the two or more flip-flops and the output of the data signal from the memory;
6. The semiconductor integrated circuit according to claim 5, wherein the selector selectively outputs one of a data signal from one of the two or more flip-flops and a data signal from the memory. The selector is
7. The semiconductor integrated circuit according to claim 6, wherein an output of a data signal from the memory is selected as an input and output to the memory BIST output comparison circuit. A memory macrocell having a memory to which each input signal is input via one or more input signal lines connected, and a circuit inspection device for inspecting a failure of the semiconductor integrated circuit,
The circuit inspection apparatus includes:
It has a scan path configured by cascading two or more flip-flops,
Each of the input signals is input to the two or more flip-flops via a signal line branched from the one or more input signal lines,
A memory macrocell, wherein a test pattern signal is input to one flip-flop of two or more cascaded flip-flops, and the test pattern signal is output from the other flip-flop.

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