JP2005051155A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which is capable of reducing a waste of a gap between interposers stacked up in layers so as to improve chip parts in mounting density, and lowering a module composed of the same number of the interposers in mounting height. <P>SOLUTION: The semiconductor integrated circuit device is composed of the interposers 2 (2a to 2e) which are each mounted with semiconductor chips 6a and 6b and/or electronic parts 7 and stacked up in layers through the intermediary of interlayer connection terminals 9 electrically connected to interlayer connection lands 3 formed on the interposers 2. The interposers 2 stacked up in layers are alternately and obliquely stacked up, and a gap between the interposers 2 that confront each other in a vertical direction is set wider at one side than at the other side. The interlayer connection terminals 8a and 8b of different heights are used to make the interposer 2 slant, the low interlayer connection terminal 8b is provided between the interposers 2 at one side, and the high interlayer connection terminal 8a is provided between the interposers 2 at the other side. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit device in which, for example, an interposer on which a semiconductor chip and an electronic component are mounted is stacked in a plurality of stages via interlayer connection terminals. Specifically, the interposer to be stacked is slanted with a separate layer to increase the mounting efficiency of the chip component with respect to the interlayer gap, and a higher-density stacked module is obtained.

  2. Description of the Related Art There is known a semiconductor integrated circuit device in which interposers mounted with bare chips such as semiconductor chips and electronic components are stacked in a plurality of stages via interlayer connection terminals (see, for example, Patent Document 1).

  FIG. 6 shows an example of a semiconductor integrated circuit device in which interposers are stacked in a plurality of stages. This semiconductor integrated circuit device has a structure in which a plurality of interposers 102 are stacked on a substrate 101 at predetermined intervals. The intermediate interposer 102 excluding the lowermost layer and the uppermost layer interposer 102 has a semiconductor chip 103 and / or an electronic component 104 mounted on both front and back surfaces. Moreover, interlayer connection lands 105 are formed on both surfaces except for the interposer 102 laminated on the uppermost layer. Interlayer connection lands 105 are formed in the uppermost interposer 102 only on the surface facing the lower interposer 102.

  In the semiconductor integrated circuit device described above, the interlayer connection land 105 formed in the lowermost interposer 102 and the substrate land 106 formed in the substrate 101 are electrically connected by the external terminal 107 to be formed in each interposer 102. The interlayer connection lands 105 facing each other are conductively connected to each other through the interlayer connection terminals 108, thereby providing a laminated structure in which the interlayer spacing between the interposers 102 is secured by the interlayer connection terminals 108.

  In this semiconductor integrated circuit device, all of the interposers 102 to be stacked are stacked in a horizontal posture, and the semiconductor chip 103 and the electronic component 104 arranged opposite to each other so as not to interfere with each other. A sufficient gap is secured. For example, when a thick semiconductor chip 103 or electronic component 104 is provided on one interposer 102 between the opposing interposers 102, the other interposer 102 facing this has a small thickness. The semiconductor chip 103 or the electronic component 104 is provided.

Japanese Unexamined Patent Publication No. 2000-68443 (page 3, FIG. 2)

  However, even if the semiconductor chip 103 or the electronic component 104 having a partially thin thickness is available, the other semiconductor chip 103 or the electronic component 104 is thick or the electronic component 104 is mixedly mounted. Then, the interlayer gap is governed by the thickness, and it becomes difficult to make the laminated module (semiconductor integrated circuit device) thin.

  Therefore, the present invention has been made in view of such a problem, the loss of the interlayer gap of the laminated interposer is reduced to improve the mounting density of the chip components, and in the case of the same number of interposer layers, An object of the present invention is to provide a semiconductor integrated circuit device capable of reducing the module mounting height.

  In the semiconductor integrated circuit device of the present invention, an interposer on which at least one of a semiconductor chip and an electronic component is mounted is stacked in a plurality of stages via interlayer connection terminals electrically connected to an interlayer connection land formed on the interposer. In the semiconductor integrated circuit device, the interposers stacked in a plurality of stages are stacked obliquely at separate layers, and the gap between the upper and lower interposers facing each other is widened on one side and narrowed on the other.

  In this semiconductor integrated circuit device, the laminated interposers are obliquely laminated with separate layers, and the gap between the upper and lower interposers facing each other is widened on one side and narrowed on the other, so that the wide gap is thick. A thick semiconductor chip or electronic component is mounted, and a thin semiconductor chip or electronic component is mounted in a narrow gap, so that loss of interlayer space is reduced and the mounting height of the module is suppressed.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings.

“First Embodiment”
As shown in FIG. 1, the semiconductor integrated circuit device according to the first embodiment includes a plurality of interposers 2 (2a to 2e) on a substrate 1 such as a mother board, and a desired interlayer gap (interlayer space). Thus, a multi-layered structure is formed.

  The substrate 1 is formed with a plurality of substrate lands 5 that are conductively connected via the external terminals 4 to the interlayer connection lands 3 formed in the lowermost interposer 2a among the interposers 2 stacked in a plurality of stages. ing. On the plurality of substrate lands 5, the interposer 2 stacked in a plurality of stages via the external terminals 4 is mounted.

  The interposer 2 having a laminated structure is arranged in a slanted manner with every other layer (every other layer). Specifically, the lowermost interposer 2a stacked on the substrate 1 is parallel to the substrate 1 and horizontal, and the interposer 2b stacked on the interposer 2b is inclined obliquely to the right and stacked thereon. The interposer 2c is horizontal, and the interposer 2d stacked on the horizontally disposed interposer 2c is also inclined to the right, and the interposer 2e stacked on the top layer is horizontally Has been placed.

  The interposer 2 is formed with interlayer connection lands 3, and semiconductor chips 6 a and 6 b such as LSIs having different thicknesses or electronic components 7 are mounted on one side or both sides. In addition, the interposer 2 has an interlayer connection function as a spacer that holds the interval between the interposers 2 at a predetermined height and a circuit connection function that conductively connects the wiring patterns formed on the interposer 2. A terminal 8 is provided.

  The interlayer connection terminal 8 is made of, for example, solder that melts by reflow, and in order to stack the interposers 2b and 2d obliquely, two types of interlayer connection terminals 8a having a high height and interlayer connection terminals 8b having a low height are used. Has been. The interposers 2b and 2d are arranged obliquely by providing the interlayer connection terminal 8b having a low height between one layer and the interlayer connection terminal 8a having a high height between the other layers. The interlayer connection terminals 8a and 8b are conductively connected by being reflowed on the interlayer connection lands 3 of the interposers 2 that are stacked in the vertical direction, and connect the wiring circuits formed in the interposers 2.

  When the interposers 2b and 2d are inclined and laminated in such a manner, the gap between the opposing upper and lower interposers 2 is wide on one side and narrow on the other. For this reason, between the interposers 2 in which a wide gap is secured, a thick semiconductor chip 6a is mounted on one interposer 2, and the thick interposer 2 facing this has a thick semiconductor chip 6a or an electronic component. 7 can be implemented. Between the interposers 2 having a narrow gap, a thin semiconductor chip 6b is mounted on one interposer 2, and a thin semiconductor chip 6b is mounted on the interposer 2 opposite to the interposer 2 or nothing. Do not implement. That is, a thick semiconductor chip 6 or electronic component 7 is mounted in a large area between layers, and a thin semiconductor chip 6b is mounted in a small area between layers or nothing is mounted.

  According to the semiconductor integrated circuit device configured as described above, the effective efficiency for mounting the chip component with respect to the interlayer gap is improved, and a higher-density laminated module can be obtained. The overall height H2 of the semiconductor integrated circuit device shown in FIG. 1 is the same as the overall height H1 of the conventional semiconductor integrated circuit device in which interposers are stacked in parallel as shown in FIG. When only the interposer is stacked, ΔH (H1−H2) is lowered. Therefore, in the semiconductor integrated circuit device of the first embodiment, the space loss between the interposer layers can be reduced, and the mounting density of the chip components on which the semiconductor chips 6a and 6b and the electronic components 7 are mounted is greatly increased. In addition, the module mounting height can be lowered with the same number of interposer layers.

[Second Embodiment]
As shown in FIG. 2, in the semiconductor integrated circuit device of the second embodiment, the number of interlayer connection terminals 9 is different, and at least one interlayer connection terminal 9 is provided between one layer and two or more interlayer connections. A terminal 9 is provided between the other layers, and the interposers 2b and 2d are inclined.

  In FIG. 2, one interlayer connection terminal 9 having a ball shape is provided on one side of the interlayer connection land 3 of the opposing interposer 2 stacked one above the other, and two other interlayer connection terminals 9 having the same ball shape are provided on the other side. 9 is provided. By making the number of the ball-shaped interlayer connection terminals 9 different on the left and right, the interposer 2 can be inclined with a separation layer as in the semiconductor integrated circuit device of the first embodiment.

  The ball-shaped interlayer connection terminal 9 used here is composed of a high melting point conductive metal 9a that does not melt at the reflow temperature and solder 9b that melts at the reflow temperature, as shown in FIG. 3A, for example. A ball shape (spherical shape formed by covering the outer surface of the metal 9a with solder 9b. The refractory conductive metal 9a serving as a core (core) has a predetermined gap between the interlayer gaps of each interposer 2. In addition, the solder 9b formed on the surface of the refractory conductive metal 9a functions as a circuit connection for conductively connecting the circuits of the interposers 2.

  As the high melting point conductive metal 8a, for example, copper having a melting point of 1083 ° C., high melting point solder, 42 alloy (Fe—Ni alloy), or the like is used. As the solder 8b, for example, a PbSn eutectic system having a melting point of 170 to 190 ° C., a SnAg system solder of 210 to 230 ° C., a SnCu system solder, a SnZn system solder of 190 to 200 ° C., a SnIn system solder of 200 to 220 ° C., etc. Is used.

  Further, as shown in FIG. 2B, the interlayer connection terminal 9 includes a heat-resistant resin 9c, a conductive metal 9d, and solder 9b. The conductive metal 9d is formed on the outer surface of the heat-resistant resin 9c serving as a core. The outer surface of the conductive metal 9d is covered with solder 9b so as to have a spherical shape. As the heat resistant resin 9c, for example, a divinylbenzene crosslinked copolymer having a thermal decomposition temperature of about 450 ° C. is used. As the conductive metal 9d, for example, copper having a melting point of 1083 ° C. or nickel having 1453 ° C. is plated. Instead of the heat-resistant resin 9c, for example, glass having a transition temperature of 500 to 600 ° C., and a high-melting point non-conductive material such as ceramic can be used.

  The interlayer connection terminals 9 are reflowed on the interlayer connection lands 3 of the interposers 2 arranged in a stacked manner in the upper and lower directions and are conductively connected. The two stacked interlayer connection terminals 9 and 9 are joined and electrically connected by melting the solder 9b on the surface by reflow.

[Third Embodiment]
As shown in FIG. 4, the semiconductor integrated circuit device according to the third embodiment uses a columnar interlayer connection terminal 10 instead of a ball shape, and the number of interlayer connection terminals 10 is different. The connection terminals 10 are provided in one layer, two or more interlayer connection terminals 10 are provided in the other layer, and the interposers 2b and 2d are inclined.

  In the semiconductor integrated circuit device of this embodiment, the space loss between the interposer layers can be reduced as in the semiconductor integrated circuit devices of the first and second embodiments, and the semiconductor chips 6a and 6b and the electronic component 7 can be reduced. It is possible to greatly increase the mounting density of chip parts for mounting the chip. Also, this semiconductor integrated circuit device can reduce the module mounting height with the same number of interposer layers.

[Fourth Embodiment]
As shown in FIG. 5, the semiconductor integrated circuit device according to the fourth embodiment has one interlayer connection terminal 9 including a junction portion in which the two interlayer connection terminals 9 having the ball shape shown in FIG. These are covered with the reinforcing resin layer 11.

  When the reinforcing resin layer 11 is subjected to concentrated stress on the joint portion of the interlayer connection terminal 9 due to occurrence of mechanical stress such as thermal stress, drop impact, vibration, etc. in the use environment of the semiconductor integrated circuit device, Functions to counteract stress. Further, since the reinforcing resin layer 11 covers the joint portion of the interlayer connection terminal 9, it also functions to prevent re-oxidation of the joint portion.

  In addition, when the storage condition of the interposer 2 may cause oxidation / bonding deterioration of the interlayer connection terminal 9 during storage (when the wettability is unstable), the reinforcing resin layer 11 has an activation component (antioxidation prevention). (Agent) may be added. Of course, when the wettability of the joint is good (a state in which it is not oxidized or contaminated), the activation action is not particularly necessary. In addition, there is also a method of plasma processing the surfaces of the interlayer connection terminals 9 and the interlayer connection lands 3 as a method for recovering the deterioration of the bondability due to storage.

  The resin of the reinforcing resin layer 11 has a viscosity characteristic that the viscosity decreases, for example, at 80 to 120 ° C., and is softened at a temperature lower than the melting point of the solder portion of the interlayer connection terminal 9. As the resin for forming the reinforcing resin layer 11, for example, trade name T693 / R3901 manufactured by Nagase Chemtech Co., Ltd., trade name CNB837-44 manufactured by Dexter Co., Ltd., or trade name RE9101 manufactured by Kester Co., Ltd. can be used. For example, a resin of T693 / R3901 is a resin containing naphthalenediglycidyl ether as a main agent and tetrahydrophthalic anhydride as a curing agent.

  Since such a resin is used, when the interlayer connection terminal 9 is joined, the reinforcing resin layer 11 softens faster than the interlayer connection terminal 9 and is pushed out from the joining interface, so that the interlayer connection terminal 9 is joined. The portion is covered with the softened reinforcing resin layer 11. By covering the joint portion of the interlayer connection terminal 9 with the reinforcing resin layer 11, the joint portion is blocked from the atmosphere, so that reoxidation of the joint portion is avoided. Further, since the resin is cured after the interposer interlayer bonding, the strength of the bonding portion of the interlayer connection terminal 9 is increased and is reinforced by the reinforcing resin layer 11.

  As described above, in the semiconductor integrated circuit device according to the present embodiment, the reinforcing resin layer 11 is covered so as to cover at least the joint portion of the interlayer connection terminal 9, so that the reinforcing resin layer 11 functions as a reinforcing member. And is not affected by the stress concentrated on the joint. Therefore, according to the semiconductor integrated circuit device of the present embodiment, cracks and breaks do not occur in the joint portion of the interlayer connection terminal 9.

  Further, by adjusting the elastic modulus of the reinforcing resin layer 11 after the bonding and hardening according to the use environment of the semiconductor integrated circuit device, it is possible to flexibly cope with the stress acting on the bonding portion of the interlayer connection terminal 9. It becomes. For example, when placing importance on drop impact resistance, use a highly elastic and hard joint. For reliability in a temperature change environment, the entire interlayer connection system (connection terminal / board, connection terminal / The appropriate elastic modulus is selected in consideration of the stress balance of the IP and the connection terminal / connection terminal, that is, the stress is dispersed.

  Further, in the semiconductor integrated circuit device of the present embodiment, particularly when the interlayer connection terminal 9 having the structure shown in FIG. 3B is used, the stress concentrated on the joint is relieved by the flexibility of the heat-resistant resin 9c serving as the core. Can be made. When the interlayer connection terminal 9 having this structure is used, it is preferable to adjust the elastic modulus of the reinforcing resin layer 11 in consideration of the elastic modulus of the heat-resistant resin 9c. For example, the stress relaxation performance of the heat resistant resin 9c may be killed by covering the connection peripheral portion with a highly elastic reinforcing resin over a wide range. In consideration of the elastic modulus of the heat-resistant resin 9c, it is preferable to adjust the elastic modulus of the reinforcing resin layer 11 after bonding by advancing the resin curing reaction by baking or the like.

  Although specific embodiments to which the present invention is applied have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made.

  In the above-described embodiment, every other interposer is alternately stacked horizontally and diagonally. However, the interposers are stacked evenly on the inclined interposer without arranging the interposer horizontally. May be.

In the present invention, an interposer on which a semiconductor chip or an electronic component is mounted is obliquely stacked with a separation layer depending on the height and number of interlayer connection terminals, and an interlayer space between upper and lower interposers facing each other is effectively used. The present invention can be applied to chip mounting technology that can increase the mounting density of chip components.

It is sectional drawing which shows an example of the semiconductor integrated circuit device of 1st Embodiment. It is sectional drawing which shows an example of the semiconductor integrated circuit device of 2nd Embodiment. It is sectional drawing which shows the interlayer connection terminal used with the semiconductor integrated circuit device of 2nd Embodiment, (a) is the interlayer connection terminal which coat | covered the solder | pewter on the surface of a high melting point conductive metal, (b) is heat-resistant. An interlayer connection terminal in which a conductive metal and solder are coated on the surface of a resin or a high melting point non-conductive metal is shown. It is sectional drawing which shows an example of the semiconductor integrated circuit device of 3rd Embodiment. It is sectional drawing which shows an example of the semiconductor integrated circuit device of 4th Embodiment. It is sectional drawing which shows an example of the conventional semiconductor integrated circuit device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Board | substrate 2, 2a-2e ... Interposer 3 ... Interlayer connection land 6a, 6b ... Semiconductor chip 7 ... Electronic component 8a, 8b, 9, 10 ... Interlayer connection terminal 9a ... High melting-point conductive metal 9b ... Solder 9c ... Heat resistance Resin or high melting point non-conductive substance 9d ... conductive metal 11 ... reinforcing resin layer

Claims (5)

A semiconductor integrated circuit device in which an interposer on which at least one of a semiconductor chip or an electronic component is mounted is stacked in a plurality of stages via interlayer connection terminals electrically connected to an interlayer connection land formed on the interposer,
The semiconductor integrated circuit device according to claim 1, wherein the interposers stacked in a plurality of stages are stacked obliquely at separate layers, and a gap between the opposing upper and lower interposers is widened on one side and narrowed on the other. The semiconductor integrated circuit device according to claim 1,
The interlayer connection terminals have different heights, a low-level interlayer connection terminal is provided in one layer, a high-level interlayer connection terminal is provided in the other layer, and the interposer is inclined. A semiconductor integrated circuit device. The semiconductor integrated circuit device according to claim 1,
The number of the interlayer connection terminals is different, at least one interlayer connection terminal is provided in one layer, two or more interlayer connection terminals are provided in the other layer, and the interposer is inclined. Semiconductor integrated circuit device. The semiconductor integrated circuit device according to claim 3,
A semiconductor integrated circuit device, wherein a reinforcing resin layer is formed so as to cover at least a joint portion of the two or more interlayer connection terminals. The semiconductor integrated circuit device according to claim 4,
A semiconductor integrated circuit device, wherein a softening point of the reinforcing resin layer is lower than a softening point of the interlayer connection terminal.

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