JP2005051146A - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide interposers which are stacked up with a gap that is kept proper and stable between them and to improve interlayer joints in mechanical strength so as to provide a semiconductor integrated circuit device which is improved in production quality and product reliability. <P>SOLUTION: The semiconductor integrated circuit device is composed of interposers 2 which are each mounted with semiconductor chips 6 and electronic parts 7, and stacked up in several layers electrically connecting interlayer connection terminals 8 on interlayer connection lands 3 formed on the interposers 2. The interlayer connection terminal 8 is formed on the interlayer connection land 3 of each of the interposers 2, and a reinforcing resin layer 9 is formed over a joint between the interlayer connection terminals 8 and 8 which are electrically connected together. The joint between the interlayer connection terminals 8 and 8 is improved in mechanical strength and electrical connection reliability by the reinforcing resin layer 9. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit device in which, for example, an interposer on which a semiconductor chip and an electronic component are mounted is stacked in a plurality of stages via interlayer connection terminals, and a manufacturing method thereof. Specifically, the interlayer of each interposer is appropriately secured, and at the same time, the interlayer connection terminal is covered with a reinforcing resin layer to improve the reliability of the semiconductor integrated circuit device.

  2. Description of the Related Art There is known a semiconductor integrated circuit device in which interposers mounted with bare chips such as semiconductor chips and electronic components are stacked in a plurality of stages via interlayer connection terminals (see, for example, Patent Document 1).

  FIG. 13 shows an example of the semiconductor integrated circuit device. This semiconductor integrated circuit device has a structure in which a plurality of interposers 102 are stacked on a substrate 101 at predetermined intervals. The semiconductor chip 103 or the semiconductor chip 103 and the electronic component 104 are mounted on one surface of the interposer 102. Except for the interposer 102 laminated on the uppermost layer, interlayer connection lands 105 are formed on both surfaces thereof. In the uppermost interposer 102, an interlayer connection land 105 is formed only on the surface facing the lower interposer 102.

  In the semiconductor integrated circuit device described above, the interlayer connection land 105 formed in the lowermost interposer 102 and the substrate land 106 formed in the substrate 101 are electrically connected by the external terminal 107 to be formed in each interposer 102. The interlayer connection lands 105 facing each other are conductively connected to each other through the interlayer connection terminals 108, thereby providing a laminated structure in which the interlayer spacing between the interposers 102 is secured by the interlayer connection terminals 108.

  FIG. 14 shows an example of a semiconductor integrated circuit device in which the semiconductor chip 103 and the electronic component 104 are mounted on both surfaces of each interposer 102 except the lowermost interposer 102. In this semiconductor integrated circuit device, since the semiconductor chip 103 and the electronic component 104 are mounted on both surfaces of the interposer 102, it is necessary to widen the interlayer spacing of each interposer 102, so that the interlayer connection terminal 108 of FIG. A tall interlayer connection terminal 109 is used.

  FIG. 15 shows an example of a semiconductor integrated circuit device using an interlayer connection terminal 110 having a large volume instead of the tall interlayer connection terminal 109 in the semiconductor integrated circuit device of FIG. In this semiconductor integrated circuit device, by using the interlayer connection terminal 110 having a large volume, a stable interlayer connection can be obtained at the same time as ensuring the interlayer spacing.

Japanese Unexamined Patent Publication No. 2000-68443 (page 3, FIG. 2)

  However, in the semiconductor integrated circuit device using the tall interlayer connection terminal 109 in FIG. 14, since the posture of the interlayer connection terminal 109 is unstable, mounting and bonding to the interlayer connection terminal 109 and further stacking of the interposer 102 are performed. Since the interlayer connection terminal 109 is inclined and easily joined in the process, the manufacturing quality is deteriorated.

  In the semiconductor integrated circuit device using the interlayer connection terminal 110 having a large volume as shown in FIG. 15, the space occupied by the interlayer connection terminal 110 becomes large, and it is difficult to arrange the connection terminals with a fine pitch and increase the number of pins.

  Therefore, the present invention has been made in view of such problems, and makes the inter-layer gap between the laminated interposers appropriate and stable, increasing the mechanical strength of the inter-layer connection portion, and manufacturing quality and products. It is an object of the present invention to provide a semiconductor integrated circuit device capable of improving reliability and a manufacturing method thereof.

  The semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit device in which an interposer on which a semiconductor chip is mounted is laminated in a plurality of stages by electrically connecting interlayer connection terminals on an interlayer connection land formed on the interposer, An interlayer connection terminal is provided on an interlayer connection land of each interposer, and a reinforcing resin layer is formed so as to cover at least a joint portion of the interlayer connection terminals that are conductively connected to each other.

  In this semiconductor integrated circuit device, since the reinforcing resin layer is formed so as to cover at least the joint portion of the interlayer connection terminal, the reinforcing resin layer serves as a reinforcing member to enhance the mechanical strength of the interlayer connection of the interposer, Stabilize the electrical connection between the interposer layers.

  In the method for manufacturing a semiconductor integrated circuit device of the present invention, a reinforcing resin sheet having a softening point lower than the softening point of the interlayer connection terminal is disposed on the interlayer connection terminal in which the interposers are stacked in a plurality of stages. After the interposer is laminated with the reinforcing resin sheet sandwiched, reflow is performed. And by the reflow, the reinforcing resin sheet is softened and at least the joint portion of the interlayer connection terminal is covered with the reinforcing resin layer.

  In this manufacturing method, a reinforcing resin sheet having a softening point lower than the softening point of the interlayer connection terminal is used, and the reinforcing resin sheet is sandwiched between the interlayer connection terminals. First, the reinforcing resin sheet is softened, and the joint portion of the interlayer connection terminal is covered with the softened resin. Thereby, the joining of the interlayer connection terminals can be conducted without being contaminated by the atmosphere.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings.

"Configuration of semiconductor integrated circuit device"
As shown in FIG. 1, the semiconductor integrated circuit device according to the present embodiment has a laminated structure in which a plurality of interposers 2 are laminated in a plurality of stages at a desired interlayer spacing on a substrate 1 such as a mother board. .

  A plurality of substrate lands 5 that are conductively connected via external terminals 4 to the interlayer connection lands 3 formed in the lowermost interposer 2 of the interposers 2 stacked in a plurality of stages are formed on the substrate 1. ing. On the plurality of substrate lands 5, the interposer 2 stacked in a plurality of stages via the external terminals 4 is mounted.

  On the interposer 2, the semiconductor chip 6 or the electronic component 7, or the semiconductor chip 6 and the electronic component 7 are mounted on both the front and back surfaces. In addition, the interposer 2 has an interlayer connection function as a spacer that holds the interval between the interposers 2 at a predetermined height and a circuit connection function that conductively connects the wiring patterns formed on the interposer 2. A terminal 8 is provided.

  For example, as shown in FIG. 2A, the interlayer connection terminal 8 includes a high melting point conductive metal 8a that does not melt at the reflow temperature and solder 8b that melts at the reflow temperature, and solder is formed on the outer surface of the high melting point conductive metal 8a. It is a so-called spherical shape (ball shape) formed by covering 8b. The high melting point conductive metal 8a serving as a core functions as a spacer having a predetermined gap between the interlayer gaps of each interposer 2. Further, the solder 8b formed on the surface of the refractory conductive metal 8a functions as a circuit connection for conductively connecting the circuits of the respective interposers 2.

As the high melting point conductive metal 8a, for example, copper having a melting point of 1083 ° C., high melting point solder, 42 alloy (Fe—Ni alloy), or the like is used. As the solder 8b, for example, a PbSn eutectic system having a melting point of 170 to 190 ° C., a SnAg system solder of 210 to 230 ° C., a SnCu system solder, a SnZn system solder of 190 to 200 ° C., a SnIn system solder of 200 to 220 ° C., etc. Is used.

  Further, as shown in FIG. 2B, the interlayer connection terminal 8 includes a heat-resistant resin 8c, a conductive metal 8d, and solder 8b. The conductive metal 8d is formed on the outer surface of the heat-resistant resin 8c serving as a core. The outer surface of the conductive metal 8d is coated and solder 8b is formed into a spherical shape. As the heat-resistant resin 8c, for example, a divinylbenzene crosslinked copolymer having a thermal decomposition temperature of about 450 ° C. is used. As the conductive metal 8d, for example, copper having a melting point of 1083 ° C. or nickel having 1453 ° C. is plated. Instead of the heat-resistant resin 8c, for example, glass having a transition temperature of 500 to 600 ° C., and a high melting point non-conductive material such as ceramic can be used.

  The interlayer connection terminals 8 are electrically connected to the interlayer connection lands 3 of the interposers 2 that are stacked in the vertical direction. Between the layers of the interposer 2 that are stacked one above the other, the interlayer connection terminals 8 that are conductively connected on the interlayer connection land 3 of each interposer 2 are melt-bonded. Due to the joining of these two interlayer connection terminals 8, the interlayer distance H of the interposer 2 facing each other is a sufficient distance that the semiconductor chip 6 and the electronic component 7 are not in contact with each other, and the product height is suppressed. Yes. Further, the wiring circuit formed in the interposer 2 is conductively connected by joining these two interlayer connection terminals 8.

  A reinforcing resin layer 9 is formed so as to cover at least the joint portion of the interlayer connection terminals 8 that are conductively joined to each other and cover one of the interlayer connection terminals 8. The reinforcing resin layer 9 is subjected to stress when concentrated stress is applied to the joint portion of the interlayer connection terminal 8 due to occurrence of mechanical stress such as thermal stress, drop impact, and vibration in the usage environment of the semiconductor integrated circuit device. Functions to counteract Further, since the reinforcing resin layer 9 covers the joint portion of the interlayer connection terminal 8, it also serves to prevent re-oxidation of the joint portion.

  If the storage conditions of the interposer 2 cause the oxidation / bonding deterioration of the interlayer connection terminals 8 during storage (when the wettability is unstable), the reinforcing resin layer 9 has an activation component (antioxidation prevention). (Agent) may be added. Of course, when the wettability of the joint is good (a state in which it is not oxidized or contaminated), the activation action is not particularly necessary. In addition, there is a method of plasma processing the surfaces of the interlayer connection terminals 8 and the interlayer connection lands 3 as a method for recovering the deterioration of the bondability due to storage.

  The resin of the reinforcing resin layer 9 has a viscosity characteristic that the viscosity decreases at, for example, 80 to 120 ° C., and is softened at a temperature lower than the melting point of the interlayer connection terminal 8 solder portion. As the resin for forming the reinforcing resin layer 9, for example, trade name T693 / R3901 manufactured by Nagase Chemtech Co., Ltd., trade name CNB837-44 manufactured by Dexter Co., Ltd., or trade name RE9101 manufactured by Kester Co., Ltd. can be used. For example, a resin of T693 / R3901 is a resin containing naphthalenediglycidyl ether as a main agent and tetrahydrophthalic anhydride as a curing agent.

  Since such a resin is used, the reinforcing resin layer 9 is softened earlier than the interlayer connection terminal 8 when the interlayer connection terminal 8 is joined, and the joint portion of the interlayer connection terminal 8 is melted. Covered with a reinforcing resin. By covering the joint portion of the interlayer connection terminal 8 with the reinforcing resin layer 9, the joint portion is shielded from the atmosphere, so that reoxidation of the joint portion is avoided. The curing resin has a curing start temperature of about (120 to 200) ° C., and the curing reaction proceeds by baking after the bonding.

  FIG. 3 is an enlarged cross-sectional view of the main part of the semiconductor integrated circuit device showing an example in which the reinforcing resin layer 9 is not formed. In FIG. 3, when mechanical stress such as thermal stress, drop impact, or vibration occurs in the environment where the semiconductor integrated circuit device is used, stress is generated in each interposer 2 in the left-right direction indicated by the arrows in the figure. The stress concentrates on the joint portion of the interlayer connection terminal 8. Due to this stress, a crack may occur in the joint portion of the interlayer connection terminal 8 and break.

  However, in the semiconductor integrated circuit device of the present embodiment, since the reinforcing resin layer 9 is covered so as to cover at least the joint portion of the interlayer connection terminal 8, the reinforcing resin layer 9 functions as a reinforcing member. Unaffected by stress concentrated at the joint. Therefore, according to the semiconductor integrated circuit device of the present embodiment, no cracks or breaks occur in the joint portion of the interlayer connection terminal 8.

  Further, by adjusting the elastic modulus of the reinforcing resin layer 9 after the bonding and hardening according to the use environment of the semiconductor integrated circuit device, it is possible to flexibly cope with the stress acting on the bonding portion of the interlayer connection terminal 8. It becomes. For example, when placing importance on drop impact resistance, use a highly elastic and hard joint. For reliability in a temperature change environment, the entire interlayer connection system (connection terminal / board, connection terminal / The appropriate elastic modulus is selected in consideration of the stress balance of the IP and the connection terminal / connection terminal, that is, the stress is dispersed.

  Further, in the semiconductor integrated circuit device of the present embodiment, particularly when the interlayer connection terminal 8 having the structure shown in FIG. 2B is used, the stress concentrated on the joint is relieved by the flexibility of the heat-resistant resin 8c as the core. Can be made. When the interlayer connection terminal 8 having this structure is used, it is preferable to adjust the elastic modulus of the reinforcing resin layer 9 in consideration of the elastic modulus of the heat-resistant resin 8c. For example, the stress relaxation performance of the heat-resistant resin 8c may be killed by covering the connection peripheral portion with a highly elastic reinforcing resin over a wide range.

[Method for Manufacturing Semiconductor Integrated Circuit Device]
Next, a method for manufacturing the semiconductor integrated circuit device described above will be described in detail with reference to the following process drawings. First, as shown in FIG. 4A, the semiconductor chip 6 is mounted on the lowermost interposer 2. The semiconductor chip 6 is mounted at a substantially central position of the interposer 2. Next, as shown in FIG. 4B, the external terminals 4 are mounted on the interlayer connection lands 3 formed in the interposer 2 and heat bonded. The external terminal 4 is formed on the interlayer connection land 3 on the back surface facing the substrate 1.

  Next, as shown in FIG. 5, interlayer connection terminals 8 are mounted on the interlayer connection lands 3 formed on the surface of the substrate 1 and reflowed. Then, the interlayer connection terminal 8 is composed of the high melting point conductive metal 8a whose core portion does not melt at the reflow temperature and the surface thereof is composed of the solder 8b that melts at the reflow temperature. Therefore, only the surface solder 8b melts, The connection terminal 8 is electrically connected to the interlayer connection land 3.

  Next, the interlayer connection terminals 8 are similarly mounted on the interlayer connection lands 3 of the interposer 2 stacked on the lowermost interposer 2 and reflowed. Interlayer connection terminals 8 are mounted on and bonded to the interlayer connection lands 3 on both surfaces of the interposer 2 disposed in the intermediate layer excluding the uppermost layer interposer 2.

  Next, as shown in FIG. 6, the reinforcing resin sheet 10 is disposed on the interlayer connection terminal 8. In the present embodiment, a rectangular reinforcing resin sheet 10 having an opening at the center according to the arrangement shape of the interlayer connection terminals 8 is arranged so as to cover the interlayer connection terminals 8. In addition, as shown in FIG. 7, the reinforcing resin paste 11 may be supplied so as to cover the interlayer connection terminals 8 instead of the reinforcing resin sheet 10. The reinforcing resin paste 11 is supplied by printing, dispensing, or transferring a paste-like resin on the interlayer connection terminal 8, for example.

  Next, as shown in FIG. 8, the interposer 2 to be stacked on the interposer 2 is disposed on the lowermost interposer 2. When laminating these interposers 2 and 2, the positions of the interlayer connection terminals 8 and 8 formed in the interposers 2 and 2 are laminated together. Then, after the interposers 2 and 2 are stacked, the interposers 2 and 2 are temporarily held so that their relative positions do not shift until the next bonding step.

  For temporary holding, the reinforcing resin sheet 10 is made sticky, and the interposers 2 and 2 are temporarily held by the adhesive force. Alternatively, the interposers 2 and 2 may be temporarily held by a dedicated jig without giving the reinforcing resin sheet 10 adhesive force. And the interposer 2 is laminated | stacked so that an above-described lamination process may be repeated sequentially and it may become a predetermined number of steps.

  Next, as shown in FIG. 9, the laminated interposer 2 is reflowed. Then, since the softening point of the reinforcing resin sheet 10 is lower than the softening point of the interlayer connection terminal 8, the reinforcing resin sheet 10 is softened (low viscosity) before the interlayer connection terminal 8 melts. The reinforcing resin sheet 10 softens and covers the entire interlayer connection terminal 8 formed in the lower layer interposer 2 and covers the joint. At the joint, the resin is extruded to the outer periphery without hindering the joint state, covers the periphery of the joint, and shields the joint from the atmosphere (oxygen) to avoid reoxidation during solder joining.

  And if the junction part of the said interlayer connection terminals 8 and 8 is covered with the softening resin sheet 10 which softened, each interlayer connection terminal 8 and 8 will fuse | melt and will be conduct-connected. Here, the high melting point conductive metal 8a does not melt, and only the solder 8b melts. For this reason, the interlayer gap of each interposer 2 is made an appropriate gap by the high melting point conductive metal 8a. When the interlayer connection terminal 8 shown in FIG. 2B is used, only the solder 8b is melted, and the conductive metal 8d and the central high melting point non-conductive metal 8c are not melted, but the conductive metal 8d. And the interlayer connection land 3 are conductively connected.

  Thus, since the junction part of the interlayer connection terminals 8 and 8 is interrupted | blocked with air | atmosphere, metal oxidation under joining high temperature can be suppressed from joining metal melting | fusing, and favorable joining quality can be obtained. Although there is a method of avoiding metal oxidation during bonding by using nitrogen instead of air as the heating atmosphere, if the resin covers the joint and an oxygen-free state is secured, it is possible to dare to use a nitrogen infrastructure (expensive equipment) or nitrogen There is no need to spend money. Further, when an activating component (antioxidant) is contained in the reinforcing resin sheet 10 described above, it is possible to remove the oxide by this activating function and restore good bondability.

  Finally, the laminated interposer 2 is put in an oven or the like, and the reinforcing resin sheet 10 softened in an atmosphere of, for example, 120 ° C. to 200 ° C. is cured. Then, as shown in FIG. 10, a reinforcing resin layer 9 is formed so as to cover one interlayer connection terminal 8 including the joint portion of the interlayer connection terminals 8, 8. By providing the reinforcing resin layer 9 so as to cover the joint portion, the interlayer connection of the interposer 2 is mechanically enhanced and the electrical connection is stably ensured. Further, the interlayer gap between the interposers 2 becomes appropriate and stable.

  Manufactured through the above processes improves the manufacturing quality of the semiconductor integrated circuit device made into a laminated module, and also under the market environment (temperature environment, drop impact, vibration, etc.) of the product equipped with this semiconductor integrated circuit device. ) Can improve the reliability of products against stress.

"Other embodiments"
In the embodiment described above, the reinforcing resin layer 9 is formed so as to cover the joint portion of the interlayer connection terminal 8 and one of the interlayer connection terminals 8. However, as shown in FIG. The reinforcing resin layer 9 may be formed so as to cover it.

  In addition, in the semiconductor integrated circuit device of FIG. 1, the interlayer connection terminals 8 formed in each interposer 2 have a spherical shape, but the interlayer connection terminals 8 may have a cylindrical shape as shown in FIG. For example, copper or 42 alloy can be used as the columnar interlayer connection terminal 8.

  Although specific embodiments to which the present invention is applied have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made.

  INDUSTRIAL APPLICABILITY The present invention can be applied to a semiconductor integrated circuit device stacking technique in which interposers on which semiconductor chips and electronic components are mounted are stacked in a plurality of stages with a predetermined gap.

It is sectional drawing which shows an example of the semiconductor integrated circuit device of this Embodiment. It is sectional drawing which shows the interlayer connection terminal used with the semiconductor integrated circuit device of this Embodiment, (a) is the interlayer connection terminal which coat | covered the solder | pewter on the surface of a refractory conductive metal, (b) is heat resistant resin or An interlayer connection terminal in which a conductive metal and solder are coated on the surface of a high melting point non-conductive metal is shown. This is an enlarged cross-sectional view of the main part showing how thermal stress and mechanical stress are generated when the interlayer connection terminals are connected to each other without forming a reinforcing resin layer, and concentrated stress is applied to the junction of the interlayer connection terminals. is there. It is process drawing which shows the manufacturing method of the semiconductor integrated circuit device of this Embodiment, and shows the process of forming an interlayer connection land and an external terminal in an interposer. It is process drawing which shows the manufacturing method of the semiconductor integrated circuit device of this Embodiment, and shows the process of mounting and joining an interlayer connection terminal on an interlayer connection land. It is process drawing which shows the manufacturing method of the semiconductor integrated circuit device of this Embodiment, and shows the process of mounting the resin sheet for reinforcement on an interlayer connection terminal. It is process drawing which shows the manufacturing method of the semiconductor integrated circuit device of this Embodiment, and shows the process of supplying the resin paste for reinforcement on an interlayer connection terminal. It is process drawing which shows the manufacturing method of the semiconductor integrated circuit device of this Embodiment, and shows the process of laminating | stacking an interposer. It is process drawing which shows the manufacturing method of the semiconductor integrated circuit device of this Embodiment, and shows the process of softening a reinforcement resin sheet and coat | covering the junction part of an interlayer connection terminal, and one interlayer connection terminal with reinforcement resin. It is process drawing which shows the manufacturing method of the semiconductor integrated circuit device of this Embodiment, and shows the process of hardening a reinforcing resin and forming a reinforcing resin layer. It is sectional drawing which shows the other example of the semiconductor integrated circuit device of this Embodiment, and shows an example which coat | covered the whole interlayer connection terminal with the resin layer for reinforcement. It is sectional drawing which shows the other example of the semiconductor integrated circuit device of this Embodiment, and shows an example using a column-shaped interlayer connection terminal. It is sectional drawing which shows an example of the conventional semiconductor integrated circuit device. It is sectional drawing which shows the other example of the conventional semiconductor integrated circuit device. It is sectional drawing which shows the other example of the conventional semiconductor integrated circuit device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Board | substrate 2 ... Interposer 3 ... Interlayer connection land 6 ... Semiconductor chip 7 ... Electronic component 8 ... Interlayer connection terminal 8a ... High melting point conductive metal 8b ... Solder 8c ... Heat-resistant resin or high melting point non-conductive metal 8d ... Conductivity Metal 9 ... Reinforcing resin layer 10 ... Reinforcing resin sheet

Claims (7)

An interposer having at least a semiconductor chip mounted thereon is a semiconductor integrated circuit device in which interlayer connection terminals on an interlayer connection land formed on the interposer are conductively connected to each other and stacked in a plurality of stages.
A semiconductor integrated circuit device, wherein the interlayer connection terminal is provided on an interlayer connection land of each interposer, and a reinforcing resin layer is formed covering at least a joint portion of the interlayer connection terminals that are conductively connected to each other. The semiconductor integrated circuit device according to claim 1,
The semiconductor integrated circuit device, wherein the reinforcing resin layer is provided so as to cover the interlayer connection terminal. The semiconductor integrated circuit device according to claim 1,
A semiconductor integrated circuit device, wherein a softening point of the reinforcing resin layer is lower than a softening point of the interlayer connection terminal. The semiconductor integrated circuit device according to claim 1,
The interlayer connection terminal is composed of a high melting point conductive metal that does not melt at the reflow temperature and solder that melts at the reflow temperature, and is formed by covering the outer surface of the high melting point conductive metal with solder. Semiconductor integrated circuit device. The semiconductor integrated circuit device according to claim 1,
The interlayer connection terminal is made of a heat-resistant resin, a conductive metal, and solder, and is formed by coating the outer surface of the heat-resistant resin with a conductive metal and coating the outer surface of the conductive metal with solder. A semiconductor integrated circuit device. The semiconductor integrated circuit device according to claim 1,
The interlayer connection terminal is made of a high melting point non-conductive metal, a conductive metal and solder that does not melt at the reflow temperature, and the outer surface of the high melting point non-conductive metal is coated with the conductive metal and the outer surface of the conductive metal. A semiconductor integrated circuit device characterized in that it is formed by covering with solder. Bonding a spacer for laminating the interposer in a plurality of stages and an interlayer connection terminal for circuit conduction connection on at least the interlayer connection land of the interposer on which the semiconductor chip is mounted;
On the interlayer connection terminal, a step of disposing a reinforcing resin sheet having a softening point lower than the softening point of the interlayer connection terminal;
Positioning the interlayer connection terminals formed on each interposer, and laminating the interposer with the reinforcing resin sheet sandwiched therebetween,
A method of manufacturing a semiconductor integrated circuit device comprising: reflowing the laminated interposer, softening the reinforcing resin sheet, and covering at least the joint portion of the interlayer connection terminal with the reinforcing resin layer.

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