JP2005047228A - Constant voltage source, recording head, and recording device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a constant voltage source which is compact and high pressure-resistant, and small in process variations and temperature-dependent variations. <P>SOLUTION: According to the circuit configuration of the constant voltage source, when a current is not supplied from an output terminal VHTM to a load, a current from a current source 101 flows to a PMOS 103 and a sufficiently large current does not flow in a current-voltage converting circuit 105. Therefore the current-voltage converting circuit 105 does not generate a voltage sufficient for turning on a PMOS 104. Thus a sum of a gate voltage of the PMOS 103 and a gate-source voltage is output to the VHTM, and when a current is supplied from the output terminal to the load, an output voltage is decreased to turn off the PMOS 103. Therefore a current flowing through the current-voltage converting circuit 105 is increased, which enables the current-voltage converting circuit 105 to supply a gate voltage sufficient for turning on the PMOS 104. As a result, the PMOS 104 supplies a current to the VHTM and increase the output voltage, which result in that the output voltage is maintained in an almost constant value. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a constant voltage source for a drive circuit that drives an inkjet recording head.

  In addition to the fact that noise generation during printing is negligibly small, a printer using an ink jet recording method (liquid jet recording) can perform high-speed recording and can print on plain paper. Has recently attracted interest. The electrothermal conversion element (heater) of this type of recording head and its drive circuit can be formed on the same substrate using semiconductor process technology (see, for example, Patent Document 1). FIG. 3 is a diagram showing a drive circuit configuration of a recording head mounted on a conventional inkjet recording apparatus.

  As shown in FIG. 3, 601 is an electrothermal conversion element (heater) that generates heat for ejecting ink, 602 is a power transistor for supplying a desired current to the heater 601, and 606 is a current for each heater 601. The shift register 606 temporarily stores image data for determining whether or not to eject ink from the nozzles of the recording head. The shift register 606 includes a transfer clock signal input terminal (CLK) and a heater 601. Is provided with an image data input terminal (DATA) for serially inputting image data for turning ON / OFF. Reference numeral 605 denotes a latch circuit for recording and holding image data for each heater 601 for each heater. A latch signal input terminal (LT) for inputting a latch signal for controlling latch timing with an output of the shift register 606 as an input. Is provided. Reference numeral 604 denotes an AND circuit that receives an output of the latch circuit 605 and a heat signal (HE) that determines the timing of current flow through the heater 601. The output of the AND circuit 604 is input to the gate of the power transistor 602 via the voltage conversion circuit 603.

  The circuit configuration of the voltage conversion circuit 603 will be described. 708 is a first inverter circuit that inverts image data from the AND circuit 604, and 707 is a second inverter that further inverts a signal output from the first inverter circuit 708. Circuit. Reference numerals 702 and 703 respectively comprise PMOS and NMOS transistors to form a first CMOS inverter circuit. Reference numeral 701 denotes an internal power supply line output from the voltage generation circuit 607 so that the first CMOS inverter circuit can be driven at 5 V or less which is the output voltage of the AND circuit (the power supply voltage of the logic section is generally 5 V or less). This is a first buffer PMOS for dividing the voltage supplied from VHTM. Reference numerals 705, 706, and 704 denote PMOS and NMOS transistors, respectively, a second CMOS inverter circuit and a second buffer PMOS. Here, the gate of the first buffer PMOS 701 is connected to a connection portion of 702 and 703 which are the output portions of the paired second CMOS inverter circuit. Further, the gate of the second buffer PMOS 704 is also connected to a connection portion of 705 and 706 which is an output portion of the first CMOS inverter circuit which makes a pair, and also serves as an output of the voltage conversion circuit.

  The output voltage VHTM of the voltage generation circuit 607 is preferably set as high as possible without exceeding the breakdown voltage of the CMOS inverter and the gate breakdown voltage of the MOS (however, from the viewpoint of protection of the voltage conversion circuit 603, it is unnecessarily high). If possible, it may be shared with the heater power line VH. This is to reduce the resistance of the power transistor 602 as much as possible when the power transistor 602 is turned on. However, the drive voltage to the normal heater is often set to a high value of 20V or more, and the breakdown voltage of the CMOS inverter is often made by a process up to about 15V. Also, since the gate breakdown voltage of the MOS depends on the gate oxide film, it is necessary to make the voltage sufficiently lower than the dielectric breakdown voltage of the gate oxide film, and it is difficult for the optimum voltage of the voltage conversion circuit and the driving voltage of the heater to match, Providing a separate power supply line for the voltage conversion circuit leads to an increase in the cost of the entire system.

  Therefore, in the conventional technique, the voltage generation circuit 607 generates the constant voltage VHTM with a circuit configuration as shown in FIGS. The example shown in FIG. 4 is an example constituted by a source follower circuit. An arbitrary voltage is generated from the heater power supply line VH by the voltage dividing ratio of the resistors R0 and R1, and an NMOS transistor T1 as a buffer and a resistor R2 A source follower circuit composed of the above is connected, and the source of the NMOS transistor T1 is configured as the output terminal of the voltage generation circuit 607.

The example shown in FIG. 5 is an example in which PMOS transistors are diode-connected in multiple stages, and is obtained by constant voltage VHTM = heater power supply voltage VH− (PMOS VGS voltage) × (PMOS number). However, the PMOS VGS voltage is a voltage generated between the gate and the source, and is obtained by the following equation.
VGS = Vth + (2 × I5 / (μ _n × C _ox × W / L)) ^1/2
Here, I5 is the current value set by I5 = (constant voltage VHTM / resistor R5), μ _n is the mobility, C _ox is the oxide film capacitance per unit area, W is the gate width, and L is the gate length. is there.
JP-A-5-185594

  However, each circuit for obtaining the constant voltage VHTM has the following problems.

  When the difference between the constant voltage VHTM and the heater power supply voltage VH is large, a configuration in which the PMOS as shown in FIG. 5 is diode-connected in multiple stages can reduce the output impedance by reducing the gate width W with current driving capability. It is necessary to provide large PMOSs in multiple stages, and there is a problem that the chip area for realizing this circuit increases.

  Further, when the circuit is manufactured by a semiconductor process, the VGS voltage characteristics of the PMOS with respect to the current value vary, and therefore the generated VGS voltage value varies even with the same current value. At this time, since the constant voltage VHTM = heater power supply voltage VH− (PMOS VGS voltage) × (PMOS number), the fluctuation value obtained by multiplying the variation of the PMOS VGS voltage value by the number of PMOS is the VHTM voltage value. The fluctuation value is greatly affected by the PMOS VGS voltage characteristics.

  Similarly, the fluctuation value obtained by multiplying the number of PMOSs also becomes a fluctuation value of the VHTM voltage value with respect to the fluctuation value of the VGS voltage due to a temperature change or the like, and thus is greatly affected by the fluctuation of the VGS voltage of the PMOS.

  In the case of an NMOS source follower circuit as shown in FIG. 4, when a semiconductor circuit using a P-type substrate, for example, a source follower circuit is formed by a general 5V CMOS process, the output voltage is 5 V or more. When the voltage is to be output, the voltage between the substrate and the source of the NMOS becomes 5 V or more, which causes a problem with the withstand voltage. Furthermore, when the circuit as shown in FIG. 4 is configured by a PMOS source follower circuit, it can be driven efficiently in the direction of drawing current into the circuit, but cannot be driven efficiently in the direction of outputting current. It cannot be used as a voltage source.

  An object of the present invention is to provide a constant voltage source that is small in size and has a high withstand voltage, has a process variation, and has a small fluctuation amount with respect to temperature.

  To achieve the above object, the constant voltage source according to the present invention includes a first PMOS transistor for determining an output voltage, a second PMOS transistor for supplying an output current, and an output current not being supplied. A first means for applying a voltage not exceeding the threshold voltage between the gate and source of the second PMOS transistor and supplying a voltage exceeding the threshold voltage when supplying an output current is provided.

  Specifically, the first means includes a first current source connected to the source side of the first PMOS transistor whose source is connected to the output terminal, and a drain side of the first PMOS transistor. And a current-voltage conversion circuit and a voltage determination circuit connected in parallel with the first current source and the first PMOS transistor between the second current source and the supply voltage and the second current source. Here, the current-voltage conversion circuit is connected to the gate of the second PMOS transistor whose drain is connected to the output terminal and whose source is connected to the supply voltage. Further, the current value of the second current source is larger than the current value of the first current source.

  The first PMOS transistor preferably constitutes a PMOS source follower circuit. Further, it is desirable that the second PMOS transistor is grounded.

  With the circuit configuration as described above, when no current is supplied from the output terminal of the constant voltage source to the load, the current of the first current source flows through the first PMOS transistor, which is sufficient for the current-voltage conversion circuit. Current does not flow. Therefore, the current-voltage conversion circuit does not give a gate voltage sufficient to turn on the second PMOS transistor. As a result, the sum of the first PMOS gate voltage and the gate-source voltage is output to the output terminal. On the other hand, when a current is supplied from the output terminal to the load, the output voltage decreases and the first PMOS transistor is turned off, so that the current flowing through the current-voltage conversion circuit increases. Therefore, the current-voltage conversion circuit provides a gate voltage sufficient to turn on the second PMOS transistor. As a result, the second PMOS transistor supplies current to the output terminal and raises the output voltage, and as a result, keeps the output voltage substantially constant.

  As described above, according to the present invention, since a PMOS is used, there are few problems with withstand voltage. In addition, the number of PMOS having a large current driving capability is as small as one, a circuit can be configured with a smaller chip area than a conventional constant voltage source, and the variation in and fluctuation of the VGS voltage characteristics of the PMOS is extremely small. strong.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram schematically showing a configuration of a constant voltage source according to an embodiment of the present invention. FIG. 2 is a diagram showing an example of the specific circuit configuration.

  In the present embodiment, as shown in FIG. 1, a reference follower circuit using a PMOS 103 that outputs a reference voltage VREF, an output voltage VHTM, current sources 101 and 102, and a PMOS 104 for supplying a load current that flows from the output voltage VHTM. The circuit is composed of a PMOS source ground circuit, a current-voltage conversion circuit 105 that sets the VGS voltage of the PMOS 104, and a voltage determination circuit 106, which are formed on a P-type substrate. Here, the PMOS VGS voltage is a voltage generated between the gate and the source. The current-voltage conversion circuit 105 and the voltage determination circuit 106 are each configured by a resistor, and the drain voltage of the PMOS source follower circuit is set by the voltage determination circuit.

  In the example shown in FIG. 2, the current source 102 in FIG. 1 is configured with NMOSs 110 and 111, the current source 101 is configured with PMOSs 115 and 116, the current-voltage conversion circuit is configured with a resistor 109, and the voltage determination circuit is configured with an NMOS transistor 112. Yes.

  The operation of this embodiment will be described for the circuit shown in FIG.

  The output voltage VHTM is set by a PMOS source follower circuit composed of a PMOS 103 whose gate is connected to a VREF terminal set as a reference voltage, and the output voltage VHTM = (VREF voltage + VGS voltage of the PMOS 103). Further, assuming that the current source 101 has a current value I1 and the current source 102 has a current value I2, this current value is set to satisfy I1 <I2, and the current-voltage conversion circuit 105 has (I2-I1) Current value will flow. At this time, the VGS voltage of the PMOS 104 becomes a voltage determined by the current value of (I2-I1) and the current-voltage conversion circuit 105, and is set so that this voltage value <Vth. Here, Vth is a threshold voltage necessary for turning on the PMOS transistor. Therefore, the PMOS 104 is off.

  Here, when the load current flows out from the output voltage VHTM terminal (the current I1 flowing through the PMOS 103 flows out from the VHTM terminal), the VHTM voltage becomes lower than the set voltage. At this time, the source voltage of the PMOS 103 is the same potential as the VHTM voltage. On the other hand, since the gate terminal of the PMOS 103 is connected to the VREF terminal, the VGS voltage of the PMOS 103 becomes small. When it becomes lower than the voltage Vth, the PMOS 103 is turned off.

  As a result, the current path for supplying current to the current source 102 is not a path from the drain terminal of the PMOS 103 but a path from the heater power supply voltage VH to the current-voltage conversion circuit 105 and the voltage determination circuit 106. At this time, the voltage determined by the current value I2 of the current source 102 and the current-voltage conversion circuit 105 is the VGS voltage of the PMOS 104, and this voltage is set to be a VGS voltage that can sufficiently supply the load current from the output voltage VHTM terminal. Then, current is supplied from the heater power supply voltage VH to the output voltage VHTM via the PMOS 104, and the output voltage VHTM increases.

  According to this circuit configuration, in order to realize a constant voltage source with low output impedance, it is only necessary to sufficiently increase the area of the PMOS 104, and it is necessary to provide a large area for all of the plurality of PMOSs as shown in FIG. Compared to the conventional circuit configuration, the area is small. If the reference voltage VREF voltage is constant, the output voltage VHTM is determined only by the VGS voltage of the PMOS 103 whose reference voltage VREF terminal is connected to the gate as described above. The VGS voltage variation due to the influence is determined by the characteristic variation of one PMOS, and the variation in the process process compared to the conventional circuit configuration that is affected by the influence of the variation in the PMOS process process by multiplying the number of PMOSs connected in multiple stages. It becomes a very strong composition. Furthermore, since the VGS voltage for one PMOS 103 is also affected by a change in the VGS voltage due to a temperature change or the like, the configuration is strong against the change in the VGS voltage.

  Furthermore, in this embodiment shown in FIG. 1, only a PMOS transistor and a resistor are used in a semiconductor integrated circuit using a P-type substrate. Since the PMOS transistor is built in the N well, the PMOS transistor can be connected to as high a voltage as is allowed by the N well and the P-type substrate. Since the N well and the P-type substrate are generally low in concentration, they have a high breakdown voltage.

  Next, the circuit shown in FIG. 2 will be described.

In the example shown in FIG. 2, the current source 102 in FIG. 1 is configured with NMOSs 110 and 111, the current source 101 is configured with PMOSs 115 and 116, the current-voltage conversion circuit is configured with a resistor 109, and the voltage determination circuit is configured with an NMOS transistor 112. Yes. Here, the VHTM voltage is (VREF voltage + VGS voltage of PMOS 107) similarly to the circuit configuration of FIG. 1, and the voltage corresponding to the reference voltage VREF of FIG. 1 is determined by the following equation.
VREF = R22 / (R21 + R22) × (VH−VGS115−VGS111−VGS112)
However, VGS115 = the gate-source voltage of the PMOS 115, VGS111 = the gate-source voltage of the NMOS 111, and VGS112 = the gate-source voltage of the NMOS 112.

  Here, assuming that the current value flowing through the PMOS 116 = I3 and the current value flowing through the NMOS 111 = I4, respectively, when I3 <I4, the current of (I4−I3) is applied to the resistor 109 and the NMOS 112 from the heater power supply voltage. And flows into the NMOS 111. At this time, the VGS voltage of the PMOS 108 is set to be (I4−I3) × (resistance value of the resistor 109) <Vth. Here, Vth is a threshold voltage necessary for turning on the PMOS transistor, and the PMOS 108 is in the off state.

  Here, when the load current flows out from the output voltage VHTM terminal and the VHTM voltage falls below the set voltage, the source voltage of the PMOS 107 whose gate is connected to the VREF terminal is lowered, and the VGS voltage of the PMOS 107 is reduced and turned off. To do. Therefore, in addition to the initial current (I4-I3) of the NMOS 112, a current value I3 similar to that flowing out of the PMOS 116 newly flows into the NMOS 112 via the resistor 109 connected to the heater power supply voltage VH. As a result, the current value flowing into the NMOS 112 = I4. At this time, (resistance value of the resistor 109) × (current value I4 of the NMOS 112) becomes the VGS voltage of the PMOS 108, and if this voltage is set to be a VGS voltage that can sufficiently supply the current from the output voltage VHTM, the PMOS 108 A current is supplied from the heater power supply voltage VH to the output voltage VHTM, and the output voltage VHTM rises.

  Here, I3 = I4 may be set. At this time, in a state before the load current flows out from the output voltage VHTM terminal, since I3 = I4, the VGS voltage of the PMOS 108 becomes 0V, and the PMOS 108 is in the OFF state. Here, when the load current flows out from the output voltage VHTM terminal and the VHTM voltage falls below the set voltage, the VGS voltage of the PMOS 107 becomes small and turns off. At this time, the current value flowing into the NMOS 112 = I4. As a result, (the resistance value of the resistor 109) × (the current value I4 of the NMOS 112) becomes the VGS voltage of the PMOS 108, and this voltage sufficiently supplies the current from the output voltage VHTM. If the VGS voltage can be set, current is supplied from the heater power supply voltage VH to the output voltage VHTM via the PMOS 108, and the output voltage VHTM increases.

  In the present embodiment shown in FIG. 2, NMOS is used for the constant current circuit. However, the voltage between the substrate and the source is 5 V or less, and there is no problem in withstand voltage. The drain voltage of the NMOS 112 is required to have a breakdown voltage equivalent to that of the heater power supply voltage. However, by using an element having a large breakdown voltage, for example, a DMOS transistor (Double diffused MOS transistor), a high breakdown voltage constant voltage circuit is manufactured. May be.

  Next, an ink jet recording head substrate having the circuit structure of any of the above-described embodiments will be described. FIG. 6 is a perspective view showing a detailed configuration of the substrate for an ink jet recording head.

  As shown in FIG. 6, the ink jet recording head substrate is assembled with a flow path wall member 801 for forming a liquid path 805 communicating with a plurality of ejection ports 800 and a top plate 802 having an ink supply port 803. Thus, an ink jet recording type recording head 810 can be configured. In this case, the ink injected from the ink supply port 803 is stored in the internal common liquid chamber 804 and supplied to each liquid path 805, and the base 808 and the heat generating unit 806 are driven in this state, whereby the ink is discharged from the discharge port 800. Is discharged.

  Also, an ink jet recording apparatus capable of realizing high speed recording and high image quality recording by mounting the recording head 810 shown in FIG. 6 on the ink jet recording apparatus main body and controlling a signal applied from the apparatus main body to the recording head 810 is provided. be able to.

  Next, an ink jet recording apparatus using the recording head 810 shown in FIG. 6 will be described. FIG. 7 is an external perspective view showing an ink jet recording apparatus 900 according to an embodiment of the present invention.

  In FIG. 7, the recording head 810 is mounted on a carriage 920 that engages with a spiral groove 921 of a lead screw 904 that rotates via driving force transmission gears 902 and 903 in conjunction with forward and reverse rotation of a driving motor 901. The carriage 920 and the guide 919 can be moved back and forth in the direction of the arrow a or b by the driving force of the drive motor 901. A paper pressing plate 905 for the recording paper P conveyed on the platen 906 by a recording medium feeding device (not shown) presses the recording paper P against the platen 906 along the carriage movement direction.

  The photocouplers 907 and 908 are home position detecting means for confirming the presence of the lever 909 provided in the carriage 920 in the region where the photocouplers 907 and 908 are provided and switching the rotation direction of the drive motor 901. It is. The support member 910 supports the cap member 911 that caps the entire surface of the recording head 810, and the suction unit 912 sucks the inside of the cap member 911 and performs suction recovery of the recording head 810 through the cap opening 513. The moving member 915 enables the cleaning blade 914 to move in the front-rear direction, and the cleaning blade 914 and the moving member 915 are supported by the main body support plate 916. It goes without saying that the cleaning blade 914 is not limited to the illustrated form, and a known cleaning blade can be applied to this embodiment. The lever 917 is provided to start suction for suction recovery and moves with the movement of the cam 918 engaged with the carriage 920, and the driving force from the drive motor 901 is a known transmission means such as clutch switching. The movement is controlled by. A recording control unit (not shown) that gives a signal to the heat generating unit 806 provided in the recording head 810 and controls the driving of each mechanism such as the driving motor 901 is provided on the apparatus main body side.

  The inkjet recording apparatus 900 configured as described above performs recording while the recording head 810 reciprocates over the entire width of the recording paper P with respect to the recording paper P conveyed on the platen 906 by the recording medium feeding device. In addition, since the recording head 810 is manufactured using the ink jet recording head substrate having the circuit structure of each of the embodiments described above, high-precision and high-speed recording is possible.

  Next, the configuration of a control circuit for executing the recording control of the above-described apparatus will be described. FIG. 8 is a block diagram showing the configuration of the control circuit of the inkjet recording apparatus 900. In the figure, showing a control circuit, 1700 is an interface for inputting a recording signal, 1701 is an MPU, 1702 is a program ROM for storing a control program executed by the MPU 1701, and 1703 is various data (the recording signal and the recording supplied to the head). This is a dynamic RAM that stores data and the like. Reference numeral 1704 denotes a gate array that controls supply of print data to the print head 1708, and also controls data transfer among the interface 1700, MPU 1701, and RAM 1703. Reference numeral 1710 denotes a carrier motor for conveying the recording head 1708, and 1709 denotes a conveyance motor for conveying the recording paper. Reference numeral 1705 denotes a head driver for driving the head, and reference numerals 1706 and 1707 denote motor drivers for driving the transport motor 1709 and the carrier motor 1710, respectively.

  The operation of the control configuration will be described. When a recording signal enters the interface 1700, the recording signal is converted into recording data for printing between the gate array 1704 and the MPU 1701. The motor drivers 1706 and 1707 are driven, and the recording head is driven in accordance with the recording data sent to the head driver 1705 to perform printing.

  In the above description, an example in which an ink jet recording head substrate is employed in an ink jet recording head has been described. However, the substrate structure according to the present invention can also be applied to a thermal head substrate, for example.

  The present invention provides an excellent effect particularly in a recording head and a recording apparatus that discharge ink using thermal energy, among inkjet recording methods.

  As for the typical configuration and principle, for example, those performed using the basic principle disclosed in US Pat. Nos. 4,723,129 and 4,740,796 are preferable. . This method can be applied to both a so-called on-demand type and a continuous type. In particular, in the case of the on-demand type, it is arranged corresponding to the sheet or liquid path holding the liquid (ink). By applying at least one drive signal corresponding to the recording information and giving a rapid temperature rise exceeding the boiling point to the electrothermal transducer, the thermal energy is generated in the electrothermal transducer, and the recording head This is effective because the film is boiled on the heat acting surface, and as a result, bubbles in the liquid (ink) can be formed in a one-to-one correspondence with the drive signal. By the growth and contraction of the bubbles, liquid (ink) is ejected through the ejection opening to form at least one droplet. It is more preferable that the drive signal has a pulse shape, since the bubble growth and contraction is performed immediately and appropriately, and thus it is possible to achieve discharge of liquid (ink) having particularly excellent responsiveness. As this pulse-shaped drive signal, those described in US Pat. Nos. 4,463,359 and 4,345,262 are suitable. Further excellent recording can be performed by employing the conditions described in US Pat. No. 4,313,124 of the invention relating to the temperature rise rate of the heat acting surface.

  As the configuration of the recording head, in addition to the combination configuration (straight liquid flow path or right-angle liquid flow path) of the discharge port, liquid path, and electric-heat converter as disclosed in each of the above-mentioned specifications, the heat acting section The configurations using US Pat. No. 4,558,333 and US Pat. No. 4,459,600 which disclose the configuration in which the lens is disposed in the bending region are also included in the present invention. In addition, for a plurality of electrothermal transducers, Japanese Patent Application Laid-Open No. 59-123670 which discloses a configuration in which a common slit is used as a discharge portion of the electrothermal transducer or an opening for absorbing a pressure wave of thermal energy The present invention is also effective as a configuration based on Japanese Patent Application Laid-Open No. 59-138461 which discloses a configuration corresponding to each part.

  Furthermore, as a full-line type recording head having a length corresponding to the width of the maximum recording medium that can be recorded by the recording apparatus, the length is set by combining a plurality of recording heads as disclosed in the above specification. Either a satisfying configuration or a single recording head configuration may be used, but the present invention can exhibit the above-described effects more effectively.

  As shown in FIG. 9, the ink jet recording head 810 includes a recording head portion 811 having a plurality of ejection ports 800 and an ink container 812 that holds ink to be supplied to the recording head portion 811. The ink container 812 is detachably provided on the recording head unit 811 with the boundary line K as a boundary. The ink jet recording head 810 is provided with an electrical contact (not shown) for receiving an electrical signal from the carriage side when mounted on the recording apparatus shown in FIG. 7, and the heater is driven by this electrical signal. . A fibrous or porous ink absorber is provided in the ink container 812 to hold the ink, and the ink is held by these ink absorbers.

  On the other hand, the ink jet recording head 810 shown in FIG. 7 includes a recording head portion 811 and an ink container 812 that are integrally formed.

  Note that the present invention can be applied to a modified or changed embodiment without departing from the spirit of the present invention.

  The present invention can be applied to a system composed of a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), or an apparatus composed of a single device (for example, a copier, a facsimile machine, etc.). May be.

It is the figure which showed the circuit structure of the constant voltage source of one Embodiment of this invention. It is the figure which showed the constant voltage source which comprised the constant current source in the circuit structure of FIG. 1 using PMOS and NMOS. FIG. 6 is a diagram illustrating a circuit configuration of a recording head mounted on a conventional inkjet recording apparatus. FIG. 4 is a circuit diagram showing a configuration of only the conventional constant voltage generating circuit shown in FIG. 3. FIG. 4 is a circuit diagram showing a configuration of only another conventional constant voltage generation circuit shown in FIG. 3. It is a perspective view which shows the detailed structure of the base | substrate for inkjet recording heads. 1 is an external perspective view showing an ink jet recording apparatus according to an embodiment of the present invention. It is a block diagram which shows the structure of the control circuit of an inkjet recording device. It is an external appearance perspective view explaining another form of the inkjet recording head shown in FIG.

Explanation of symbols

101, 102 Constant current source 103, 104, 107, 108, 115, 116 PMOS transistor 105, 106, 109, 113, 114 Resistance 110-112 NMOS transistor 601 Electrothermal conversion element (heater)
602 Power transistor 603 Voltage conversion circuit 604 AND circuit 605 Latch circuit 606 Shift register 607 Voltage generation circuit

Claims (9)

In a constant voltage source that generates and outputs a predetermined voltage from a supply voltage,
A first PMOS transistor formed on a P-type substrate for determining an output voltage;
A second PMOS transistor for supplying an output current;
A first means for supplying a voltage not exceeding the threshold voltage between the gate and source of the second PMOS transistor when the output current is not supplied and supplying a voltage exceeding the threshold voltage when supplying the output current; A constant voltage source characterized by The first means includes
A first current source connected to the source side of the first PMOS transistor, the source of which is connected to the output terminal;
A second current source connected to the drain side of the first PMOS transistor;
A current-voltage conversion circuit and a voltage determination circuit connected in parallel with the first current source and the first PMOS transistor between the supply voltage and the second current source;
The current-voltage conversion circuit has a drain connected to the output terminal and a source connected to the gate of the second PMOS transistor connected to the supply voltage;
The constant voltage source according to claim 1, wherein the second current source has a current value larger than a current value of the first current source.   The constant voltage source according to claim 1, wherein the first PMOS transistor forms a PMOS source follower circuit.   4. The constant voltage source according to claim 1, wherein the second PMOS transistor has a common source. 5.   The constant voltage source according to claim 2, wherein the current-voltage conversion circuit includes a resistor.   The constant voltage source according to claim 2, wherein the voltage determination circuit includes a resistor.   The constant voltage source according to claim 2, wherein the voltage determination circuit includes a transistor.   An electric current is supplied to the electrothermal conversion element by a drive circuit including the constant voltage source according to claim 1 to generate thermal energy to eject ink, and the drive circuit and the electrothermal conversion element are formed on the same substrate. Inkjet recording head. An electric current is supplied to the electrothermal conversion element by a drive circuit including the constant voltage source according to claim 1 to generate thermal energy to eject ink, and the drive circuit and the electrothermal conversion element are formed on the same substrate. A recording apparatus having an inkjet recording head.

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