JP3437423B2 - Recording head and recording apparatus using the recording head - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ink jet type recording head for recording on a recording medium by ejecting ink, and a recording apparatus using the recording head.

[0002]

2. Description of the Related Art FIG. 3 shows a circuit configuration of a conventional ink jet recording head. The electrothermal conversion element (heater) of the recording head as shown in FIG. 3 and its drive circuit are formed on the same substrate by using a semiconductor process technique as disclosed in, for example, Japanese Patent Laid-Open No. 185594/1993. There is.

As shown in FIG. 3, reference numeral 401 is an electrothermal conversion element (heater) for generating heat energy, which is designated by reference numeral 42.
Reference numeral 2 is a power transistor for supplying a desired current to the heater 401, and reference numeral 424 is for supplying current to each heater 401 to temporarily store image data for determining whether or not to eject ink from the nozzle portion of the recording head. A shift register for storing, reference numeral 427 is a transfer clock input terminal for inputting the transfer clock signal CLK provided in the shift register 424, and reference numeral 426 is image data input for serially inputting image data DATA for turning the heater 401 ON / OFF. A terminal, reference numeral 423, is a latch circuit for recording and holding image data for each heater, for each heater, reference numeral 4
Reference numeral 28 is a latch signal input terminal for inputting a latch signal LT for controlling the latch timing of the latch circuit 423, reference numeral 429 is a switch for deciding the timing of flowing current to the heater 401, and 425 is a current for applying a predetermined voltage to the heater. Is a GND line into which the current flowing through the heater 401 and the power transistor 422 flows.

The number of bits of image data stored in the shift register 424, the number of power transistors 422, and the number of heaters 401 are the same.

FIG. 4 is a timing chart of various signals for driving the drive circuit of the recording head shown in FIG. The drive circuit of the recording head shown in FIG. 3 will be described with reference to FIG.

The transfer clock input terminal 427 receives the transfer clock signal CLK for the number of bits of the image data DATA stored in the shift register 424.

Data transfer to the shift register 424 is performed in synchronization with the rising edge of the transfer clock signal CLK.
Image data DATA for turning ON / OFF each heater 401 is input from an image data input terminal 426.
Here, since the number of bits of the image data DATA stored in the shift register 424 and the number of the heaters 410 and the power transistors 422 are the same, as many pulses of the transfer clock signal CLK as the number of the heaters 401 are input to input the image data. After transferring DATA to the shift register 424,
The latch signal LT is given to the latch signal input terminal 428 to hold the image data DATA corresponding to each heater 401 in the latch circuit 423.

After that, the switch 429 is turned on for an appropriate time.
If so, a current flows from the power supply line 425 to the power transistor 422 and the heater 401 according to the period in which the switch 429 is ON, and the current flows into the GND line 430. At this time, the heater 401 generates heat necessary for ejecting ink, and the ink corresponding to the image data is ejected from the nozzle of the recording head.

The circuit configuration described above has already been disclosed in Japanese Patent Laid-Open No. 8-1.
Although disclosed in No. 08536, a circuit configuration shown in FIG. 5 is proposed as an improved type of the circuit configuration shown in FIG.

As shown in FIG. 5, reference numeral 440 is the heater 4.
01 is a power transistor for supplying a desired current, and an nMOS transistor is used. Figure 3
The power transistor shown in is an N connected in Darlington.
Although a PN transistor is used, a CMOS gate is usually used in a so-called logic circuit such as a shift register or a latch circuit in such a circuit configuration. Therefore, at the same time, a Bi-CMOS process is used to form an NPN transistor. Will be used. However, Bi-CMO
The S process has the drawback that it requires a large number of masks for the process and is expensive. Therefore, if an nMOS transistor is used as the power transistor instead of the NPN transistor, the nMOS transistor can be manufactured by a process similar to that of the logic circuit, and therefore the manufacturing cost can be relatively low. What has been described above is the circuit configuration of the recording head manufactured by the so-called CMOS process.

In the circuit structure using this CMOS process, the signal applied to the CMOS logic circuit is 0V / 5.
Since it is a digital signal in which V is Lo / Hi, nMO
Even if a 5V Hi signal is directly applied to the gate of the S power transistor, there is a problem that sufficient drivability cannot be obtained. Therefore, it has been proposed to provide the voltage conversion circuit 451 shown in FIG. 5 for the purpose of increasing the gate voltage and improving drivability.

That is, in the recording head composed of the CMOS logic circuit and the power transistor composed of the nMOS transistor, the amplitude 5V of the signal in the CMOS logic circuit is converted into a higher voltage and then supplied to the gate of the nMOS power transistor. We are working to improve drivability.

[0013]

However, in the above conventional technique, the resistor 452 and the nM in the voltage conversion circuit 451 are connected to each other.
The threshold value of the inverter combined with the OS transistor 453 is determined by the correlation between the resistor 452 and the ON resistance of the nMOS transistor 453, and is lower than that of the CMOS inverter used in the latch circuit 423 or the shift register 424, which causes noise. There was a problem of weakness. Especially in an inkjet printer, the heater 4
01, the current flowing through the nMOS power transistor 440 flows into the GND line 430, and a large noise is generated in the GND line. Therefore, a circuit configuration resistant to noise is required.

Further, in the above-mentioned conventional technique, in the inverter in which the resistor 452 in the voltage conversion circuit 451 and the nMOS transistor 453 are combined, when the switch 429 is turned on while the image signal of the latch circuit 423 is Hi, the interval is kept. A constant current always flows from the power supply line 456 through the resistor 452 and the nMOS transistor 453. This current increases as the number of bits of the image signal Hi of the latch circuit 423 increases. At present, inkjet printers are pursuing high speed and high image quality, and in order to realize them, it is necessary to increase the number of bits to be ejected at the same time as the heater pitch is narrowed and the number of nozzles is increased. The increase in the number of bits to be discharged at the same time means that the number of bits at which the output of the latch circuit 423 becomes Hi increases, that is, the current flowing from the power supply line 456 to the GND line 430 of the voltage conversion circuit increases. . As a result, the voltage flowing through the conversion power supply line 456 causes a voltage drop due to the flowing current, and the voltage applied to the gate of the power transistor 440 drops when multiple bits are simultaneously turned on.
As a result, since the voltage applied to the gate of the power transistor 440 changes depending on the number of ON bits, there is a problem that the stable driving of the nMOS power transistor cannot be performed.

The present invention has been made in view of the above problems,
The purpose is to increase the threshold value of the inverter used in the voltage conversion circuit for improving the drivability of the nMOS power transistor to secure the noise margin of the GND line, and to fluctuate the power supply voltage depending on the number of ON bits. It is an object of the present invention to provide a recording head that suppresses the above and a recording apparatus that uses the recording head.

[0016]

In order to solve the above problems and achieve the object, a recording head of the present invention has the following constitution. That is, in a recording head that has a plurality of recording elements, and that electrically drives each recording element independently to record image data on a recording medium, power is supplied,
A power transistor for energizing and driving the recording element, an output circuit for outputting image data to each of the recording elements at a predetermined timing, and a power supply, and a gate of the power transistor based on the image data CMOS for converting the voltage applied to the transistor and energizing it
A logic circuit, wherein the CMOS logic circuit is a first logic circuit.
The inverter circuit and the first pMOS type element, and the second inverter
A first pMOS-type element and a first pMOS-type element
The output of the inverter circuit of the
Is connected to the second inverter circuit, and the output of the second inverter circuit is
1 is connected to the gate of the pMOS type element .

In order to solve the above problems and achieve the object, the recording head of the present invention has the following constitution. That is,
In a recording head which has a plurality of recording elements and records image data on a recording medium by independently energizing each recording element, power is supplied and a power transistor for energizing the recording elements. An output circuit that outputs image data to each of the recording elements at a predetermined timing, and a power supply are supplied, and the voltage applied to the gate of the power transistor is converted based on the image data to drive by energization. A first CM including a first pMOS transistor and a first nMOS transistor.
The second pMO transistor includes an OS inverter circuit, a second pMOS transistor, a second CMOS inverter circuit including a third pMOS transistor and a second nMOS transistor, and a fourth pMOS transistor.
The source of the S-transistor is connected to the power supply and the second p
A drain of the MOS transistor is connected to a source of the first pMOS transistor, a drain of the first pMOS transistor is connected to a drain of the first nMOS transistor, and a source of the first nMOS transistor is grounded; The source of the fourth pMOS transistor is connected to the power supply, the drain of the fourth pMOS transistor is connected to the source of the third pMOS transistor, and the drain of the third pMOS transistor is the second nMOS transistor. Is connected to the drain of the second nMOS transistor, the source of the second nMOS transistor is grounded, and the gate of the second pMOS transistor is connected to the drain of the third pMOS transistor and the second nMOS transistor.
Connected to the connection with the drain of the MOS transistor,
The gate of the fourth pMOS transistor is connected to the drain of the first pMOS transistor and the first nMOS.
The gates of the first pMOS and nMOS transistors are connected to the connection with the drain of the transistor, and are commonly connected to a terminal for outputting the same signal as the output of the image signal, and the third pMOS and the second nMOS are connected. The gates of the transistors are commonly connected to a terminal for outputting a signal obtained by inverting the output of the image signal, and the third pMOS and the second n are connected.
A signal obtained by converting the amplitude of the image signal is output from the connection of the drain of the MOS transistor to the gate of the power transistor.

In order to solve the above-mentioned problems and to achieve the object, the recording apparatus of the present invention is configured to mount the recording head having the above characteristics.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[Circuit Configuration of First Embodiment] The circuit configuration of the first embodiment will be described. FIG. 1 shows the first of the present invention.
3 is a circuit diagram of the embodiment of FIG.

As shown in FIG. 1, reference numeral 121 is an electrothermal conversion element (hereinafter referred to as a heater) that generates heat for ejecting ink, and reference numeral 122 is a power transistor for supplying a desired current to the heater 121. , Reference numeral 124 is a shift register for supplying electric current to each heater 121 and temporarily storing image data for determining whether or not ink is ejected from the nozzles of the recording head, and reference numeral 127 is a transfer register provided in the shift register 124. A transfer clock input terminal for the clock signal CLK, reference numeral 126 indicates ON / OF of the heater 121.
Image data input terminal for serially inputting image data DATA to be F, reference numeral 123 is a latch circuit for recording and holding image data for each heater 121 for each heater, and reference numeral 128 is for controlling the latch timing to the latch circuit 123. Latch signal input terminal for inputting the latch signal LT of No. 1, reference numeral 129 is a switch for deciding the timing of flowing the current to the heater 121, and reference numeral 131 is for converting the voltage amplitude of the digital signal from the switch 129 into a higher voltage amplitude, and the power transistor A voltage conversion circuit to be supplied to the gate of 122, reference numeral 140 is the voltage conversion circuit 13
1 is a power supply line for supplying power, 130 is a GND line into which the current supplied to the heater 121 and the power transistor 122 flows, and reference numeral 132 is the latch circuit 12.
3 is a CMOS inverter element that inverts the image data to form a part of the voltage conversion circuit 131, and the reference numeral 133 is a CMOS inverter element that further inverts the image data inverted by the CMOS inverter element 132, the reference numeral 13
5, 136 are pMOS and nMOS transistors, respectively, which are C
It constitutes a MOS inverter. Reference numeral 134 indicates the CMOS inverters 135 and 136 and the latch circuit 123.
The buffer pMOSs for dividing the voltage supplied from the power supply line 140 in order to be able to drive with the 5V input which is the output voltage from the device, reference numerals 138, 139 and 137 are the CMOS inverters 135, 136 and the buffer pMOS 134, respectively. NMOS arranged in pairs,
pMOS and buffer pMOS. Here, the gate of the buffer pMOS 134 has a pMOS 138 and an nMOS 139 which are the output parts of the paired CMOS inverter.
Is connected to the connection part of. Also, pMOS for buffer
Similarly, the gate of 137 has pMOS135 and nMOS13.
6 are connected to the connection part.

[Circuit Operation] Here, the circuit operation when the output from the latch circuit 123 is Hi will be described.

When the output from the latch circuit 123 is Hi, the output of the CMOS inverter element 132 becomes Lo, and Lo is applied to the input portion of the CMOS inverter composed of the pMOS transistor 138 and the nMOS transistor 139. For buffer pMOS1
Since the ON / OFF state of 37 is indeterminate, the nMOS
The pMOS transistor 138 and the nMOS transistor 1 which become the voltage applied to the gate of the power transistor 122.
Hi / L of output voltage of CMOS inverter consisting of 39
o depends on the ON / OFF state of the buffer pMOS 137. The gate of the buffer pMOS 137 is connected to the output section of the CMOS inverter including the pMOS transistor 135 and the nMOS transistor 136 forming a pair. This pMOS transistor 135 and nMO
The input portion of the CMOS inverter including the S-transistor 136 includes the latch circuit 123 and the CMOS inverter 1
The output voltage that has passed through 32 and 133 is input. Since the output from the latch circuit 123 is described as Hi here, the pMOS transistor 135, the nMOS
The gate of the transistor 136 is provided with Hi from the logic circuit.
Input signal 5V is applied to the nMOS transistor 13
6 is energized. Although the gate voltage 5V is applied to the pMOS transistor 135, it can be considered that the pMOS transistor 135 is turned on when the voltage supplied from the power supply line 140 is higher than 5V. However, since there is a voltage drop in the buffer pMOS 134, the output voltage becomes lower than the voltage of the power supply line 140, and this voltage is the buffer pMOS 134, pMOS.
Transistor 135 and nMOS transistor 136
It can be controlled by changing the size of. Therefore, the output voltage of the CMOS inverter composed of the pMOS transistor 135 and the nMOS transistor 136 applied to the gate of the buffer pMOS 137 is the power supply line 14
It can be made lower than 0 voltage, and this value can be
It can be set to a value at which 137 is turned on. As a result of being set in this way and turning on the buffer pMOS 137, the output of the CMOS inverter composed of the pMOS transistor 138 and the nMOS transistor 139 is fixed to Hi, the voltage of the power supply line 140 is applied, and the latch circuit 123 outputs the voltage. Input signal 5V can be converted into a voltage supplied from the power supply line 140 and supplied to the nMOS power transistor 122. Further, since this output voltage is also connected to the gate of the buffer pMOS134, the buffer pMOS134 is instantly turned off, and the buffer pMOS134, pMOS134
The penetrating current flowing through the transistor 135 and the nMOS transistor 136 only slightly flows at the moment of switching ON / OFF. As a result, buffer pMOS
Since the voltage applied to the gate of 137 is fixed at 0V, the ON state of the buffer pMOS 137 can be made more reliable.

When the output voltage from the latch circuit 123 is Lo, the pMOS for buffer 134, the CMOS inverters 135 and 136 and the pMOS for buffer 137, C.
The MOS inverters 138 and 139 are in the opposite states, and the signal output to the gate of the nMOS power transistor 122 becomes 0V. That is, the latch circuit 12
When the output of No. 3 is Hi (with image data), the voltage of the power supply 140 is applied to the gate of the power transistor 122, the power transistor 122 is turned on, current flows through the heater 101, and recording by ink ejection is performed. .

At this time, if the voltage of the power supply line 140 is set higher than the power supply voltage of 5 V which is the power supply voltage of the shift register 124 and the latch circuit 123, the voltage is applied to the gate of the power transistor 122, and the voltage of the power transistor 122. Drivability can be improved. The voltage of the power supply line 140 at this time can be set arbitrarily, but for example, it should be set as high as possible within the allowable range of breakdown withstand voltage of the CMOS inverter and withstand voltage of the gate oxide film of the MOS transistor. Is desirable. Further, the voltage of the power supply line 125 to the heater 121 and the power supply line 140 of the voltage conversion circuit 131.
It is also possible to share the above, and thus, it is not necessary to provide two power supply lines, desired characteristics can be obtained, and the circuit configuration can be simplified.

In this case, ON / O of the voltage conversion circuit 131
The threshold value of the FF is the voltage of the power supply line 140, the buffer pMOSs 134 and 137, the pMOS transistors 135 and 138 that form the CMOS inverter, and the nMOS.
Since it is determined by the sizes of the transistors 136 and 139, they can be adjusted to any value by optimizing them. For example, turning on the buffer pMOSs 134 and 137
If the resistance is sized to be high, the threshold will be low, and if the ON resistance is low, the threshold will be high. By adjusting the size in this way and setting it to a threshold value near 2.5 V, for example, a high noise margin can be secured as compared with the conventional voltage conversion circuit composed of a resistor and an nMOS transistor.

[Circuit Configuration of Second Embodiment] The circuit configuration of the second embodiment will be described. FIG. 2 shows the second aspect of the present invention.
3 is a circuit diagram of the embodiment of FIG.

As shown in FIG. 2, reference numeral 151 is a voltage supply circuit for generating a voltage from the power supply line 125 of the heater 121 to the power supply line 140 of the voltage conversion circuit 131. Reference numerals 152 and 153 are resistors, and reference numeral 154 is nMO.
S-transistor, reference numeral 155 is nMOS transistor 1
The nMOS transistor 154 and the resistor 155 form a source follower type buffer with a resistor connected to the source of 54. In the first embodiment, the voltage of the power supply line 140 of the voltage conversion circuit 131 is preferably set as high as possible without exceeding the breakdown withstand voltage of the CMOS inverter and the gate withstand voltage of the MOS. It may be shared with the power line. However, the driving voltage to the heater is usually 2
It is often set to a high value of 0 V or higher, and the CMO
The breakdown voltage of an S inverter is often made by a process up to about 15V. Moreover, since the gate breakdown voltage of the MOS depends on the gate oxide film thickness, it is necessary to set the voltage sufficiently lower than the insulation breakdown voltage of the gate oxide film, and the optimum voltage of the voltage conversion circuit and the heater driving voltage may not match. difficult. Furthermore, providing a separate power supply line for the voltage conversion circuit is a heavy burden depending on the entire system,
It may lead to higher costs.

Therefore, in the second embodiment, the resistor 1
The power supply line 12 of the heater is determined by the voltage division ratio of 52 and 153.
5, an arbitrary voltage is generated, a source follower circuit composed of an nMOS transistor 154 as a buffer and a resistor 155 is connected to the voltage, and the voltage is supplied to the voltage conversion circuit. It is possible to supply the optimum voltage for the.

In particular, in the case where the conventional voltage conversion circuit composed of the combination of the nMOS transistor and the resistor is used in the circuit configuration of the second embodiment, the voltage drop caused by the current flowing when the nMOS transistor is turned on is absorbed. In order to achieve this, it was necessary to make the nMOS transistor as a buffer sufficiently large, and it was necessary to increase the chip size. However, when the circuit configuration of the present invention is applied, the current of the voltage conversion circuit is instantaneously switched by ON / OFF switching. It does not require a large buffer transistor as in the past, so the chip size can be reduced.

As described above, according to the first and second embodiments, the output of the latch circuit 123 and the power n
Between the gate of the MOS transistor 122 and the power n
A voltage conversion circuit is provided for the purpose of improving the drivability of the MOS transistor 122, and the voltage conversion circuit is configured to have buffer pMOS transistors 134 and 137, pMOS transistors 135 and 138, and an nMOS transistor 1.
By using CMOS inverters 36 and 139 and adjusting their sizes, a voltage conversion circuit with a high noise margin can be realized.

Further, the current flowing through the voltage conversion circuit is ON /
Since it only flows momentarily when switching OFF, stable heater driving can be realized without depending on the number of bits to be turned ON.

[Inkjet Recording Head Substrate] Next, an inkjet recording head substrate having the circuit structures of the first and second embodiments will be described. FIG. 6 is a perspective view showing the detailed configuration of the inkjet recording head substrate.

As shown in FIG. 6, the ink jet recording head substrate has a liquid passage 80 communicating with a plurality of ejection ports 800.
By assembling the flow path wall member 801 for forming 5 and the top plate 802 having the ink supply port 803,
An ink jet recording type recording head 810 can be configured. In this case, the ink injected from the ink supply port 803 is stored in the internal common liquid chamber 804 and supplied to each liquid path 805, and in this state, the base 808 and the heat generating portion 806 are driven to eject the ink from the ejection port 800. Is discharged.

Further, by mounting the recording head 810 shown in FIG. 6 in the ink jet recording apparatus main body and controlling the signal given from the apparatus main body to the recording head 810, an ink jet recording apparatus capable of realizing high speed recording and high image quality recording. Can be provided.

[Inkjet Recording Device Main Body] Next, an inkjet recording device using the recording head 810 shown in FIG. 6 will be described. FIG. 7 is an external perspective view showing an inkjet recording apparatus 900 according to an embodiment of the present invention.

In FIG. 7, the recording head 810 is driven by a driving force transmission gear 90 in association with the forward and reverse rotations of the driving motor 901.
It is mounted on a carriage 920 that engages with a spiral groove 921 of a lead screw 904 that rotates via a rotary shaft 2, 903, and is driven by a driving force of a driving motor 901 along with a carriage 920 along a guide 919 along an arrow a or b.
It is possible to reciprocate in any direction. The paper pressing plate 905 for the recording paper P that is conveyed onto the platen 906 by the recording medium feeding device (not shown) presses the recording paper P against the platen 906 along the carriage movement direction.

The photocouplers 907 and 908 are the photocouplers 90 of the lever 909 provided on the carriage 920.
Home position detecting means for confirming the presence in the area where 7, 908 are provided and for switching the rotation direction of the drive motor 901 and the like. The support member 910 is the recording head 8
10 supports the cap member 911 that caps the entire surface, and the suction means 912 sucks the inside of the cap member 911,
The suction recovery of the recording head 810 is performed through the opening 513 in the cap. The moving member 915 allows the cleaning blade 914 to move in the front-rear direction, and the cleaning blade 914 and the moving member 915 are supported by the main body support plate 916. Needless to say, the cleaning blade 914 is not limited to the illustrated form, but a known cleaning blade can be applied to this embodiment. Also, the lever 91
Reference numeral 7 is provided to start suction for suction recovery, moves with the movement of the cam 918 engaging with the carriage 920, and the driving force from the driving motor 901 is controlled by a known transmission means such as clutch switching. To be done. A recording control unit (not shown) that gives a signal to the heat generating unit 806 provided in the recording head 810 and controls the drive of each mechanism such as the drive motor 901 is provided on the apparatus main body side.

In the ink jet recording apparatus 900 having the above structure, the platen 906 is provided by the recording medium feeding apparatus.
The recording head 810 performs recording on the recording paper P conveyed above while reciprocating over the entire width of the recording paper P. The recording head 810 is an inkjet recording head having the circuit structure of each of the above-described embodiments. Since it is manufactured using the substrate for use, high-precision and high-speed recording is possible.

[Structure of Control Circuit] Next, the structure of the control circuit for executing the recording control of the above-mentioned apparatus will be described. FIG. 8 is a block diagram showing the configuration of the control circuit of the inkjet recording apparatus 900. In the figure showing a control circuit, 1700 is an interface for inputting a recording signal, 1701 is an MPU, 1702 is a program ROM for storing a control program executed by the MPU 1701, 1
A dynamic RA 703 stores various data (the above-mentioned recording signals, recording data supplied to the head, etc.).
It is M. A gate array 1704 controls supply of print data to the print head 1708, and also controls data transfer between the interface 1700, the MPU 1701, and the RAM 1703. 1710 is a recording head 1708
1709 is a carrier motor for carrying the recording paper, and 1709 is a carrying motor for carrying the recording paper. Reference numeral 1705 is a head driver for driving the head, and 1706 and 1707 are motor drivers for driving the carry motor 1709 and the carrier motor 1710, respectively.

The operation of the above control structure will be described. When a recording signal is input to the interface 1700, the gate array 17
The print signal is converted between the print signal 04 and the MPU 1701 to print data for printing. Then, the motor driver 17
06 and 1707 are driven, and the head driver 1
The print head is driven according to the print data sent to 705, and printing is performed.

In the above description, an example in which the ink jet recording head substrate is used in an ink jet recording head has been described, but the substrate structure according to the present invention can be applied to a thermal head substrate, for example. .

The present invention provides excellent effects particularly in a recording head and a recording apparatus of the type proposed by the applicant among the ink jet recording systems, which ejects ink by utilizing thermal energy.

With regard to its typical structure and principle, it is preferable to use the basic principle disclosed in, for example, US Pat. Nos. 4,723,129 and 4,740,796. This method is applicable to both so-called on-demand type and continuous type, but in particular,
In the case of the on-demand type, the electrothermal converter arranged corresponding to the sheet or liquid path holding the liquid (ink) has a rapid temperature rise corresponding to the recorded information and exceeding the boiling point. By applying at least one drive signal that gives a heat energy to the electrothermal converter, the film is boiled on the heat-acting surface of the recording head, and as a result, the liquid (ink It is effective because bubbles can be formed inside. The liquid (ink) is ejected through the ejection openings by the growth and contraction of the bubbles to form at least one droplet. It is more preferable to make the driving signal into a pulse shape because bubbles can be grown and contracted immediately and appropriately, and thus a liquid (ink) with excellent responsiveness can be ejected. As the pulse-shaped drive signal, those described in US Pat. Nos. 4,463,359 and 4,345,262 are suitable. In addition,
US Pat. No. 4, of the invention relating to the rate of temperature rise of the heat acting surface,
If the conditions described in the specification of 313,124 are adopted,
Further excellent recording can be performed.

As the constitution of the recording head, in addition to the combination constitution of the discharge port, the liquid passage, and the electric heat conversion body (the linear liquid passage or the right-angled liquid passage) as disclosed in the above-mentioned respective specifications. U.S. Pat.No. 4,558,333, U.S. Pat.
The structure using the specification of No. 9,600 is also included in the present invention. In addition, Japanese Laid-Open Patent Publication No. 123670/1984, which discloses a configuration in which a common slit is used as a discharge portion of a plurality of electrothermal converters, and an opening for absorbing a pressure wave of thermal energy are provided. The present invention is also effective as a configuration based on JP-A-59-138461, which discloses a configuration corresponding to the ejection portion.

Further, as a full line type recording head having a length corresponding to the width of the maximum recording medium which can be recorded by the recording device, a combination of a plurality of recording heads as disclosed in the above-mentioned specification is used. The present invention can exert the above-mentioned effects more effectively, although it may have a configuration satisfying the length or a configuration as one recording head integrally formed.

[Other Form of Recording Head] As shown in FIG. 9, an ink jet recording head 810 holds a recording head portion 811 having a plurality of ejection ports 800 and ink to be supplied to the recording head portion 811. And an ink container 812. The ink container 812 is detachably attached to the recording head unit 811 with the boundary line K as a boundary. The ink jet recording head 810 is provided with an electric contact (not shown) for receiving an electric signal from the carriage side when mounted on the recording apparatus shown in FIG. 7, and the heater is driven by this electric signal. . A fibrous or porous ink absorber is provided inside the ink container 812 to hold the ink, and the ink is held by these ink absorbers.

On the other hand, in the ink jet recording head 810 shown in FIG. 7, the recording head portion 811 and the ink container 812 are integrally formed.

The present invention can be applied to a modification or change of the above embodiment without departing from the spirit of the present invention.

Even when the present invention is applied to a system composed of a plurality of devices (for example, host computer, interface device, reader, printer, etc.), a device composed of one device (for example, copying machine, facsimile device, etc.) )
May be applied to.

[0051]

As described above, according to the present invention,
It is possible to increase the threshold value of the inverter used in the voltage conversion circuit for improving the drivability of the power transistor to secure the noise margin of the GND line and suppress the fluctuation of the power supply voltage depending on the number of ON bits.

[0052]

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a second embodiment of the present invention.

FIG. 3 is a diagram showing a circuit configuration of a conventional inkjet recording head.

FIG. 4 is a timing chart of various signals for driving the drive circuit of the recording head shown in FIG.

FIG. 5 is a diagram showing a circuit configuration of a conventional inkjet recording head.

FIG. 6 is a perspective view showing a detailed configuration of a substrate for an inkjet recording head.

FIG. 7 is an external perspective view showing an inkjet recording apparatus according to an embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a control circuit of the inkjet recording apparatus.

9 is an external perspective view illustrating another form of the inkjet recording head shown in FIG. 7. FIG.

[Explanation of symbols]

121 ... Heater 122 ... nMOS power transistor 123 ... Latch circuit 124 ... Shift register 131 ... Voltage conversion circuit 151 ... Voltage generation circuit

─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-11-88124 (JP, A) JP-A-10-151746 (JP, A) JP-A-60-61271 (JP, A) JP-A-59- 214668 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) B41J 2/05 B41J 2/01

Claims (8)

(57) [Claims] 1. A recording head having a plurality of recording elements, wherein each recording element is independently energized to record image data on a recording medium, and power is supplied to energize the recording elements. Power transistor, an output circuit that outputs image data to each of the recording elements at a predetermined timing, and power is supplied to convert the voltage applied to the gate of the power transistor based on the image data. And a CMOS logic circuit for energizing and driving the same. The CMOS logic circuit comprises a first inverter circuit and a first inverter circuit.
1 pMOS type element, second inverter circuit and second
And a pMOS type element of
The output is connected to the gate of the second pMOS-type device,
The output of the second inverter circuit is the first pMOS type element.
A recording head characterized in that it is connected to the gate of . 2. The first and second CMOS logic circuits invert the image data and input the inverted image data to the second inverter circuit.
2. The recording head according to claim 1 , further comprising: the CMOS inverter element of 1 ), and a second CMOS inverter element that inverts the inverted image data again and inputs the inverted image data to the first inverter circuit. 3. A power supply supplied to the power transistor for energizing the recording element, and the CMOS.
Recording head according to claim 1 or 2, characterized in that a common and power supplied to the logic circuit. 4. The recording head according to claim 3 , further comprising a voltage generation circuit connected to a power supply supplied to the power transistor and generating a power supply voltage supplied to the CMOS logic circuit. . 5. The recording head according to claim 1, wherein the recording head is an inkjet recording head that performs recording by ejecting ink. 6. The recording head is a recording head which ejects ink by utilizing thermal energy, and is provided with a thermal energy converter for generating thermal energy applied to the ink. Item 5. The recording head according to item 5 . 7. A recording head having a plurality of recording elements, wherein each recording element is independently energized to record image data on a recording medium, and power is supplied to energize the recording elements. Power transistor, an output circuit that outputs image data to each of the recording elements at a predetermined timing, and power is supplied to convert the voltage applied to the gate of the power transistor based on the image data. And a CMOS logic circuit for energization driving, wherein the CMOS logic circuit is a first CMOS including a first pMOS transistor and a first nMOS transistor.
An inverter circuit, a second pMOS transistor, a second CMOS inverter circuit composed of a third pMOS transistor and a second nMOS transistor, and a fourth pMOS transistor.
A MOS transistor, a source of the second pMOS transistor is connected to a power source, a drain of the second pMOS transistor is connected to a source of the first pMOS transistor, and a drain of the first pMOS transistor. Is the first nM
The first nM is connected to the drain of the OS transistor.
The source of the OS transistor is grounded, the source of the fourth pMOS transistor is connected to the power supply, the drain of the fourth pMOS transistor is connected to the source of the third pMOS transistor, and the source of the third pMOS transistor is connected to the source of the third pMOS transistor. The drain is the second nM
The second nM is connected to the drain of the OS transistor.
The source of the OS transistor is grounded, and the gate of the second pMOS transistor is connected to the drain of the third pMOS transistor and the second nMOS.
A gate of the fourth pMOS transistor is connected to a drain of the transistor, and a gate of the fourth pMOS transistor is connected to a drain of the first pMOS transistor and the first nMOS.
The gates of the first pMOS and nMOS transistors are connected to the connection with the drain of the transistor, and are commonly connected to a terminal that outputs the same signal as the output of the image signal, and the third pMOS and the second nMOS. The gate of the transistor is commonly connected to a terminal for outputting a signal obtained by inverting the output of the image signal, and an image signal is output from the connection part of the drains of the third pMOS and second nMOS transistors to the gate of the power transistor. A recording head characterized in that a signal obtained by converting the amplitude of is output. 8. A recording apparatus comprising the recording head according to any one of claims 1 to 7 .