JP2005019590A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To raise the reuse efficiency of a substrate in a semiconductor device manufacturing method wherein, after a semiconductor thin film is formed on the substrate, the substrate is divided into individual semiconductor devices. <P>SOLUTION: On the top of the substrate (11), an etching stopper layer (13), a peel-off layer (14), and the semiconductor thin film (20) are formed in order. After forming a semiconductor element in the semiconductor thin film (20), a trench (21) is formed in the semiconductor thin film (20) and in the peel-off layer (14) using a first etchant, for example, sulfuric acid and hydrogen peroxide; and then the peel-off layer (14) is removed using a second etchant, for example, hydrofluoric acid. The etching stopper layer (13) is less likely to be etched by the first etchant (sulfuric acid and hydrogen peroxide) than the semiconductor thin film (20) and the peel-off layer (14), and the semiconductor thin film (20) is less likely to be etched by the second etchant (hydrofluoric acid) than the peel-off layer (14). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device that enables a semiconductor device to be reused by forming a semiconductor thin film on a substrate and then separating it to manufacture the semiconductor device. The present invention also relates to a laminate used in the manufacturing method as described above. The present invention is used, for example, when a row of light emitting elements is formed by a semiconductor thin film.
[0002]
[Prior art]
As a method for forming a light emitting element at a low cost, there is a method in which an intermediate layer is formed on a sapphire substrate, a compound semiconductor layer is formed thereon, and a light emitting portion is formed there (Patent Document 1).
[0003]
[Patent Document 1]
JP-A-7-202265
[0004]
Further, when a GaAs-based semiconductor is used as the compound semiconductor, it is known to perform as shown in FIGS.
[0005]
In this method, first, as shown in FIG. 22, Al having a thickness of about 5 μm is formed on a GaAs substrate 51. _0.7 Ga _0.3 An As layer 52 is formed, and a GaAs thin film 53 having a thickness of about 30 μm is formed thereon.
[0006]
Thereafter, as shown in FIG. 23, by selectively immersing in hydrofluoric acid (HF), Al is selectively removed. _0.7 Ga _0.3 The As layer 52 is removed by etching, and the GaAs thin film 53 can be separated from the GaAs substrate 51.
[0007]
[Problems to be solved by the invention]
When peeling the semiconductor thin film by the method described above, for example, if the semiconductor substrate remaining after peeling the semiconductor thin film can be reused as a substrate for obtaining the semiconductor thin film, the material utilization efficiency can be improved. Conceivable.
[0008]
However, as a method of obtaining a large number of semiconductor thin films from a large-diameter substrate by using the above-described peeling method, for example, as shown in FIG. 55, a selective etching layer for peeling (for example, Al _0.7 Ga _0.3 (As layer) 52 is exposed, and selective etching layer 52 is etched away to obtain a large number of semiconductor thin films. However, the AlGaAs layer 52 is also etched by the etchant that etches the GaAs thin film 53. For example, generally well-known phosphoric acid perwater (phosphoric acid + hydrogen peroxide water + water) or sulfuric acid perwater (sulfuric acid + hydrogen peroxide water + water) for etching the GaAs thin film 53 is only the GaAs thin film 53. In addition, the AlGaAs layer 52 is also etched. Therefore, when the groove 55 for division is formed, there is a problem that etching may penetrate the AlGaAs layer 52 and reach the GaAs substrate 51. When the etching reaches the substrate 51, a process for flattening the surface is required prior to the reuse of the substrate 51, which is not efficient.
[0009]
An object of the present invention is to solve the above-described problems and to provide a method for manufacturing a semiconductor device capable of efficiently reusing a substrate, and a laminate used in such a manufacturing method.
[0010]
[Means for Solving the Problems]
The present invention
A substrate,
An etching stopper layer formed on the substrate;
A first release layer formed on the etching stopper layer;
A semiconductor thin film formed on the first release layer;
With
The etching stopper layer is less likely to be etched by the first etchant than the semiconductor thin film,
The semiconductor thin film is less likely to be etched by the second etchant than the first release layer.
There is provided a laminate characterized by the above.
The present invention also provides a step of preparing a laminate as described above,
Forming a semiconductor element on the semiconductor thin film;
Forming a groove in the semiconductor thin film using the first etching solution;
Removing the first release layer using the second etchant;
The manufacturing method of the semiconductor device which has this.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. Each drawing schematically shows the features of the embodiment, and does not limit the details of the dimensional relationship or positional relationship.
The semiconductor thin film according to the following embodiment constitutes a light emitting diode array (LED array), which is bonded to another semiconductor substrate and connected to a drive circuit formed on the other semiconductor substrate. This is used to form a composite semiconductor device comprising a drive circuit formed on a substrate and an LED array as a driven element formed in a semiconductor thin film.
In the following embodiments, the semiconductor thin film is composed of a plurality of layers, but the present invention can also be applied to a case where the semiconductor thin film is formed of a single layer.
[0012]
First embodiment
1 to 4 are a schematic cross-sectional view and a schematic plan view for explaining the manufacturing method according to the first embodiment of the present invention. Hereinafter, the first embodiment will be described with reference to these drawings.
[0013]
First, as shown in FIG. 1, a semiconductor substrate, for example, an n-type GaAs substrate 11, a GaAs buffer layer 12 formed thereon, for example, (Al _x Ga _1-x ) _y In _1-y P etching stopper layer 13, an AlAs release layer 14 formed thereon, an n-type GaAs lower contact layer 15 formed thereon, and an n-type Al layer formed thereon, for example. _s Ga _1-s As lower clad layer 16 and, for example, p-type Al formed thereon _t Ga _1-t As active layer 17 and, for example, p-type Al formed thereon _u Ga _1-u A laminated body having an As upper cladding layer 18 and, for example, a p-type GaAs upper contact layer 19 formed thereon is prepared.
[0014]
Such a laminate can be formed as follows. That is, on a semiconductor substrate, for example, an n-type GaAs substrate 11, for example, a GaAs buffer layer 12, such as (Al _x Ga _1-x ) _y In _1-y P etching stopper layer 13, for example, AlAs release layer 14, for example, n-type GaAs lower contact layer 15, for example, n-type Al _s Ga _1-s As lower cladding layer 16, for example, p-type Al _t Ga _1-t As active layer 17, for example, p-type Al _u Ga _1-u An As upper cladding layer 18, for example, a p-type GaAs upper contact layer 19 is formed in order.
These layers can be formed, for example, by epitaxial growth by metal organic chemical vapor deposition (MOCVD).
[0015]
Here, the lower contact layer 15, the lower clad layer 16, the active layer 17, the upper clad layer 18, and the upper contact layer 19 are separated from the substrate 11 by peeling and bonded to another semiconductor substrate later. 20 is configured. The semiconductor thin film 20 in the illustrated example is used as an LED array, and the lower contact layer 15 and the upper contact 19 serve as electrode contact layers in the LED after the semiconductor thin film 20 is peeled off.
[0016]
On the other hand, the peeling layer 14 is selectively etched and dissolved or decomposed in order to separate the semiconductor thin film 20 from the substrate 11 by peeling. In addition, the etching stopper layer 13 is used to stop the etching in forming the groove for dividing the semiconductor thin film 20 as will be described later.
The buffer layer 12 is for relaxing the lattice constant mismatch between the substrate 11 and the semiconductor thin film 20 and also relaxing the stress due to the difference in thermal expansion coefficient between the substrate 11 and the semiconductor thin film 20.
[0017]
The active layer may be divided into two upper and lower layers, the lower active layer may be n-type, and the upper active layer may be p-type.
Furthermore, the lower contact layer 15 and the lower cladding layer 16 may be p-type, and the upper cladding layer 18 and the upper contact layer may be n-type. In this case, when the active layer is divided into two upper and lower layers, the lower side is p-type and the upper side is n-type.
[0018]
In addition, instead of the heterojunction type LED as described above, a homojunction type LED can also be configured. In this case, after each layer is epitaxially grown, impurity diffusion is performed by the solid phase diffusion method from the surface of the uppermost layer to form a pn junction in the active layer.
Moreover, the LED which formed the epitaxial layer of the same composition and formed the pn junction in this epitaxial layer may be sufficient. For example, an n-type GaAs layer may be formed as an epitaxial semiconductor layer, Zn may be diffused, and an n-type GaAs layer / p-type GaAs layer may be laminated.
[0019]
After forming the stacked body or the stacked structure shown in FIG. 1, the semiconductor element is formed by performing element isolation (for example, etching away to the active layer other than the light emitting region) or formation of the diffusion region described above. Form. As will be described in detail below, the semiconductor thin film 20 is divided into a plurality of semiconductor thin film pieces by forming the grooves 21, and the semiconductor element is formed in each semiconductor thin film piece formation scheduled region. In this embodiment, it is assumed that each semiconductor thin film constitutes an LED array, and an LED array composed of a plurality of LED elements is formed in each semiconductor thin film piece.
[0020]
In the description of the present embodiment, as will be described later, after forming a semiconductor element, for example, an LED array in each semiconductor thin film piece formation scheduled region, separation into each semiconductor thin film piece and the separation from the first substrate are performed. Although the manufacturing process which peels a semiconductor thin film piece is demonstrated, you may make it as follows. That is, the semiconductor thin film piece is separated from the first substrate after being divided by the groove 21 and bonded to the second substrate, and then a semiconductor element is formed in the semiconductor thin film (for example, other than the light emitting region). It is also possible to etch away at least part of the active layer and perform necessary interlayer insulating film formation / processing, electrode formation, wiring formation, etc.).
[0021]
After forming the semiconductor element as described above, as shown in FIGS. 2 and 3, etching is performed to form the groove 21. This etching is performed to divide the semiconductor thin film 20 into a plurality of semiconductor thin film pieces by the grooves 21, and the region occupied by each semiconductor thin film piece is indicated by the symbol R. In FIG. 2, only two of the plurality of semiconductor thin film pieces and regions R are shown, and only six are shown in FIG. In this specification, as long as it is considered that confusion does not occur, a semiconductor thin film piece obtained by division is also called a semiconductor thin film.
[0022]
In order to perform etching, an etching mask pattern is first formed on the upper contact layer 19 using a photomask (not shown) using a photosensitive material such as a photoresist, and is immersed in an etching solution through the mask pattern.
[0023]
As an etching solution, an etching rate of each layer constituting the semiconductor thin film 20 is high, and an etching rate of the stopper layer 13 positioned between the semiconductor thin film 20 and the substrate 11 is low. For example, sulfuric acid / hydrogen peroxide (sulfuric acid / hydrogen peroxide solution) / Pure water = 16/1/1), phosphoric acid perwater (phosphoric acid / hydrogen peroxide water / water = 12/8/80), or citric acid perwater.
In other words, the stopper layer 13 is a material that is relatively difficult to be etched by the etching solution used for etching the semiconductor thin film 20, that is, a material that has a lower etching rate than the semiconductor thin film 20 and the release layer 14. It is configured.
[0024]
As shown in FIG. 2, this etching is terminated when the etching proceeds to the upper surface of the etching stopper layer 13. That is, in the state shown in FIG. 2, the etching groove 21 penetrates the peeling layer 14 to completely expose the peeling layer 14 in the thickness direction, while (Al _x Ga _1-x ) _y In _1-y It stops at the P etching stopper layer 13.
Due to the difference in etching rate as described above, the progress of etching can be reliably stopped on the upper surface of the stopper layer 13 without strictly controlling the etching conditions such as the etching time.
[0025]
The width Gw of the etching groove 21 is, for example, about 50 μm to 100 μm. In order to improve the penetration of the etching solution, it is preferable that the width of the groove is wide, but from the viewpoint of effective utilization of the material of the substrate 11 and the semiconductor thin film 20, the width of the groove is preferably small.
The dimension Ra × Rb of the divided region R is about 100 μm × 8 mm. The size of the divided region can be appropriately selected by design, and may be, for example, a size of about 5 mm × 5 mm to 10 mm × 15 mm.
[0026]
Next, the semiconductor thin film 20 is peeled from the substrate 11 by removing the peeling layer 14 by etching.
This etching is performed by immersing the structure shown in FIGS. 2 and 3 in an etching solution tank (not shown) filled with an etching solution.
As an etchant, an etching solution having a high etching rate for the peeling layer 14 and a low etching rate for the semiconductor thin film 20 and the etching stopper layer 13, for example, 10% hydrofluoric acid (10% -HF) is used.
In other words, the etching stopper layer 13 is made of a material that is relatively difficult to be etched by the etching solution used for etching the peeling layer 14, that is, a material that has a lower etching rate with the etching solution than the peeling layer 14. Yes.
[0027]
The thin film 20 peeled off from the substrate 11 by etching is bonded to, for example, another semiconductor substrate (not shown) (for example, a Si substrate) to form a composite semiconductor device.
[0028]
When the thin film 20 is removed by performing the etching as described above, the stopper layer 13, the buffer layer 12, and the substrate 11 remain as shown in FIG.
In FIG. 4, reference numeral 23 indicates a trace where the divided semiconductor thin film 20 is removed, and reference numeral 22 indicates an area of the etching groove 21.
[0029]
Next, the stopper layer 13 is selectively removed by etching to the structure shown in FIG. 4 to expose the surface of the buffer layer 12.
For this etching, for example, a hydrochloric acid (HCl) -based etching solution is used.
Thereby, the stopper layer 13 can be selectively etched without eroding the buffer layer 12.
[0030]
In this way, the substrate 11 in which only the buffer layer 12 remains (that is, the combination of the substrate 11 and the buffer layer 12) is reused. That is, layers 13 to 19 are sequentially formed on the buffer layer 12 in the same manner as shown in FIG. 1, and then the same processing as described with reference to FIGS. 2 to 4 is repeated. The semiconductor thin film 20 can be obtained again.
[0031]
Hereinafter, the configuration and characteristics of each layer of the semiconductor thin film 20, the etching stopper layer 13, and the release layer 14, and particularly the etching characteristics and lattice matching thereof will be described in more detail.
[0032]
GaAs lower contact layer 15 constituting the semiconductor thin film 20, Al _s Ga _1-s As lower clad layer 16, Al _t Ga _1-t As active layer 17, Al _u Ga _1-u For example, the As cladding layer 18 and the GaAs upper contact layer 19 have the following characteristics. That is, the GaAs lower contact layer 15 is n-type, Al _S Ga _1-s As lower cladding layer 16 is n-type, Al _t Ga _1-t As active layer 17 is p-type, Al _u Ga _1-u As upper cladding layer 18 is p-type, GaAs upper contact layer 19 is p-type, Al _S Ga _1-s As lower clad layer 16, Al _t Ga _1-t As active layer 17, Al _u Ga _1-u The relation of the Al composition ratio of the As upper cladding layer 18 is determined as s> t, u> t, and a so-called double heterostructure is formed, thereby increasing the light emission efficiency. The light emission efficiency is increased because when a current is passed between the GaAs lower contact layer 15 and the GaAs upper contact layer 19 after the semiconductor thin film 20 is peeled off, carriers injected through the pn junction are heteroepitaxial. This is because it is confined by the energy barrier at the interface, and as a result, the carrier recombination probability increases.
[0033]
(Al _x Ga _1-x ) _y In _1-y The P etching stopper layer 13 prevents the etching groove 21 from reaching the GaAs substrate 11 when the etching groove 21 is formed in the semiconductor thin film 20. Configure stopper layer 13 (Al _x Ga _1-x ) _y In _1-y P and GaAs and AlGaAs constituting each layer of the semiconductor thin film 20 are greatly different in etching rates in etchants capable of etching GaAs and AlGaAs, for example, sulfuric acid-hydrogen peroxide, phosphoric acid hydrogen peroxide, and citric acid hydrogen peroxide. It is known. Therefore, when the etching groove 21 is provided in the semiconductor thin film 20, the etching structure 21 does not reach the GaAs substrate 11. In other words, when the etching groove 21 is provided in the semiconductor thin film 20, it is not necessary to strictly control the etching conditions in order to prevent the etching groove 21 from reaching the GaAs substrate 11. Since it is not necessary to strictly control the etching conditions, it is possible to set a longer etching time so that the AlAs release layer 14 is reliably exposed.
[0034]
When forming a semiconductor epitaxial layer, it is desirable to select a material so that the lattice constant of the crystal matches in order to prevent the occurrence of defects in the epitaxial layer. For example, on the GaAs substrate 11, (Al _x Ga _1-x ) _y In _1-y When the P etching stopper layer 13 is provided and the semiconductor thin film 20 for forming a semiconductor element is further provided thereon, (Al _x Ga _1-x ) _y In _1-y The lattice constant of the P etching stopper layer 13 is preferably equal to the lattice constant of GaAs constituting the substrate 11. (Al _x Ga _1-x ) _y In _1-y It is known that when P is 0.48 ≦ y ≦ 0.52, the lattice constant becomes equal to the lattice constant of GaAs. (In the ideal state, lattice matching with GaAs is achieved when y = 0.5, but methods for producing semiconductor epitaxial growth layers such as molecular beam epitaxy (MBE), metal organic vapor phase epitaxy, liquid layer epitaxy, etc. (There is a slight range in the composition ratio y (value of y actually obtained by analysis / measurement) for lattice matching depending on the epitaxial layer growth conditions by the above method.)
[0035]
More specifically, for example, x = 0, 0.48 ≦ y ≦ 0.52, that is, Ga _y In _1-y P (0.48 ≦ y ≦ 0.52) can be set. Therefore, from the viewpoint of preventing the occurrence of defects in the epitaxial layer, the composition of the etching stopper layer 103 is set to (Al _x Ga _1-x ) _y In _1-y In P, for example, x = 0, 0.48 ≦ y ≦ 0.52, and Ga _y In _1-y P (0.48 ≦ y ≦ 0.52) is desirable.
[0036]
As described above, all the etching grooves 21 on the substrate are (Al _x Ga _1-x ) _y In _1-y When the surface of the P-etching stopper layer 13 is stopped, the depth of the etching groove 21 is uniform and the degree of exposure of the AlAs peeling layer 14 is uniform over the entire area of the substrate. Etching of the AlAs peeling layer 14 for peeling 20 progresses uniformly over the entire substrate, and even if the substrate has a large area, the semiconductor thin film 20 can be peeled satisfactorily.
[0037]
As shown in FIG. 4, it remains after the semiconductor thin film 20 is peeled off (Al _x Ga _1-x ) _y In _1-y The P etching stopper layer 13 can be selectively removed by etching without etching the GaAs buffer layer 12 using, for example, a hydrochloric acid-based etchant. Selectively (Al _x Ga _1-x ) _y In _1-y Since the P etching stopper layer 13 can be removed by etching, the surface of the GaAs buffer layer 12 in a uniform state can be exposed over the entire substrate surface even if the substrate has a large area.
[0038]
Therefore, a good semiconductor epitaxial layer can be formed again on the GaAs buffer layer by, for example, the MOCVD method.
[0039]
As described above in detail, in the first embodiment, each layer constituting the semiconductor thin film 20 is provided between the AlAs layer peeling 14 for peeling the semiconductor thin film 20 from the GaAs substrate 11 and the GaAs substrate 11. Non-etching property to the etching solution to be etched (Al _x Ga _1-x ) _y In _1-y Since the laminated body provided with the P etching stopper layer 13 is formed and the semiconductor device is formed using this, the following effects can be obtained.
[0040]
First, even if an etching groove 21 for dividing the semiconductor thin film 20 into a plurality of regions is provided on the substrate 11, the etching groove 21 can be prevented from reaching the GaAs substrate 11, and the GaAs substrate 11 can be efficiently used. Can be reused.
[0041]
Further, the exposed state of the peeling layer 14 by the etching groove 21 can be made uniform over the entire surface of the substrate without strictly controlling the etching conditions, and even when the substrate has a large area, the semiconductor thin film can be peeled well over the entire surface of the substrate. Can be performed.
[0042]
Second embodiment
In the first embodiment, (Al _x Ga _1-x ) _y In _1-y Although the laminate in which the AlAs release layer 14 is formed on the P stopper layer 13 is used, the release layer 14 on the stopper layer 13 is omitted as shown in FIG. Alternatively, a laminate in which a release layer 24 is provided may be used. In other words, the stacking order of the stopper layer 13 and the release layers (14, 24) may be switched.
That is, as shown in FIG. 5, a semiconductor substrate, for example, an n-type GaAs substrate 11, a GaAs buffer layer 12 formed thereon, for example, an AlAs release layer 24 formed thereon, and a Formed for example (Al _x Ga _1-x ) _y In _1-y P etching stopper layer 13, an n-type GaAs lower contact layer 15 formed thereon, and an n-type Al layer formed thereon, for example. _s Ga _1-s As lower clad layer 16 and, for example, p-type Al formed thereon _t Ga _1-t As active layer 17 and, for example, p-type Al formed thereon _u Ga _1-u A laminated body having the As upper cladding layer 18 and, for example, a p-type GaAs upper contact layer 19 formed thereon may be prepared.
[0043]
When the stopper layer 13 and the release layers (14, 24) are exchanged as described above, the etching is performed when the etching proceeds to the upper surface of the stopper layer 13 in forming the etching groove 21 as shown in FIG. Terminate. Therefore, the groove 21 does not penetrate the release layer 24, and the release layer 24 is not exposed except in the peripheral portion of the substrate 11.
[0044]
As described in the first embodiment, by using an etching solution for forming the groove 21 that has a high etching rate for each layer constituting the semiconductor thin film 20 and a low etching rate for the stopper layer 13. Etching can be stopped at the surface of the stopper layer 13 without strictly controlling etching conditions such as etching time.
[0045]
After the formation of the groove 21, the AlAs peeling layer 24 is etched to peel off the semiconductor thin film 20 and the stopper layer 13 as shown in FIG. In this etching, the etching solution permeates along the peeling layer 24 from the peripheral edge of the substrate 11 toward the central portion. When this peeling is performed, the buffer layer 12 and the GaAs substrate 11 remain as shown in FIG.
[0046]
In the etching process of the AlAs release layer 24, the etching rate of AlAs is high and the etching rate of GaAs constituting the substrate 11 and the buffer layer 12 is low (for example, the etching rate ratio is about 10). ⁷ Since the etching solution (for example, hydrofluoric acid) is used, the surface of the GaAs buffer layer 12 on the GaAs substrate 11 is hardly affected by etching and can be easily reused. That is, the surface of the GaAs substrate 11 and the surface of the GaAs buffer layer 12 thereon are sufficiently flat and in good condition so as not to hinder immediate epitaxial growth again.
[0047]
The combination of the semiconductor thin film 20 and the stopper layer 13 separated from the substrate 11 is selectively dissolved by, for example, immersing in a hydrochloric acid-based etching solution, whereby the entire stopper layer 13 is divided by the etching groove 21. The individual semiconductor thin films 20 are separated from each other, and an independent semiconductor thin film can be obtained as shown in FIG.
[0048]
In the first and second embodiments, the GaAs buffer layer 12 is provided on the GaAs substrate 11. The buffer layer 12 is provided in order to improve the epitaxial layer formed thereon. However, the buffer layer 12 is omitted, and the buffer layer 12 is directly formed on the substrate 11 (Al _x Ga _1-x ) _y In _1-y The P stopper layer 13 or the release layer 14 may be formed.
[0049]
In the first and second embodiments described above, the substrate 11 in which the buffer layer 12 remains is reused, but the buffer layer 12 is removed by a method such as chemical mechanical polishing, Only the substrate 11 may be reused. In this case, the buffer layer 12 is newly formed on the substrate 11, and the layers 13 to 19 are formed thereon.
[0050]
Furthermore, the substrate 11 is not limited to a GaAs substrate, and (Al _x Ga _1-x ) _y In _1-y A substrate made of another material may be used as long as it can be selectively etched with the P stopper layer 13.
[0051]
In the first embodiment, the etching stopper layer 13 is made of a material that can be lattice-matched in the epitaxial growth, but is lattice-matched with the semiconductor thin film 20 depending on the selection of the substrate material. It has a composition that does not match (Al _x Ga _1-x ) _y In _1-y A P stopper layer 13 may be used. Also, (Al _x Ga _1-x ) _y In _1-y A buffer layer can be provided on the P stopper layer 13 to relieve the lattice constant mismatch with the semiconductor thin film 20.
[0052]
Third embodiment
In the first embodiment, the laminated body shown in FIG. 1 is first formed. In the third embodiment, the laminated body shown in FIG. 9 is first formed.
The stacked body includes a semiconductor substrate, for example, an n-type GaAs substrate 11, a GaAs buffer layer 12 formed thereon, an AlAs release layer 31, for example, formed thereon, and a layer formed thereon, for example, (Al _x Ga _1-x ) _y In _1-y P etching stopper layer 13, an AlAs release layer 14 formed thereon, an n-type GaAs lower contact layer 15 formed thereon, and an n-type Al layer formed thereon, for example. _s Ga _1-s As lower clad layer 16 and, for example, p-type Al formed thereon _t Ga _1-t As active layer 17 and, for example, p-type Al formed thereon _u Ga _1-u It has an As upper cladding layer 18 and, for example, a p-type GaAs upper contact layer 19 formed thereon.
The difference between FIG. 9 and FIG. 9 is that a second release layer 31 is provided between the stopper layer 13 and the buffer layer 12. Note that the release layer 14 is referred to as a first release layer for distinction from the second release layer 31.
[0053]
The second release layer 31 is formed of, for example, an AlAs layer, similar to the release layer 31 of the second embodiment.
[0054]
9 includes a buffer layer 12, a second release layer 31, an etching stopper layer 13, a first release layer 14, a lower contact layer 15, a lower cladding layer 16, and an active layer on a substrate 11. 17, the upper cladding layer 18, and the upper contact layer 19 are obtained by epitaxial growth in this order.
[0055]
After the stacked body of FIG. 9 is formed, an etching groove 21 is formed as described in the first embodiment (FIG. 10). The etching groove 21 has a depth that reaches the surface of the stopper layer 13. By doing so, the first release layer 14 is completely exposed in the thickness direction.
[0056]
As an etching solution for forming the etching groove 21, an etching solution having a low etching rate of the etching stopper layer 13 and a high etching rate of each layer constituting the thin film 20, for example, as described in the first embodiment. Similarly, sulfuric acid perwater, phosphoric acid perwater, and citric acid perwater can be used.
[0057]
As described in connection with the first embodiment, the etching time for forming the etching groove 21 is, for example, an etching time so that the depth of the etching groove 21 does not become insufficient over the entire surface of the large area substrate (wafer). Even long enough, (Al _x Ga _1-x ) _y In _1-y Etching can be stopped at the surface of the P etching stopper layer 13.
[0058]
Next, as shown in FIG. 11, the semiconductor thin film 20 is peeled from the GaAs substrate 11. This is done by etching the first release layer 14 with hydrofluoric acid (HF) as described with respect to the first embodiment.
[0059]
As shown in FIG. 11, since the first release layer 14 under the semiconductor thin film 20 subdivided by the etching groove 21 is also subdivided, the etching solution is transferred from the etching groove 21 to the first release layer 14 at high speed. To penetrate.
[0060]
On the other hand, the second release layer 31 is formed over the entire surface of the substrate (wafer) (Al _x Ga _1-x ) _y In _1-y Since it is sandwiched between the P stopper layer 13 and the GaAs substrate 11, it is shielded from the etching solution in the vertical direction, and etching proceeds along the peeling layer 31 from the periphery of the substrate 11 toward the center. Therefore, as shown in FIG. 11, at the time when the etching removal of the first release layer 14 is finished and the semiconductor thin film 20 is separated from the GaAs substrate 11, the second release layer 31 is only in the vicinity of the periphery. Has been removed and most remains.
[0061]
Here, the layer thickness of the second release layer is set to be equal to or less than the layer thickness of the first release layer so that the penetration of the etchant into the second release layer is delayed, and the etching of the first release layer is performed. In this case, it is possible to ensure that the second release layer remains. Further, the second release layer is made of a material equivalent to the material of the first release layer, or the etching rate of the second release layer is lower than the etching rate of the first release layer, It is possible to ensure that the second release layer remains when the first release layer is etched. In this case, for example, the material of the first release layer is Al. _s Ga _1-s As (1 ≧ s> 0), the material of the second release layer is Al _t Ga _1-t As (1 ≧ t> 0), s ≧ t.
[0062]
After peeling the semiconductor thin film 20, (Al _x Ga _1-x ) _y In _1-y The P etching stopper layer 13 is removed by etching with, for example, a hydrochloric acid-based etchant to expose the second release layer 31 (FIG. 12).
[0063]
As described above, after the second release layer 31 is exposed, the second release layer 31 is removed by etching with, for example, 10% hydrofluoric acid (FIG. 13).
[0064]
In the etching of the second peeling layer 31 with hydrofluoric acid, the etching rate of GaAs constituting the buffer layer 12 with respect to hydrofluoric acid is extremely slow compared with the etching rate of AlAs constituting the peeling layer 31 with respect to hydrofluoric acid (about 1). / 10 ⁷ Therefore, the GaAs buffer layer 12 is hardly eroded, and the surface of the GaAs buffer layer 12 after the AlAs release layer 31 is removed by etching is very smooth.
[0065]
As described above, the structure shown in FIG. 11 is etched with a hydrochloric acid-based etchant to remove the stopper layer 13, and then the hydrofluoric acid is used as an etchant to remove the peeling layer 31 by etching. In the structure shown in FIG. 11, the second release layer 31 and the stopper layer 13 thereon may be removed simultaneously by removing the second release layer 31 by etching using hydrofluoric acid ( FIG. 14). In this case, the etching solution permeates along the second release layer 31 from the peripheral edge of the substrate 11 toward the center.
[0066]
Further, the removal of the first peeling layer 14 and the removal of the second peeling layer 31 can be performed using the same etching solution (hydrofluoric acid), and these are performed simultaneously (as one step). Can do. In this case, by appropriately selecting the composition, thickness, and the like of the first release layer 14 and the second release layer 31, the removal of the first release layer 14 and the removal of the second release layer 31 are substantially simultaneously performed. It can also be completed. This will be described in detail later.
[0067]
According to the third embodiment, since the second release layer 31 is interposed between the etching stopper layer 13 and the buffer layer 12, the buffer layer 12 is removed when the second release layer 31 is removed by etching. However, the buffer layer 12 having a sufficiently flat surface can be obtained after the peeling layer 31 (and the stopper layer 13) is removed. Therefore, when the substrate 11 having the buffer layer 12 is reused, a good epitaxial layer can be grown on the buffer layer 12.
[0068]
In the third embodiment, the second release layer 31 may be provided directly on the substrate 11 without providing the GaAs buffer layer 12. In that case, since the surface of the GaAs substrate 11 becomes extremely flat when the release layer 31 is peeled off, a good epitaxial layer can be grown on the surface of the GaAs substrate 11 when the substrate is reused. it can.
[0069]
Fourth embodiment
In the third embodiment, the laminated body shown in FIG. 9 is first formed, but instead, the laminated body shown in FIG. 15 may be formed.
The stacked body includes a semiconductor substrate, for example, an n-type GaAs substrate 11, a GaAs buffer layer 12 formed thereon, an AlAs release layer 31, for example, formed thereon, and a layer formed thereon, for example, GaAs buffer layer 33 and, for example, (Al _x Ga _1-x ) _y In _1-y A P etching stopper layer 13, a GaAs buffer layer 34 formed thereon, an AlAs release layer 14 formed thereon, and an n-type GaAs lower contact layer 15 formed thereon, for example; For example, n-type Al formed thereon _s Ga _1-s As lower clad layer 16 and, for example, p-type Al formed thereon _t Ga _1-t As active layer 17 and, for example, p-type Al formed thereon _u Ga _1-u It has an As upper cladding layer 18 and, for example, a p-type GaAs upper contact layer 19 formed thereon.
[0070]
15 differs from FIG. 15 in that a second buffer layer 33 is provided between the stopper layer 13 and the lower release layer 31, and a third buffer is provided between the stopper layer 13 and the upper release layer 14. The layer 34 is provided. In order to distinguish between the second and third buffer layers 33 and 34, the buffer layer 12 is referred to as a first buffer layer.
[0071]
Both the second buffer layer 33 and the third buffer layer 34 are made of GaAs.
[0072]
15 includes a buffer layer 12, a second release layer 31, a buffer layer 33, a stopper layer 13, a buffer layer 34, a first release layer 14, a contact layer 15, a cladding layer 16, and a substrate 11. The active layer 17, the cladding layer 18, and the contact layer 19 are obtained by epitaxial growth in this order.
[0073]
After the stacked body shown in FIG. 15 is formed, the etching groove 21 is formed and the first release layer 14 is exposed in the same manner as described in the first embodiment (FIG. 16). The etching groove 21 has a depth that exposes at least the AlAs layer 14. In the drawing shown here, for example, the depth reaches the surface of the stopper layer 13.
[0074]
Next, the first peeling layer 14 is removed by etching with hydrofluoric acid, and the semiconductor thin film 20 is peeled off (FIG. 17).
[0075]
Next, the second peeling layer 31 is removed by etching with hydrofluoric acid to expose the GaAs buffer layer 12 (FIG. 18). When the peeling layer 31 is removed by etching with hydrofluoric acid, the etching solution (hydrofluoric acid) permeates along the second peeling layer 31 from the periphery of the substrate 11 toward the center.
In the fourth embodiment, the same effect as in the third embodiment can be obtained, and the same modification can be made.
[0076]
In the fourth embodiment, since the stopper layer and the first peeling layer are provided after the second buffer layer or the third buffer layer is provided, the first peeling layer and the semiconductor thin film layer are provided. Quality can be improved and the state of the peeling interface of the semiconductor thin film can be improved. Further, a higher quality semiconductor element can be obtained.
[0077]
Fifth embodiment
In the first embodiment, the stacked body shown in FIG. 1 is formed first, but the stacked body shown in FIG. 19 may be formed instead.
The stacked body is formed on a semiconductor substrate, for example, a silicon (Si) substrate 41, a GaAs buffer layer 12 formed thereon, for example, an AlAs release layer 14 formed thereon, and the like. For example, n-type GaAs lower contact layer 15 and, for example, n-type Al formed thereon _s Ga _1-s As lower clad layer 16 and, for example, p-type Al formed thereon _t Ga _1-t As active layer 17 and, for example, p-type Al formed thereon _u Ga _1-u It has an As upper cladding layer 18 and, for example, a p-type GaAs upper contact layer 19 formed thereon.
The difference between FIG. 19 and FIG. 19 is that a silicon (Si) substrate 41 is used instead of the GaAs substrate 11 and that the stopper layer 13 is not provided.
[0078]
19 is obtained by epitaxially growing a buffer layer 12, a release layer 14, a contact layer 15, a cladding layer 16, an active layer 17, a cladding layer 18, and a contact layer 19 in this order on a substrate 41.
[0079]
When a compound semiconductor semiconductor thin film is formed on the Si substrate 41 as in the present embodiment, the buffer layer 12 needs to be formed relatively thick in order to reduce the defect density of the semiconductor thin film.
[0080]
After the stacked body of FIG. 19 is formed, an etching groove 21 is formed to expose the release layer 14 in the same manner as described in the first embodiment (FIG. 20).
The etching groove 21 extends to the middle of the GaAs buffer layer 12.
As an etchant, a solution capable of etching the semiconductor thin film 20, the AlAs layer 14, and the buffer layer 12, for example, phosphoric acid / hydrogen peroxide (phosphoric acid + hydrogen peroxide water + pure water) is used.
[0081]
Thereafter, the peeling layer 14 is removed by etching with, for example, 10% hydrofluoric acid, and the semiconductor thin film 20 is separated from the substrate 41 (FIG. 21).
[0082]
Thereafter, the buffer layer 12 is selectively removed by etching using an etchant that is not etched, for example, phosphoric acid / hydrogen peroxide.
As a result, a Si substrate 41 having a flat surface is obtained (FIG. 21).
The Si substrate 41 has a flat surface and can be reused.
[0083]
In the above example, as shown in FIG. 20, the etching groove 21 is halfway through the buffer layer 12, but in this embodiment, the buffer layer 12 is relatively thick, so that the etching time and the like are accurately controlled. Even without this, the progress of etching can be stopped in the middle of the buffer layer 12.
[0084]
In the fifth embodiment, the Si substrate 41 is used, and the etching groove 21 erodes the Si substrate 41 even if the etching groove 21 is provided in the semiconductor thin film on the substrate 41 and subdivided into individual semiconductor thin film regions. The flat Si substrate 41 can be obtained after the semiconductor thin film 20 is peeled off.
[0085]
Note that some of the modifications described with respect to the first and second embodiments (FIGS. 1 to 8) are also applicable to other embodiments.
[0086]
For example, as described in the first and second embodiments (FIGS. 1 to 8), in the third and fourth embodiments (FIGS. 9 to 18), the substrate 11 is made of a GaAs substrate. Without limitation, (Al _x Ga _1-x ) _y In _1-y A substrate made of another material may be used as long as it can be selectively etched with the P stopper layer 13.
[0087]
Further, as described in the first, second and third embodiments (FIGS. 1 to 14), the fourth and fifth embodiments (embodiments of FIGS. 5 to 21) also The buffer layer 12 may be omitted.
In the fourth embodiment, the second buffer layer 33 may be omitted.
[0088]
In each of the above embodiments, the release layer 14 is made of AlAs. However, the material of the release layer 14 is a material that lattice-matches with the layers constituting the semiconductor thin film 20. Any other material may be used as long as it is a material that can be etched at high speed with an etchant having a low etching rate with respect to the layers constituting the semiconductor thin film 20.
For example, instead of AlAs, Al _p Ga _1-p As (1>p> 0) can be used
AlAs is assumed to be Al if p can take a value in the range of 1 ≧ p> 0. _p Ga _1-p It can be considered that As (1 ≧ p> 0) and p = 1.
However, for selective etching, it is necessary to make the Al composition ratio higher than that of AlGaAs constituting the lower cladding layer 16, the active layer 17, and the upper cladding layer 18 of the semiconductor thin film 20. That is, the material of the lower cladding layer 16, the active layer 17, and the upper cladding layer 18 of the semiconductor thin film 20 is Al. _z Ga _1-z When represented by As (z = s for the lower cladding layer 16, z = t for the active layer 17, and z = u for the upper cladding layer 18),
z <p
It is necessary to satisfy.
[0089]
Furthermore, in the embodiment of FIGS. 9 to 14 and the embodiment of FIGS. 15 to 18,
The composition of the second release layer is Al _q Ga _1-q When expressed as As (1>q> 0),
z <q
It is necessary to satisfy. In order to complete most of the etching of the second peeling layer during the etching of the first peeling layer, it is desirable to satisfy at least the following conditions. That is, it is desirable that p <q.
Furthermore, it is desirable that the thickness of the second release layer 31 is larger than the thickness of the first release layer 14.
Furthermore, it is desirable that the etching rate of the second peeling layer 31 is higher than the etching rate of the first peeling layer 14 with respect to the second etching solution (hydrofluoric acid).
Further, the etching completion time of the first peeling layer 14 and the etching completion time of the second peeling layer 31 are substantially matched, and the etching of the first peeling layer and the second peeling layer is completed by one etching. Can be made.
[0090]
The above point will be described in more detail.
When the peeling layers 14 and 31 are made of AlGaAs, the etching rate by hydrofluoric acid used as the second etching liquid increases as the Al composition ratio increases. Therefore, the Al composition ratio p of the first release layer 14 and the Al composition ratio q of the second release layer 31 are
p <q
If the condition is satisfied, the etching rate of the second release layer 31 can be made higher than that of the first release layer 14.
[0091]
In addition, the first release layer 14 is located under the semiconductor thin film 20 separated into individual islands by the etching grooves 21 and is exposed to a large number of grooves 21, whereas the second release layer 31 is It is covered with the etching stopper layer 13 and is only exposed at the edge of the substrate 11. Therefore, when the first and second release layers 14 and 31 are etched in this state, the length of the first and second release layers 14 and 31 to which hydrofluoric acid must penetrate (in the etching progress direction). The distance along L1 and L2 is
L2> L1
Have the relationship. Here, when the etching rates of the first and second release layers 14 and 31 are S1 and S2, the times T1 and T2 required for etching the first and second release layers 14 and 31 are respectively
T1 = L1 / S1
T2 = L2 / S2
It becomes. As described above, if L2> L1, a condition that satisfies S2> S1, that is, a condition in which the etching rate of the second release layer 31 is higher than the first release layer 14 is selected. A result that is approximately equal to T2 can be obtained. If T1 = T2, it is possible to complete not only the removal of the semiconductor thin film 20 but also the removal of the second peeling layer almost simultaneously in the step of peeling the semiconductor thin film 20 with the second etching solution. In other words, the peeling of the semiconductor thin film 20 by the etching removal of the first peeling layer 14 and the removal of the second peeling layer 31 can be performed at the same time and completed almost simultaneously.
[0092]
In addition, if the second release layer 31 is thicker than the first release layer 14, the material of the second release layer 31 is etched when the materials of the first release layer 14 and the second release layer 31 are the same. The speed S2 is higher than the etching speed of the material of the first release layer. That is, S2> S1. Therefore, the Al composition ratio of AlGaAs explained above
p <q
In the same manner as described above, the etching time T1 = L1 / S1 of the first peeling layer and the etching time T2 = L2 / S2 of the second peeling layer can be made substantially equal. As a result, in the step of peeling the semiconductor thin film 20 with the second etching solution, it is possible to complete not only the peeling of the semiconductor thin film 20 but also the removal of the second peeling layer almost simultaneously. In other words, the peeling of the semiconductor thin film 20 and the removal of the second peeling layer 31 by etching removal of the first peeling layer 14 can be performed at the same time and completed almost simultaneously.
[0093]
As described above, instead of increasing the Al composition ratio q of the second release layer 31 to be greater than the Al composition ratio p of the first release layer 14, p and q may not be equal to each other. . For example, it is good also as p> q.
Further, as described above, instead of making the second release layer 31 thicker than the thickness of the first release layer 14, the thickness of the first release layer 14 and the thickness of the second release layer 31 are equal to each other. It may not be equal. For example, the thickness of the first release layer 14 may be greater than the thickness of the second release layer 31. In such a case (when p> q or the thickness of the first release layer 14> the thickness of the second release layer 31), the second release is performed when the first release layer 14 is etched. The etching of the release layer 31 hardly progressed, and the etching stopper layer 13 was etched on the entire surface (the etching stopper layer 13 exposed on the entire surface of the entire wafer was etched simultaneously), and then the second release layer 31 was etched on the entire surface (entire surface of the wafer The second release layer 31 exposed over the entire surface can be etched simultaneously).
[0094]
In each of the above embodiments, the etching stopper layer 13 is made of Al. _x Ga _1-x ) _y In _1-y The one formed of P was used.
As described in connection with the first embodiment (FIGS. 1 to 4), in the second to fourth embodiments (FIGS. 5 to 18), when the substrate 11 is GaAs, From the viewpoint of lattice matching with GaAs, 0.48 ≦ y ≦ 0.52 is desirable. More specifically, for example, Ga = 0, 0.48 ≦ y ≦ 0.52. _y In _1-y It is desirable that P (0.48 ≦ y ≦ 0.52).
However, the material of the etching stopper layer 13 may be another material as long as it can be selectively etched with the layers constituting the semiconductor thin film 20. For example, InP, InGaAs, InAlAs, InGaAsP, or the like can be used.
[0095]
Furthermore, in the first and third embodiments, by adjusting the etching time, the etching is finished in the middle of the AlAs release layer 14, that is, the AlAs release layer 14 is only partly in the thickness direction. It can also be exposed.
[0096]
In each of the above embodiments, the semiconductor thin film 20 is used as an LED array. However, the present invention is not limited to this, and the semiconductor thin film is used for forming various elements and circuits other than LEDs. It is also applicable to cases.
[0097]
【The invention's effect】
As described above, according to the present invention, the substrate can be efficiently reused.
[Brief description of the drawings]
FIG. 1 is a schematic partial sectional view showing a state in which a laminated structure of semiconductor thin films is formed in a manufacturing method according to a first embodiment of the present invention.
FIG. 2 is a schematic partial cross-sectional view showing a state where grooves are formed in the manufacturing method according to the first embodiment of the present invention.
FIG. 3 is a schematic partial perspective view showing a state in which grooves are formed in the manufacturing method according to the first embodiment of the present invention.
FIG. 4 is a schematic partial perspective view showing a state in which the semiconductor thin film is removed in the manufacturing method according to the first embodiment of the present invention.
FIG. 5 is a schematic partial sectional view showing a state in which a laminated structure of semiconductor thin films is formed in the manufacturing method according to the second embodiment of the present invention.
FIG. 6 is a schematic partial cross-sectional view showing a state in which grooves are formed in one step of the manufacturing method according to the second embodiment of the present invention.
FIG. 7 is a schematic partial cross-sectional view showing a state where a semiconductor thin film and an etching stopper layer are removed in the manufacturing method according to the second embodiment of the present invention.
FIG. 8 is a schematic partial cross-sectional view showing a state where a semiconductor thin film is separated from an etching stopper layer in the manufacturing method according to the second embodiment of the present invention.
FIG. 9 is a schematic partial sectional view showing a state in which a laminated structure of semiconductor thin films is formed in the manufacturing method according to the third embodiment of the present invention.
FIG. 10 is a schematic partial cross-sectional view showing a state where grooves are formed in the manufacturing method according to the third embodiment of the present invention.
FIG. 11 is a schematic partial cross-sectional view showing a state where a semiconductor thin film is peeled off in the manufacturing method according to the third embodiment of the present invention.
FIG. 12 is a schematic partial cross-sectional view showing a state where an etching stopper layer is removed in the manufacturing method according to the third embodiment of the present invention.
FIG. 13 is a schematic partial cross-sectional view showing a state where a release layer is removed in the manufacturing method of the third embodiment of the present invention.
FIG. 14 is a schematic partial cross-sectional view showing a state in which an etching stopper layer and a release layer have been removed in a manufacturing method according to a modification of the third embodiment of the present invention.
FIG. 15 is a schematic partial sectional view showing a state in which a laminated structure of semiconductor thin films is formed in the manufacturing method according to the fourth embodiment of the present invention.
FIG. 16 is a schematic partial sectional view showing a state in which grooves are formed in the manufacturing method according to the fourth embodiment of the present invention.
FIG. 17 is a schematic partial cross-sectional view showing a state where a semiconductor thin film is peeled off in the manufacturing method according to the fourth embodiment of the present invention.
FIG. 18 is a schematic partial cross-sectional view showing a state where the second and third buffer layers and the etching stopper layer are removed in the manufacturing method according to the fourth embodiment of the present invention.
FIG. 19 is a schematic partial sectional view showing a state in which a laminated structure of semiconductor thin films is formed in the manufacturing method according to the fifth embodiment of the present invention.
FIG. 20 is a schematic partial cross-sectional view showing a state where grooves are formed in the manufacturing method according to the fifth embodiment of the present invention.
FIG. 21 is a schematic partial cross-sectional view showing a state where a semiconductor thin film is peeled off in the manufacturing method according to the fifth embodiment of the present invention.
FIG. 22 is a schematic partial cross-sectional view showing the state of the semiconductor device in one step of the conventional method of manufacturing a semiconductor device.
FIG. 23 shows Al in a conventional method for manufacturing a semiconductor device. _0.7 Ga _0.3 It is a general | schematic fragmentary sectional view which shows the state which etched the As layer.
FIG. 24 is a schematic plan view showing a state in which a semiconductor thin film is divided by grooves in a conventional method for manufacturing a semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 Substrate, 12 Buffer layer, 13 Etching stopper layer, 14 Release layer, 15 Lower contact layer, 16 Lower cladding layer, 17 Active layer, 18 Upper cladding layer, 19 Upper contact layer, 20 Semiconductor thin film, 21 Groove, 24 Release layer, 31 release layer, 33 buffer layer, 34 buffer layer, 41 substrate.

Claims (39)

A substrate,
An etching stopper layer formed on the substrate;
A first release layer formed on the etching stopper layer;
A semiconductor thin film formed on the first release layer, and the etching stopper layer is less likely to be etched by the first etchant than the semiconductor thin film,
The laminated body, wherein the semiconductor thin film is less likely to be etched by the second etchant than the first release layer. A substrate,
A first release layer formed on the substrate;
An etching stopper layer formed on the first release layer;
A semiconductor thin film formed on the etching stopper layer,
The etching stopper layer is relatively difficult to be etched by the first etching solution compared to the semiconductor thin film,
The laminated body, wherein the semiconductor thin film is less likely to be etched by the second etchant than the first release layer. 3. The laminate according to claim 1, wherein the substrate is less likely to be etched by a third etchant than the etching stopper layer. 4. The substrate is GaAs;
The first release layer is Al _p Ga _1-p As (1 ≧ p ≧ 0);
The laminate according to claim ₁ , wherein the stopper layer is an (Al _x Ga _1-x ) _y In _1-y P layer (1 ≧ x ≧ 0, 1 ≧ y ≧ 0). Wherein each layer of the semiconductor thin film _laminate of claim 4, characterized in that the _{Al z Ga 1-z As (} 1 ≧ z ≧ 0). The laminate according to claim 5, wherein z <p with respect to an Al composition ratio z of each layer of the semiconductor thin film and an Al composition ratio p of the first release layer. The laminate according to claim 5, wherein the first release layer is AlAs. 5. The laminate according to claim 4, wherein x = 0 and 0.48 ≦ y ≦ 0.52 in the composition of the stopper layer (Al _x Ga _1-x ) _y In _1-y P. 6. A second release layer formed on the substrate;
The stopper layer is formed on the second release layer,
2. The laminate according to claim 1, wherein the second release layer is more easily etched by the first etchant than the substrate and is easily etched by the second etchant. . The substrate is a GaAs substrate;
The first release layer is Al _p Ga _1-p As (1 ≧ p ≧ 0),
The stopper layer is an (Al _x Ga _1-x ) _y In _1-y P layer (1 ≧ x ≧ 0, 1 ≧ y ≧ 0),
The laminate according to claim 9, wherein the second release layer in the previous period is Al _q Ga _1-q As (1 ≧ q ≧ 0). Wherein each layer of the semiconductor thin film _laminate of claim 10, characterized in that the _{Al z Ga 1-z As (} 1 ≧ z ≧ 0). Regarding the Al composition ratio z of each layer of the semiconductor thin film, the Al composition ratio p of the first release layer, and the Al composition ratio q of the second release layer,
The laminate according to claim 11, wherein z <p and z <q. The laminate according to claim 10, wherein an Al composition ratio p of the first release layer and an Al composition ratio q of the second release layer are not equal to each other. The laminate according to claim 10, wherein the thickness of the first release layer and the thickness of the second release layer are not equal to each other. For the first release layer and the second release layer, the etching rate of the second release layer is higher than the etching rate of the first release layer with respect to the second etching solution. The laminate according to claim 10. The laminate according to claim 15, wherein the Al composition ratio p of the first release layer and the Al composition ratio q of the second release layer satisfy p <q. The laminate according to claim 10, wherein the first release layer and the second release layer are AlAs. The layered product according to claim 15 or 17, wherein the layer thickness of said 2nd exfoliation layer is larger than the layer thickness of said 1st exfoliation layer. 11. The stacked body according to claim 10, wherein x = 0 and 0.48 ≦ y ≦ 0.52 in the composition of the stopper layer (Al _x Ga _1-x ) _y In _1-y P. 11. A first buffer layer formed on the substrate;
The second release layer is formed on the first buffer layer,
A second buffer layer formed on the second release layer;
The stopper layer is formed on the second buffer layer;
A third buffer layer formed on the stopper layer;
The laminate according to claim 10, wherein the first release layer is formed on the third buffer layer. A substrate,
A release layer formed on the substrate;
A semiconductor thin film formed on the release layer;
The substrate is less likely to be etched by the first etchant than the semiconductor thin film and the release layer,
The laminate, wherein the substrate is less likely to be etched by the second etchant than the release layer. The laminate according to claim 21, wherein the substrate is a Si substrate, and the semiconductor thin film is a GaAs-based semiconductor thin film. The material for each layer of the semiconductor thin film is represented by Al _z Ga _1-z As (z ≧ 0). The laminate according to claim 22, wherein the material of the release layer is represented by Al _p Ga _1-p As (1 ≧ p> 0). The laminate according to claim 24, wherein z <p with respect to an Al composition ratio z of each layer of the semiconductor thin film and an Al composition ratio p of the second epitaxial layer. 25. The laminate according to claim 24, wherein a material of the release layer is represented by AlAs. The laminate according to claim 22, wherein the first substrate and the release layer are in contact with each other. The semiconductor thin film includes a lower contact layer, a lower clad layer located thereon, an active layer located thereon, an upper clad layer located thereon, and an upper contact layer located thereon The laminate according to any one of claims 1 to 27, comprising: The semiconductor thin film is formed by epitaxially growing the lower contact layer, the lower cladding layer, the active layer, the upper cladding layer, and the upper contact layer in order. The laminate according to 28. The laminate according to any one of claims 1 and 3 to 8, wherein the substrate is harder to be etched by a third etchant than the etching stopper layer. The laminate according to any one of claims 2 to 8, wherein the substrate is harder to be etched by a third etchant than the etching stopper layer. Preparing the laminate according to any one of claims 1 and 3 to 8,
Forming a semiconductor element on the semiconductor thin film;
Forming a groove in the semiconductor thin film using the first etching solution;
And a step of removing the first release layer using the second etchant. Preparing the laminate according to any one of claims 2 to 8,
Forming a semiconductor element on the semiconductor thin film;
Forming a groove in the semiconductor thin film using the first etching solution;
Separating the semiconductor thin film from the substrate by removing the first release layer using the second etchant. Preparing a laminate according to claim 30;
Forming a semiconductor element on the semiconductor thin film;
Forming a groove in the semiconductor thin film using the first etching solution;
Removing the first release layer using the second etchant;
And a step of removing the stopper layer using a third etching solution. Preparing a laminate according to claim 31;
Forming a semiconductor element on the semiconductor thin film;
Forming a groove in the semiconductor thin film using the first etching solution;
Removing the first release layer using the second etchant;
And a step of removing the stopper layer using a third etching solution. Preparing a laminate according to any one of claims 9 to 19,
Forming a semiconductor element on the semiconductor thin film;
Forming a groove in the semiconductor thin film using the first etching solution;
Removing the first release layer using the second etchant;
And a step of removing the second release layer after the step of removing the first release layer. 37. The method according to claim 36, further comprising a step of removing the stopper layer after the step of removing the first release layer and before the step of removing the second release layer. The manufacturing method of the semiconductor device of description. Preparing a laminate according to claim 20;
Forming a semiconductor element on the semiconductor thin film;
Forming a groove in the semiconductor thin film using the first etching solution;
Removing the first release layer using the second etchant;
A step of separating the third buffer layer, the stopper layer, and the second buffer layer from the substrate by removing the second release layer after the step of removing the first release layer. A method for manufacturing a semiconductor device. Preparing a laminate according to any one of claims 21 to 27;
Forming a semiconductor element on the semiconductor thin film;
Forming a groove in the semiconductor thin film using the first etching solution;
Separating the semiconductor thin film from the substrate by removing the release layer using the second etchant;
A method for manufacturing a semiconductor device comprising:

Images