JP2005019500A - Laminated capacitor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate the parasitism of the stray electrostatic capacitance of a laminated capacitor. <P>SOLUTION: In the laminated capacitor, five layers of internal electrodes are successively disposed from the top in an elemental dielectric body 12 and an internal electrode 21 is disposed in the outermost layer. Terminal electrodes 31-38 for signals are disposed on the outside of the elemental dielectric body 12 in a state where the electrodes 31-38 respectively cover the side faces 12C of the body 12. In addition, grounding terminal electrodes 39 and 40 connected to the internal electrode 21 are also disposed on the outside of the elemental dielectric body 12 to cover the side faces 12B of the body 12. The terminal electrodes 31-38 for signals and grounding terminal electrodes 39 and 40 are respectively protruded to the top and bottom surfaces 12D of the elemental dielectric body 12. The lengths L2 of the sagging sections 42 of the grounding terminal electrodes 39 and 40 protruded to the top and bottom surfaces 12D of the elemental dielectric body 12 are made longer than those L1 of the sagging sections 41 of the terminal electrodes 31-38 for signals also protruded to the surfaces 12D. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multilayer capacitor in which floating capacitance is reduced by eliminating overlap between a terminal electrode and an internal conductor, and particularly suitable for a multilayer through-type capacitor array in which a plurality of capacitors are housed in a ceramic sintered body. It is a thing.
[0002]
[Prior art]
Chip-type multilayer capacitors are often used in electronic devices, but in particular, small electronic devices such as personal computers, word processors, mobile phones, cordless phones, and pagers have a small mounting space. In particular, a multilayer feedthrough capacitor array or a multilayer capacitor array having a plurality of built-in capacitors is often used. Conventional multilayer feedthrough capacitor arrays and multilayer capacitor arrays are disclosed in the following patent documents, for example.
[0003]
For example, in a multilayer through-type capacitor array, a ceramic sintered body 112 serving as a base body is formed by sequentially laminating a plurality of green sheets while sandwiching the internal electrodes 121 to 125 shown in FIG. As shown by 8, it is formed so as to exhibit a substantially rectangular parallelepiped.
[0004]
A pair of ground terminal electrodes 139 and 140 respectively connected to the pair of internal electrodes 122 and 124 for the ground line among the five layers of internal electrodes 121 to 125 are ceramic sintered bodies as shown in FIG. It is provided in the part located in the both sides of the outer surface of 112 facing each other. Further, as shown in FIG. 9, this multilayer through-type capacitor array has a pair of signal terminal electrodes 131 to 138 corresponding to the number of capacitors (four in this example) housed in the ceramic sintered body 112. Along with this, a plurality of capacitors are integrally stored.
[0005]
This multilayer feedthrough capacitor array is generally used for products having a small mounting space as described above. For this reason, the multilayer through-type capacitor array has a length of 2.0 mm, a width of 1.25 mm, a height of about 0.5 to 2.0 mm, or a length less than 1.6 mm and a width of 0.8mm, height 0.3-1.0mm, length 1.0mm, width 0.5mm, height 0.2-0.8mm, etc. It is desired.
[0006]
[Patent Document 1]
JP-A-9-35998
[Patent Document 2]
JP-A-7-169649
[Patent Document 3]
Japanese Patent Laid-Open No. 11-154621
[Patent Document 4]
JP 55-80313 A
[0007]
[Problems to be solved by the invention]
However, in accordance with the downsizing of the multilayer feedthrough capacitor array as described above, the sizes of the sagging portions 141 and 142 that are portions where the terminal electrodes 131 to 140 protrude from the upper and lower surfaces of the ceramic sintered body 112 are controlled. It became necessary to do. That is, if the sizes of the sagging portions 141 and 142 are not controlled, for example, an overlap occurs between the innermost electrode 121 and the sagging portion 142 shown in FIG. Will occur.
[0008]
Further, when the overlap between the internal electrode 121 and the sagging portion 142 is not constant, the variation in the floating capacitance increases, and as the floating capacitance increases, crosstalk or the like occurs. In addition, the characteristics of the electronic circuit may be greatly deteriorated due to parasitic transmission. It can be understood from the specific graph of FIG. 10 that the stray capacitance increases as the overlapping area between the internal electrode and the sagging portion increases.
[0009]
On the other hand, as shown in FIG. 9, a large ground land 44 is formed on the substrate 43 so that the ground terminal electrodes 139 and 140 are securely connected to the substrate 43 on which the multilayer feedthrough capacitor array is mounted by solder (not shown). In this case, stray capacitance is also generated in the facing portion S2 between the ground land 44 and the signal line internal electrode 125. The presence of this floating capacitance also has a drawback that the cutoff frequency is shifted as a result of the change in the capacitance of the entire multilayer feedthrough capacitor array and the shift of the resonance point.
[0010]
An object of the present invention is to provide a multilayer capacitor that eliminates parasitic parasitic parasitic capacitance in consideration of the above facts.
[0011]
[Means for Solving the Problems]
A multilayer capacitor according to claim 1 is a capacitor main body formed by laminating a plurality of dielectric sheets along the lamination direction;
At least one first inner conductor disposed within the capacitor body;
The first inner conductor and the first inner conductor overlap with each other through a dielectric sheet, and are disposed closer to the outer layer side of the capacitor body in the stacking direction than the first inner conductor, and sandwich the first inner conductor. At least two second inner conductors;
A signal terminal electrode that is arranged to cover the side surface of the capacitor body while being connected to the first inner conductor, and can be connected to the outside for signal use;
A ground terminal electrode arranged to cover the side surface of the capacitor body while being connected to the second inner conductor, and connected to the outside for grounding;
And
The length of the portion of the ground terminal electrode protruding from the surface forming the end of the capacitor body in the stacking direction is longer than the length of the portion of the signal terminal electrode protruding from the surface of the capacitor body forming the end in the stacking direction. , Characterized by being lengthened.
[0012]
According to the multilayer capacitor in accordance with the first aspect of the present invention, at least one first internal conductor is disposed in a capacitor body formed by laminating a plurality of dielectric sheets along the laminating direction. In addition, at least two second internal conductors are arranged on the outer side in the stacking direction of the capacitor body with respect to the first internal conductors so as to overlap each other through the dielectric sheet in the stacking direction with the first internal conductors. The two second inner conductors sandwich the first inner conductor.
[0013]
Further, a signal terminal electrode arranged so as to cover the side surface of the capacitor body is connected to the first inner conductor, and a ground terminal electrode similarly arranged so as to cover the side surface of the capacitor body is used as the second inner conductor. It is connected. In this claim, the length of the portion of the ground terminal electrode that protrudes from the surface of the capacitor body that forms the end in the stacking direction is the signal that protrudes from the surface of the capacitor body that forms the end of the capacitor in the stacking direction. It is made longer than the length of the terminal electrode portion for use.
[0014]
That is, the multilayer capacitor generates a capacitance between the first inner conductor for the signal line and the second inner conductor for the ground line. However, in the multilayer capacitor of the present invention, the inner electrode of the outermost layer is always provided. It was set as the 2nd internal conductor for ground lines.
[0015]
However, if the second inner conductor is simply arranged as the innermost electrode of the outermost layer, the influence of the signal terminal electrode becomes relatively large as the multilayer capacitor is downsized. There is a risk that electric capacity will be generated. Therefore, in this claim, the signal terminal electrode protrudes from the surface forming the end of the capacitor body in the stacking direction so that the attenuation characteristic is emphasized and the second inner conductor for the ground line may be increased to some extent. The length of this portion was shortened to eliminate the overlap between the second inner conductor and the protruding portion of the signal terminal electrode.
[0016]
Furthermore, the length of the protruding portion of the terminal terminal for ground is made longer than the length of the protruding portion of the signal terminal electrode, and the length of the protruding portion of the ground terminal electrode on the surface forming the end in the stacking direction of the capacitor body is also extended. With this ground terminal electrode whose length is increased, the adhesion strength between the substrate and the ground land is improved.
[0017]
As described above, according to the present invention, it is possible to obtain a multilayer capacitor in which the parasitic capacitance of the floating capacitance is eliminated and the change in the capacitance value due to the influence of the floating capacitance can be controlled to be small. It becomes small, there is no parasitic transmission, and there is no shift in frequency characteristics such as transmission frequency.
[0018]
According to the multilayer capacitor of the second aspect, in addition to the configuration similar to the multilayer capacitor of the first aspect, the portion of the signal terminal electrode that protrudes from the surface forming the end of the capacitor body in the stacking direction is The second inner conductor is projected along the second inner conductor. That is, by controlling these dimensions so that the protruding portion of the signal terminal electrode and the second inner conductor do not overlap, the floating capacitance becomes smaller, and the capacitance caused by the influence of the floating capacitance The change in value can be controlled more reliably.
[0019]
According to the multilayer capacitor of the third aspect, in addition to the same configuration as the multilayer capacitor of the first and second aspects, the first inner conductor and the second inner conductor are drawn out in a direction crossing each other. The signal terminal electrode and the ground terminal electrode are formed on different side surfaces of the capacitor body. Therefore, according to the present claim, not only the same effect as in the first aspect occurs, but also the terminal electrodes are optimally arranged on the side surface of the capacitor body, so that the multilayer capacitor can be further reduced in size. It becomes.
[0020]
According to the multilayer capacitor of the fourth aspect, in addition to the same configuration as the multilayer capacitor of the first to third aspects, the first inner conductor is drawn out to the two opposite side surfaces of the capacitor body, and the first The second inner conductor is drawn out on the two opposite side surfaces of the capacitor body different from the two side surfaces from which the first inner conductor is drawn, and the signal is connected to the first inner conductor on the two side surfaces from which the first inner conductor is drawn. Each of the terminal electrodes is disposed, and ground terminal electrodes connected to the second inner conductor are disposed on the two side surfaces from which the second inner conductor is drawn.
[0021]
That is, as the first inner conductor is drawn out on the two side surfaces of the capacitor body facing each other, the signal terminal electrodes are respectively disposed on these two side surfaces, and the capacitor body facing each other As the second inner conductor is drawn out on the two side surfaces, the ground terminal electrodes are arranged on the two side surfaces, respectively. Therefore, it is possible to more reliably achieve the function and effect of the first aspect while effectively reducing the size by effectively using the side surface of the capacitor body.
[0022]
According to the multilayer capacitor in accordance with a fifth aspect of the present invention, in addition to the configuration similar to that of the multilayer capacitor of the fourth aspect, the capacitor main body is formed in a rectangular parallelepiped shape. That is, the dielectric sheets are each formed in a quadrilateral shape such as a rectangle, and the dielectric sheets are laminated, so that the capacitor body is formed in a rectangular parallelepiped shape.
[0023]
The multilayer capacitor according to claim 4 has a first inner conductor drawn to two side surfaces of the capacitor body and a second inner conductor drawn to two side surfaces of the capacitor body different from these. Therefore, the lead portion of the internal conductor is provided on all the side surfaces of the capacitor body formed in a rectangular parallelepiped shape having four optimal side surfaces from the viewpoint of productivity, and it becomes easier to reduce the size of the multilayer capacitor.
[0024]
According to the multilayer capacitor of the sixth aspect, in addition to the same configuration as the multilayer capacitor of the first to fifth aspects, a plurality of first inner conductors are arranged in the same plane, and the plurality of first inner conductors Correspondingly, a plurality of signal terminal electrodes are provided. That is, according to the multilayer capacitor of this claim, since it has an array structure in which a plurality of capacitors are built in, the size can be further reduced, and it can be applied even when the mounting space is smaller.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of a multilayer capacitor according to the present invention will be described with reference to the drawings.
1 to 5 show a multilayer feedthrough capacitor array 10 which is a multilayer capacitor according to the present embodiment. As shown in these figures, it is obtained by firing a laminated body in which a plurality of ceramic green sheets, which are dielectric sheets, are laminated in the laminating direction which is the vertical direction in FIGS. 2, 4 and 5. The multilayer through-type capacitor array 10 is configured with a dielectric body 12 which is a rectangular parallelepiped sintered body as a main part.
[0026]
As shown in FIG. 3, an internal electrode 21 extending between the left side and the right side of FIG. 3 of the dielectric body 12 is disposed at a predetermined height position in the dielectric body 12. Further, in the dielectric body 12, below the internal electrode 21 across the ceramic layer 12 </ b> A which is a sintered ceramic green sheet, the front side and the back side of the dielectric body 12 in FIG. A plurality (four in this embodiment) of internal electrodes 22 each extending between them are arranged.
[0027]
Furthermore, an internal electrode 23 extending between the left side and the right side of FIG. 3 of the dielectric body 12 is provided below the internal electrode 22 across the ceramic layer 12A in the dielectric body 12 in the same manner as the internal electrode 21. Have been placed. In addition, a plurality of (four in this embodiment) respectively extend between the front side and the back side of FIG. 3 of the dielectric element body 12 below the internal electrode 23 that separates the ceramic layer 12A in the dielectric element body 12. ) Is arranged so as to have the same positional relationship as the internal electrode 22. In the dielectric element body 12, an internal electrode 25 extending between the left side and the right side in FIG. 3 of the dielectric element body 12 is provided below the internal electrode 24 that separates the ceramic layer 12 </ b> A. Have been placed.
[0028]
For this reason, the five layers of internal electrodes from the internal electrode 21 to the internal electrode 25 are a ceramic layer 12A which is a dielectric layer in the dielectric element body 12 which is a capacitor body and is a dielectric sheet after firing. It will be arranged facing each other while being separated. That is, in the present embodiment, at least one ceramic layer 12A is sandwiched between the internal electrodes 21 and 25, and at least one ceramic layer is disposed above the internal electrode 21 and below the internal electrode 25. The ceramic layers 12A are respectively disposed.
[0029]
At this time, the three internal electrodes 21, 23, 25 are arranged so as to overlap with the two layers of internal electrodes 22, 24 via the ceramic layer 12 </ b> A in the stacking direction (direction indicated by arrow Z in FIG. 3). ing. Furthermore, these two layers of internal electrodes 22 and 24, which are first internal conductors, serve as signal-side internal electrodes and are second internal conductors extending in a direction intersecting with each other with respect to the internal electrodes 22 and 24. The internal electrodes 21, 23, and 25 are ground-side internal electrodes, and the internal electrodes 22, 24 and the internal electrodes 21, 23, 25 constitute the internal electrode of the capacitor.
[0030]
As described above, in the present embodiment, although the first inner conductor and the second inner conductor are alternately arranged, the first inner conductor has two layers, whereas the second inner conductor has Since there are three, the internal electrodes 21 and 25 as the second internal conductors are respectively disposed closer to the outer layer side in the stacking direction of the dielectric body 12 with respect to the internal electrodes 22 and 24. The internal electrodes 21 and 25 sandwich the two layers of internal electrodes 22 and 24. These internal electrodes may be arranged not only in five layers as described above, but also in a large number of layers, and as a material of these internal electrodes, for example, a metal electrode material mainly composed of nickel which is a base metal material Can be considered.
[0031]
Further, as shown in FIG. 3, the left and right end portions of the internal electrodes 21, 23, 25 have narrow widths drawn to the left and right side surfaces 12B (shown in FIG. 2) of the dielectric body 12 facing each other. Leaders 21A, 23A, and 25A are formed, respectively. In addition, narrow portions that are drawn to the front and back side surfaces 12C (shown in FIG. 2) of the dielectric element body 12 are provided on the front and back side portions of the internal electrodes 22 and 24 that are arranged in two layers of four each. The lead-out portions 22A and 24A are respectively formed.
[0032]
Accordingly, the lead portions 21A, 23A, 25A of the internal electrodes 21, 23, 25 are drawn to the left and right side surfaces 12B facing each other, and the lead portions 22A, 24A of the internal electrodes 22, 24 intersect this lead direction. The multilayer feedthrough capacitor array 10 according to the present embodiment has a structure that is different from these side surfaces and is drawn out to the two side surfaces 12C opposed to each other.
[0033]
On the other hand, a plurality of signal terminal electrodes 31 to 38 shown in FIGS. 1 and 2 (four on each side surface in this embodiment) are connected to the lead portions 22A and 24A of the internal electrodes 22 and 24, respectively. Is disposed outside the dielectric body 12 so as to cover the front and back side surfaces 12C of the dielectric body 12 facing each other along the vertical direction of FIGS.
[0034]
That is, the lead-out portions 22A and 24A of the internal electrodes 22 and 24 located at the left end in FIG. 3 are connected to the signal terminal electrodes 31 and 32 shown in FIGS. 1 and 2, respectively, and the second internal electrode located from the left side. The lead-out portions 22A and 24A of 22 and 24 are connected to signal terminal electrodes 33 and 34 shown in FIGS. Further, the lead-out portions 22A and 24A of the internal electrodes 22 and 24 located third from the left in FIG. 3 are connected to the signal terminal electrodes 35 and 36 shown in FIGS. 1 and 2, respectively, and the internal electrodes located on the right end. The lead-out portions 22A and 24A of 22 and 24 are connected to signal terminal electrodes 37 and 38 shown in FIGS. 1 and 2, respectively.
[0035]
Further, the ground terminal electrodes 39 and 40 shown in FIGS. 1 and 2 are connected to the lead portions 21A, 23A, and 25A of the internal electrodes 21, 23, and 25, respectively. The left and right side surfaces 12B facing each other are disposed outside the dielectric body 12 so as to cover the left and right side surfaces 12B in the vertical direction of FIGS.
[0036]
The signal terminal electrodes 31 to 38 and the ground terminal electrodes 39 and 40 protrude from the upper and lower surfaces 12D, which are the surfaces forming the end portions of the dielectric body 12 in the stacking direction. . However, in the present embodiment, the sagging portion 41 that is the portion of the signal terminal electrodes 31 to 38 that protrudes from the upper and lower surfaces 12D extends along the stacking direction of the internal electrodes 21, 23, and 25 perpendicular to the paper surface of FIG. The sagging portion 41 of the signal terminal electrodes 31 to 38 was formed small so as not to overlap the projected portion. Accordingly, the length L1 of the saucer portion 41 that is the portion of the signal terminal electrodes 31 to 38 that protrudes from the upper and lower surfaces 12D is shortened, and from this length L1, the ground terminal electrode 39 that protrudes from the upper and lower surfaces 12D, The length L2 of the sagging portion 42, which is the portion 40, is increased.
[0037]
As shown in FIGS. 4 and 5, the signal terminal electrodes 31 to 38 and the ground terminal electrodes 39 and 40 each have a three-layer structure. Specifically, the innermost layer A is constituted by baking of copper (copper) and frit, and the intermediate layer B is constituted by nickel electrolytic plating. Furthermore, the outermost layer C is constituted by tin electroplating. In this embodiment, the signal terminal electrodes 31 to 38 can be connected to an external circuit for signals, and the ground terminal electrodes 39 and 40 are connected to an external circuit for grounding. To be able to be.
[0038]
Next, the operation of the multilayer feedthrough capacitor array 10 according to the present embodiment will be described.
According to the multilayer through-type capacitor array 10 according to the present embodiment, a plurality of dielectric sheets each serving as the ceramic layer 12A are laminated along the laminating direction to form the dielectric element body 12 in a rectangular parallelepiped shape.
[0039]
In the dielectric body 12, four internal electrodes 22 and four internal electrodes 24 are arranged respectively. Also, the three internal electrodes 21, 23, 25 are alternately arranged with these two layers of internal electrodes 22, 24 so as to overlap with the internal electrodes 22, 24 via the ceramic layer 12A in the stacking direction. . For this reason, the internal electrodes 21 and 25 are arranged at positions closer to the outer layer side of the dielectric body 12 with respect to the internal electrodes 22 and 24 (the direction indicated by the arrow Z in FIGS. 4 and 5). The internal electrodes 22, 24 are sandwiched between the internal electrodes 21, 25.
[0040]
That is, such a multilayer feedthrough capacitor array generates a capacitance between the signal line internal electrodes 22, 24 and the ground line internal electrodes 21, 23, 25. In the multilayer through-type capacitor array 10, the outermost internal electrodes are always the internal electrodes 21 and 25 that are the second internal conductors for the ground line.
[0041]
Furthermore, signal terminal electrodes 31 to 38 arranged so as to cover the two opposite side surfaces 12C of the dielectric body 12 are connected to the internal electrodes 22 and 24, respectively. Ground terminal electrodes 39 and 40 arranged so as to cover the two opposite side surfaces 12B are connected to the internal electrodes 21, 23 and 25, respectively.
[0042]
In the present embodiment, the sagging portions 41 of the signal terminal electrodes 31 to 38 that protrude from the upper and lower surfaces 12D of the dielectric body 12 are arranged in the stacking direction (perpendicular to the paper surface of FIG. 1), as shown in FIG. Are formed small so as not to overlap the portions of the internal electrodes 21, 23, 25 projected along the direction. Accordingly, the length L2 of the sagging portion 42 of the ground terminal electrodes 39 and 40 that protrudes from the upper and lower surfaces 12D of the dielectric element body 12 corresponds to the signal terminal electrodes that protrude from the upper and lower surfaces 12D of the dielectric element body 12. It is longer than the length L1 of the sagging portion 41 of 31 to 38.
[0043]
In other words, in the present embodiment, the signal terminal that protrudes from the upper and lower surfaces 12D of the dielectric body 12 is emphasized so that the attenuation characteristics are emphasized and the internal electrodes 21, 23, 25 for the ground line may be increased to some extent. The length of the sagging portion L1 of the electrodes 31 to 38 is shortened so that the internal electrodes 21, 23, 25 and the sagging portion L1 of the signal terminal electrodes 31 to 38 are not overlapped.
[0044]
Further, the length L2 of the sagging portion 42 of the ground terminal electrodes 39, 40 that protrudes from the upper and lower surfaces 12D of the dielectric body 12 from the length L1 of the sagging portion 41 of the protruding signal terminal electrodes 31 to 38. As shown in FIG. 4, the ground terminal electrodes 39 and 40 with the length L2 of the sagging portion 42 are increased to improve the bonding strength between the substrate 43 and the ground land 44 shown in FIG. I tried to do it.
[0045]
As described above, according to the present embodiment, it is possible to obtain the multilayer feedthrough capacitor array 10 in which the parasitic parasitic capacitance is eliminated and the change in the capacitance value due to the influence of the floating capacitance can be controlled to be small. As a result, the crosstalk is reduced, and there is no parasitic transmission, resulting in a highly reliable, small and high performance multilayer feedthrough capacitor array 10 with no deviation in frequency characteristics such as transmission frequency.
[0046]
On the other hand, when manufacturing the multilayer feedthrough capacitor array 10 according to the present embodiment, the dielectric element body 12 was formed in a rectangular parallelepiped shape by laminating dielectric sheets each formed in a quadrilateral shape such as a rectangle.
[0047]
Accordingly, the multilayer feedthrough capacitor array 10 of the present exemplary embodiment includes four internal electrodes 22, four internal electrodes 24 that are respectively drawn out from the two side surfaces 12 </ b> C of the dielectric body 12, and two different from these. Three internal electrodes 21, 23, 25 led out to the side surface 12 </ b> B are provided. Therefore, from the viewpoint of productivity, all the side surfaces 12B and 12C of the dielectric element body 12 formed in a rectangular parallelepiped shape having four side surfaces 12B and 12C that are optimal are provided with internal electrode lead-out portions. It becomes easier to reduce the size of the mold capacitor array 10.
[0048]
Next, using a network analyzer, the following characteristics of each sample were measured, and the attenuation characteristics of each sample were obtained.
First, the content of the sample to be each sample and the attenuation characteristic measurement circuit will be described. That is, the multilayer feedthrough capacitor array shown in FIGS. 8 and 9 is a conventional example, and the multilayer feedthrough capacitor array according to the embodiment shown in FIGS. 1 to 5 is an example. Further, by arranging the sample 55 in the attenuation characteristic measuring circuit having the oscillator 51, the two resistors 52 and 53 and the meter 54 shown in FIG. 7, the result of measuring the characteristic of each sample is the attenuation characteristic measurement. It is displayed by the meter 54 of the circuit.
[0049]
Then, as shown in the graph of FIG. 6, from the data of the characteristic curve A representing the attenuation characteristic of the conventional example and the data of the characteristic curve B representing the attenuation characteristic of the embodiment, on the horizontal axis of the graph of FIG. It can be seen that the resonance point of the characteristic curve A of the conventional example is located at 2600 MHz represented by the point C, whereas the resonance point of the characteristic curve B of the example is located at 3100 MHz represented by the point D.
[0050]
As a result, it can be seen from the data of the graph of FIG. 6 that the resonance point of the embodiment is located closer to the high frequency side by about 500 MHz than the conventional example. It is confirmed that a resonance point is generated at an appropriate frequency without or being small.
[0051]
In the multilayer feedthrough capacitor array according to the above-described embodiment, the five layers of internal electrodes are arranged. However, the number of layers is not limited to these, and the number of layers is further increased. Alternatively, it may be several hundred. Furthermore, in the above-described embodiment, each internal conductor is drawn out on the two opposite side surfaces of the capacitor body. However, the internal conductor is drawn out only on one side surface, and only on one side surface according to this structure. A multilayer capacitor array structure in which signal terminal electrodes and ground terminal electrodes are arranged may be employed.
[0052]
On the other hand, in the above embodiment, four first inner conductors are arranged in the same plane. However, two, three, five or more first inner conductors are arranged. Also good. Also, a single multilayer feedthrough capacitor structure in which a plurality of first inner conductors arranged in the same plane is single and only one first inner conductor is arranged in the same plane may be adopted.
[0053]
【The invention's effect】
According to the present invention, it is possible to provide a multilayer capacitor that eliminates parasitic parasitic parasitic capacitance.
[Brief description of the drawings]
FIG. 1 is a plan view of a multilayer feedthrough capacitor array according to an embodiment of the present invention.
FIG. 2 is a perspective view showing a multilayer through-type capacitor array according to an embodiment of the present invention.
FIG. 3 is an exploded perspective view of a multilayer through-type capacitor array according to an embodiment of the present invention.
4 is a cross-sectional view showing a state in which the multilayer through-type capacitor array according to the embodiment of the present invention is mounted on a substrate, corresponding to a cross section taken along line 4-4 in FIG.
5 is a cross-sectional view illustrating a multilayer through-type capacitor array according to an embodiment of the present invention, and corresponds to a cross section taken along line 5-5 in FIG.
FIG. 6 is a graph showing attenuation characteristics of each sample.
FIG. 7 is a diagram showing an attenuation characteristic measurement circuit for measuring the attenuation characteristic of each sample.
FIG. 8 is a plan view of a multilayer feedthrough capacitor array according to the prior art.
9 is a cross-sectional view showing a state in which a multilayer feedthrough capacitor array according to the prior art is mounted on a substrate, and is a view corresponding to a cross section taken along line 9-9 in FIG.
FIG. 10 is a graph showing a relationship between an overlapping area between an internal electrode and a sagging portion and stray capacitance.
[Explanation of symbols]
10 Multilayer feedthrough capacitor array (multilayer capacitor)
12 Dielectric body (capacitor body)
12A Ceramic layer (dielectric sheet)
12B side
12C side
12D Top and bottom
21 Internal electrode (second internal conductor)
22 Internal electrode (first internal conductor)
23 Internal electrode (second internal conductor)
24 Internal electrode (first internal conductor)
25 Internal electrode (second internal conductor)
31-38 Signal terminal electrode
39, 40 Ground terminal electrode
41 Sauce
42 Sauce

Claims (6)

A capacitor body formed by laminating a plurality of dielectric sheets along the laminating direction;
At least one first inner conductor disposed within the capacitor body;
The first inner conductor and the first inner conductor overlap with each other through a dielectric sheet, and are disposed closer to the outer layer side of the capacitor body in the stacking direction than the first inner conductor, and sandwich the first inner conductor. At least two second inner conductors;
A signal terminal electrode that is arranged to cover the side surface of the capacitor body while being connected to the first inner conductor, and can be connected to the outside for signal use;
A ground terminal electrode arranged to cover the side surface of the capacitor body while being connected to the second inner conductor, and connected to the outside for grounding;
And
The length of the portion of the ground terminal electrode protruding from the surface forming the end of the capacitor body in the stacking direction is longer than the length of the portion of the signal terminal electrode protruding from the surface of the capacitor body forming the end in the stacking direction. A multilayer capacitor characterized by being lengthened. 2. The multilayer structure according to claim 1, wherein the portion of the signal terminal electrode that protrudes from the surface forming the end of the capacitor body in the stacking direction does not overlap the portion of the second inner conductor projected along the stacking direction. Capacitor. The first inner conductor and the second inner conductor are formed so as to be drawn out in directions intersecting each other, and the signal terminal electrode and the ground terminal electrode are arranged on different side surfaces of the capacitor body. The multilayer capacitor according to claim 1 or 2. The first inner conductor is drawn out to the two opposite sides of the capacitor body, and the second inner conductor is drawn to the two opposite sides of the capacitor body different from the two sides from which the first inner conductor is drawn, respectively.
Signal terminal electrodes connected to the first inner conductor are respectively disposed on the two side surfaces from which the first inner conductor is drawn,
4. The multilayer capacitor according to claim 1, wherein ground terminal electrodes connected to the second inner conductor are respectively disposed on two side surfaces from which the second inner conductor is drawn. 5. The multilayer capacitor according to claim 4, wherein the capacitor body is formed in a rectangular parallelepiped shape. 6. A plurality of first inner conductors are arranged in the same plane, and a plurality of signal terminal electrodes are provided corresponding to the plurality of first inner conductors. Multilayer capacitor.

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