JP6363444B2 - Multilayer capacitor - Google Patents

Description

  The present invention relates to a multilayer capacitor used for a noise filter or the like with reduced equivalent series inductance (ESL) in a high frequency region.

  In recent years, information processing devices, communication devices, and the like have been digitized, and the frequency of digital signals handled by these devices has been increasing with the increase in information processing capability. Therefore, in these devices, the generated noise tends to increase in the high frequency region as well, and for example, electronic components such as multilayer capacitors are used for noise countermeasures. An example of such a multilayer capacitor is disclosed in Patent Document 1.

JP 2005-44871 A

  As described above, the multilayer capacitor is used, for example, to suppress noise from entering the LSI from the power supply line or other devices in an LSI power circuit such as a CPU, or to prevent malfunction of the LSI. It is used for.

  However, the trend toward higher frequencies is increasing in information processing equipment or communication equipment, and multilayer capacitors are subject to noise in high frequency areas, for example, noise in high frequency areas such as signal lines or power supply lines. In order to reduce, ESL must be further reduced.

  The present invention has been made in view of the above-described problems, and an object thereof is to provide an equivalent series by arranging a signal internal electrode and a ground internal electrode so as to face each other in the same plane in the laminate. An object of the present invention is to provide a multilayer capacitor capable of reducing inductance (ESL).

In the multilayer capacitor of the present invention, a plurality of dielectric layers are stacked to connect the first and second main surfaces facing each other and the first and second main surfaces facing each other. A laminated body formed in a substantially rectangular parallelepiped shape having a first end face and a second side face facing each other, connecting the second end face and the first and second end faces, and the dielectric layer in the laminated body And at least a first signal internal electrode drawn out to the first end face, and the first signal internal electrode at a predetermined interval in the same plane as the first signal internal electrode The first grounding internal electrode led out to the first side surface, which is disposed opposite to the first grounding internal electrode, and the first grounding internal electrode disposed in a stacking direction with the dielectric layer interposed therebetween. For at least the second signal drawn out to the second end face The second signal internal electrode is disposed at a position overlapping the partial electrode and the first signal internal electrode in the stacking direction and at a predetermined interval in the same plane as the second signal internal electrode. And a second grounding internal electrode led out to the second side surface and disposed at the first end surface and connected to at least the first signal internal electrode. A signal external terminal including one signal external terminal and at least a second signal external terminal connected to the second signal internal electrode and disposed on the second end face; A first grounding external terminal connected to the first grounding internal electrode and a second grounding terminal connected to the second grounding internal electrode arranged on the second side surface. and a grounding external terminal and an grounding external terminal, wherein 1 ground internal electrode and the second ground internal electrodes is what the thickness of the electrode is equal to or greater than the first signal internal electrode and the second signal internal electrodes.

  According to the multilayer capacitor of the present invention, the equivalent series inductance (ESL) can be lowered by disposing the signal internal electrode and the ground internal electrode so as to face each other in the same plane in the multilayer body.

1 is a schematic perspective view showing a multilayer capacitor according to an embodiment. (A) is the cut part end surface cut | disconnected by the AA line of the multilayer capacitor | condenser shown in FIG. 1, (b) is the cut part end surface cut | disconnected by the BB line | wire of the multilayer capacitor | condenser shown in FIG. FIG. FIG. 2 is a schematic exploded perspective view of the multilayer capacitor shown in FIG. 1. FIG. 2 is a cross-sectional view of the multilayer body orthogonal to the stacking direction of the multilayer capacitor shown in FIG. 1, wherein (a) is a cross-sectional view showing a first signal internal electrode and a first grounding internal electrode. FIG. 5B is a cross-sectional view showing the second signal internal electrode and the second grounding internal electrode. (A) And (b) is another example of the multilayer capacitor shown in FIG. 1, and is a cut end view taken along a line corresponding to the CC line of the multilayer capacitor shown in FIG. (A) And (b) is another example of the multilayer capacitor shown in FIG. 1, and is a cut end view taken along a line corresponding to the CC line of the multilayer capacitor shown in FIG. It is the figure which showed the graph showing the attenuation | damping characteristic of a multilayer capacitor. (A) And (b) is explanatory drawing for demonstrating the structure of the internal electrode of the multilayer capacitor of a prior art example.

<Embodiment 1>
The multilayer capacitor 10 according to Embodiment 1 of the present invention will be described below with reference to the drawings.

  FIG. 1 is a schematic perspective view showing a multilayer capacitor 10 according to an embodiment of the present invention. FIG. 2A is a cross-sectional view taken along line AA of the multilayer capacitor 10 shown in FIG. FIG. 2B is an end view of the cut portion taken along line BB. The multilayer capacitor 10 may have either direction upward or downward. For convenience, the multilayer capacitor 10 defines an orthogonal coordinate system XYZ, and the upper side or the lower side with the positive side in the Z direction as the upper side. The following terms shall be used.

  The multilayer capacitor 10 will be described below with reference to the drawings.

  As shown in FIGS. 1 to 4, the multilayer capacitor 10 includes a multilayer body 1, a signal internal electrode 2 (a first signal internal electrode 2 a and a second signal internal electrode 2 b), and a ground internal electrode 3. (First grounding internal electrode 3a and second grounding internal electrode 3b), signal external terminal 4 (first signal external terminal 4a and second signal external terminal 4b), grounding external terminal 5 (First grounding external terminal 5a and second grounding external terminal 5b).

The multilayer body 1 is formed in a substantially rectangular parallelepiped shape by laminating a plurality of dielectric layers 1a, and the first and second main surfaces (1b, 1c) facing each other and the first and second surfaces facing each other. End faces (1d, 1e) have first and second side faces (1f, 1g) facing each other. The first and second end faces (1d, 1e) facing each other connect the first and second main faces (1b, 1c), and the first and second faces facing each other. Side (1f, 1g)
Connects the first and second main faces (1b, 1c) and the first and second end faces (1d, 1e). Note that the substantially rectangular parallelepiped shape includes not only a cubic shape or a rectangular parallelepiped shape, but also includes, for example, a shape in which the ridge portion of the rectangular parallelepiped is chamfered and the ridge portion has an R shape.

  The laminated body 1 is a sintered body obtained by laminating and firing a plurality of ceramic green sheets to be the dielectric layer 1a. Thus, the laminated body 1 is formed in a substantially rectangular parallelepiped shape, and is formed on the first main surface 1b and the second main surface 1c, the first main surface 1b, and the second main surface 1c facing each other. The first end face 1d and the second end face 1e that are orthogonal and face each other, and the first side face 1f and the second side face 1g that are orthogonal to the first end face 1d and the second end face 1e and face each other. And have. Moreover, as for the laminated body 1, the plane used as the cross section (XY surface) of a direction orthogonal to the lamination direction (Z direction) of the dielectric material layer 1a is a rectangular shape as shown in FIG.

  The dimension of the multilayer capacitor 10 having such a configuration is such that the length in the longitudinal direction (Y direction) is, for example, 0.6 (mm) to 2.2 (mm), and the length in the short direction (X direction). However, the length in the height direction (Z direction) is, for example, 0.3 (mm) to 1.5 (mm), for example, 0.3 (mm) to 1.2 (mm).

  The dielectric layer 1a is rectangular in a plan view from the stacking direction, and the thickness per layer is, for example, 0.5 (μm) to 3.0 (μm). In the laminated body 1, for example, a plurality of dielectric layers 1a composed of 10 (layers) to 1000 (layers) are laminated in the Z direction.

  The signal internal electrode 2 includes a first signal internal electrode 2a and a second signal internal electrode 2b, and the ground internal electrode 3 includes the first ground internal electrode 3a and the second ground internal electrode 3b. The signal internal electrode 2 and the ground internal electrode 3 are disposed between the dielectric layers 1a, respectively, and the first main surface 1b and the second main surface 1b of the multilayer body 1 are included. Are provided so as to be parallel to the main surface 1c.

  The first signal internal electrode 2a is disposed between the dielectric layers 1a and is drawn out to at least one of the first end face 1d and the second side face 1e. The first ground internal electrode 3a is The first signal internal electrode 2a is disposed in the same plane as the first signal internal electrode with a predetermined interval, and is led out to the first side face 1f. Thus, the first signal internal electrode 2a and the first grounding internal electrode 3a are in the same plane in the direction orthogonal to the stacking direction in the stacked body 1, as shown in FIGS. Inside, it arrange | positions so that it may mutually oppose in the center part of the transversal direction (X direction) of the laminated body 1. FIG. That is, the first signal internal electrode 2a and the first grounding internal electrode 3a are arranged in parallel to the first side face 1f and the second side face 1g with a predetermined interval therebetween.

  The first signal internal electrode 2a is formed in the multilayer body 1, and has a quadrangular shape in plan view from the lamination direction, as shown in FIG. 4A. The first grounding internal electrode 3a is formed in the same plane as the first signal internal electrode 2a, and has a quadrangular shape in plan view from the stacking direction. The first grounding inner electrode 3a is provided with a lead part 3c extending from a side part on the first side face 1f side of the square shape to the first side face 1f, and the end part of the lead part 3c is the first part. It is pulled out to the first side face 1f so as to be exposed to the side face 1f of the first side. In addition, in FIG. 4A, the first grounding internal electrode 3a is provided with two lead portions 3c, but this is not limiting, and one or three or more lead portions 3c are provided. May be.

Thus, the first signal internal electrode 2a and the first grounding internal electrode 3a are paired in the same plane with a predetermined interval as shown in FIGS. 3 and 4A. They are arranged so as to face each other, and have a facing portion parallel to the longitudinal direction (Y direction) in the central region in the short direction (X direction) within the same plane. The predetermined interval is, for example, 30 (μm) to 50 (μm). The term “in the same plane” means that the same dielectric layer exists.

  The second signal internal electrode 2b has the same shape as the first signal internal electrode 2a, and is disposed via the dielectric layer 1a at a position overlapping the first ground internal electrode 3a in the stacking direction. It is pulled out to at least one of the first end face 1d and the second side face 1e.

  Thus, the first signal internal electrode 2a is formed in the multilayer body 1 and has a quadrangular shape in plan view as shown in FIGS. 2 to 4, and the second ground internal electrode in the stacking direction. It arrange | positions between 3b and is pulled out by the at least one side surface of the two side surfaces (1d, 1e) which the laminated body 1 opposes. The second signal internal electrode 2b is formed in the multilayer body 1 and has a quadrangular shape in plan view, and is disposed between the first grounding internal electrodes 3a in the stacking direction, and is opposed to two side surfaces. It is pulled out to at least one side surface of (1d, 1e).

  In the multilayer capacitor 10, the first signal internal electrode 2a and the second signal internal electrode 2b are drawn out to both end surfaces of the first end surface 1d and the second end surface 1e. The first signal internal electrode 2a and the second signal internal electrode 2b only have to be drawn out to either the first end face 1d or the second end face 1e.

  The second grounding internal electrode 3b is disposed at a position overlapping the first signal internal electrode 2a in the stacking direction, and is disposed in the same plane as the second signal internal electrode 2b via a predetermined interval. The second signal inner electrode 2b is disposed opposite to the second signal inner electrode 2b and is drawn out to the second side surface 1g. As described above, the second signal internal electrode 2b and the second grounding internal electrode 3b are short in the lateral direction of the multilayer body 1 in the same plane perpendicular to the lamination direction in the multilayer body 1. It arrange | positions so that it may mutually oppose in the center part (X direction). In other words, the second signal internal electrode 2b and the second grounding internal electrode 3b are arranged in parallel with the first side face 1f and the second side face 1g with a predetermined distance therebetween.

As shown in FIG. 4B, the second signal internal electrode 2b has a quadrangular shape in plan view from the stacking direction. Further, the second grounding internal electrode 3b has a quadrangular shape in plan view from the stacking direction. The second grounding internal electrode 3b is formed in the same plane as the second signal internal electrode 2b, and the lead-out portion 3d extends from the side portion on the second side surface 1g side to the second side surface 1g.
And extended to the second side surface 1g so that the end of the lead portion 3d is exposed to the second side surface 1g. The second grounding internal electrode 3b is provided with two lead portions 3d in FIG. 4B, but is not limited thereto, and one or three or more lead portions 3d are provided. May be.

  As described above, the second signal internal electrode 3b and the second ground internal electrode 3b are paired in the same plane with a predetermined interval as shown in FIGS. 3 and 4B. They are arranged to face each other, and have a facing portion parallel to the longitudinal direction (Y direction) in the central region in the short side direction (X direction) in the same plane. The predetermined interval is, for example, 30 (μm) to 50 (μm). The term “in the same plane” means that the same dielectric layer exists.

Further, as shown in FIGS. 3 and 4, the multilayer capacitor 10 is arranged so that the first grounding internal electrode 3 a is drawn out to the first side face 1 f in the lamination direction. The second grounding internal electrode 3b is arranged so that the lead portion 3d is drawn to the second side surface 1g, and the lead portion 3c and the lead portion 3d are in the X direction in plan view from the stacking direction. They are arranged opposite to each other. The lead portion 3c may be provided at any position as long as it is located on the first side face 1f side of the first grounding internal electrode 3a, and the lead portion 3d is provided with the second grounding side. As long as it is located on the second side face 1g side of the internal electrode 3b, it may be provided at any position.

  Thus, in the multilayer capacitor 10, the second signal internal electrode 2b is sandwiched between the first ground internal electrodes 3a, and the first signal internal electrode 3b is sandwiched between the second ground internal electrodes 3b. The electrode 2a is sandwiched, and the first grounding internal electrode 3a and the second grounding internal electrode 3b have the same polarity. That is, in the multilayer capacitor 10, the first signal internal electrode 2a and the second ground internal electrode 3b are arranged so as to overlap each other in the stack direction, and the first ground internal electrode 3a The second signal internal electrodes 2b are arranged so as to overlap each other in the stacking direction.

  The conductive material of the signal internal electrode 2 is, for example, a metal material such as nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), or gold (Au), or one or more of these metal materials For example, an alloy material such as an Ag—Pd alloy. The signal internal electrode 2 has a thickness of, for example, 0.5 (μm) to 2 (μm). The first signal internal electrode 2a and the second signal internal electrode 2b are preferably formed of the same metal material or alloy material.

  The conductive material of the grounding internal electrode 3 is, for example, a metal material such as nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), or gold (Au), or these metal materials. For example, it is an alloy material such as an Ag—Pd alloy including one or more. The grounding internal electrode 3 has a thickness of, for example, 0.5 (μm) to 2 (μm). The first grounding internal electrode 3a and the second grounding internal electrode 3b are preferably formed of the same metal material or alloy material. The signal internal electrode 2 and the ground internal electrode 3 are preferably formed of the same metal material or alloy material.

  As shown in FIGS. 2 to 4, the multilayer capacitor 10 includes a first signal internal electrode 2 a and a first ground internal electrode 3 a as a set in the same plane. The second grounding internal electrode 3b and the second signal internal electrode 2b are paired via the dielectric layer 1a so as to face each other in the same plane. Are arranged. Thus, the first signal internal electrode 2a and the first grounding internal electrode 3a are provided side by side in the same plane, and the second grounding internal electrode 3b and the second grounding internal electrode 3a are provided in the same plane. The signal internal electrodes 2b are provided side by side, and as shown in FIG. 3, these are alternately arranged in order from the first main surface 1b side to the second main surface 1c via the dielectric layer 1a. ing. That is, the set of first signal internal electrode 2a and first grounding internal electrode 3a, and the set of second grounding internal electrode 3b and second signal internal electrode 2b are laminated body 1. The dielectric layers 1a are separated from each other and are arranged to face each other, and at least one dielectric layer 1a is sandwiched between them. A plurality of dielectric layers 1 a on which these internal electrodes are formed are laminated to form a multilayer body 1 that is a main body of the multilayer capacitor 10.

  Further, the multilayer capacitor 10 is not limited to the multilayer configuration as shown in FIG. For example, the multilayer capacitor 10 includes a second grounding internal electrode 3b and a second signal internal electrode 2b in the same plane, and the first signal internal electrode 2a and the first signal internal electrode 2b in the same plane. Grounding internal electrodes 3a may be provided, and these may be alternately arranged in order from the first main surface 1b side to the second main surface 1c via the dielectric layer 1a. Further, the number of stacked layers of the signal internal electrode 2 and the ground internal electrode 3 is appropriately designed according to the characteristics of the multilayer capacitor 10 and the like.

The signal external terminal 4 includes a first signal external terminal 4a and a second signal external terminal 4b. The signal external terminals 4 are arranged on two opposite side surfaces (1d, 1e) of the laminate 1 so as to face each other. Yes. The first signal external terminal 4a is disposed on the first end face 1d and is connected to at least the first signal internal electrode 2a. The second signal external terminal 4b is connected to the second end face 1e. And is connected to at least the second signal internal electrode 2b. As shown in FIG. 1, the first signal external terminal 4a is provided so as to cover the entire first end face 1d, and the second signal external terminal 4b covers the entire second end face 1e. It is provided as follows.

  The signal external terminal 4 is connected to, for example, a signal line electrode or a current line electrode on a circuit board (not shown) on which the multilayer capacitor 10 is mounted.

  The first grounding external terminal 5a is disposed on the first side face 1f and connected to the first grounding internal electrode 3a. The second grounding external terminal 5b is connected to the second side face 1g. Arranged and connected to the second grounding internal electrode 3b. As shown in FIG. 4, the first grounding external terminal 5a is connected to the lead portion 3c of the first grounding internal electrode 3a, and the second grounding external terminal 5b is connected to the second grounding internal electrode 3b. It is connected to the drawer 3d.

  As described above, in the multilayer capacitor 10, the first grounding external terminal 5a and the second grounding external terminal 5b are connected to two opposing side surfaces (1f, 1f, 1g), the first grounding external terminal 5a is disposed on the first side face 1f, and the second grounding external terminal 5b is disposed on the second side face 1g. The first grounding external terminal 5a is provided so that the end portion extends from the first side surface 1f to the first main surface 1b and the second main surface 1c. The grounding external terminal 5b is provided such that an end thereof extends from the second side surface 1g to the first main surface 1b and the second main surface 1c. Further, the first grounding external terminal 5a and the second grounding external terminal 5b may be electrically connected in the laminate 1. For example, the first grounding external terminal 5a and the second grounding external terminal 5b are connected to one of the first main surface 1b and the second main surface 1c of the laminate 1. Alternatively, the first grounding external terminal 5a and the second grounding external terminal 5b may be connected to each other on both the first main surface 1b and the second main surface 1c. Good.

  The first grounding external terminal 5a is provided so as to cover the exposed part of the lead portion 3c to the first side face 1f, and the second grounding external terminal 5b is the second part of the lead portion 3d. It is provided so as to cover the exposed part to the side surface 1g.

  The first grounding internal electrode 5a and the second grounding external terminal 5b are connected to ground pads on a circuit board (not shown) on which the multilayer capacitor 10 is mounted, for example. Become.

  The multilayer capacitor 10 is provided between the first signal internal electrode 2a and the first ground internal electrode 3b in the vertical direction via the dielectric layer 1a in the multilayer body 1 and also for the second signal. A capacitance is formed between the internal electrode 2b and the first grounding internal electrode 3a.

  Further, the multilayer capacitor 10 includes a first signal internal electrode 2a and a first grounding internal electrode 3a, as shown in FIG. 4A, in a first plane with a predetermined interval therebetween. The first signal internal electrode 2a and the first grounding internal electrode 3a constitute a capacitor, which are arranged side by side so as to be parallel to the side surface 1f and the second side surface 1g. Further, as shown in FIG. 4B, the second signal internal electrode 2b and the second grounding internal electrode 3b are connected to each other with the first side surface 1f and the second side electrode at a predetermined interval in the same plane. The first signal internal electrode 2a and the first grounding internal electrode 3a constitute a capacitor. The first signal internal electrode 2a and the first grounding internal electrode 3a are parallel to the side surface 1g.

In the multilayer capacitor 10, since the respective end portions of the first grounding external terminal 5a and the second grounding external terminal 5b extend to the first main surface 1b, the respective end portions are, for example, It can be brought into contact with a case (housing) in which the circuit board is accommodated. That is, by contacting the ends of the first grounding external terminal 5a and the second grounding external terminal 5b with the case or the like, the multilayer capacitor 10 has the first grounding external terminal 5a and the second grounding terminal 5a. The end of the grounding external terminal 5b and the case can be set to the same potential. The case in which the circuit board is accommodated is grounded, and the multilayer capacitor 10 strengthens the ground via the first grounding external terminal 5a and the second grounding external terminal 5b. Can do.

  In the multilayer capacitor 10, the signal internal electrode 2 is arranged extending in the longitudinal direction (Y direction), and the signal internal electrode 2 constitutes a path for transmitting a signal.

  In the multilayer capacitor 10, as shown in FIGS. 3 and 4, the first grounding inner electrode 3a is disposed with the second signal inner electrode 2b interposed therebetween in the Z direction (lamination direction). The second grounding inner electrode 3b is disposed with the first signal inner electrode 2a interposed therebetween in the Z direction (stacking direction), and the lead portion 3c is disposed on the first side face 1f. In addition, the lead portion 3d extends to the second side surface 1g. The multilayer capacitor 10 has a first grounding external terminal 5a connected to the lead part 3c, a second grounding external terminal 5b connected to the lead part 3d, and the first grounding internal electrode 3a. The second grounding internal electrode 3b constitutes a path for passing a current to the ground.

  As described above, the multilayer capacitor 10 is configured such that a current flows to the ground through two paths including the first grounding internal electrode 3a and the second grounding internal electrode 3b. Therefore, in the multilayer capacitor 10, the first grounding internal electrode 3a and the second grounding internal electrode 3b are arranged via the dielectric layer 1a, and a set of first grounding internal electrodes 3a. In addition, the second grounding internal electrode 3b has a path through which currents to the ground flow in opposite directions, so that mutual inductance can be canceled out in the multilayer body 1. That is, in the multilayer capacitor 10, the lead portion 3c of the first grounding internal electrode 3a is led out to the first side surface 1f, and the lead portion 3d of the second grounding internal electrode 3ba is opposed to the first side surface 1f. The first grounding internal electrode 3a and the second grounding internal electrode 3b that are located in the stacking direction (Z direction) through the dielectric layer 1a have a current flowing through the second side surface 1g. Flow in opposite directions.

  Thus, in the multilayer capacitor 10, the first grounding internal electrode 3a is provided on the first side face 1f side in the stacking direction (Z direction), and the second grounding internal electrode 3b is Provided on the second side surface 1g side, the first grounding internal electrode 3a and the second grounding internal electrode 3b are arranged so as to face each other in a plan view from the stacking direction. Since the portion 3c and the lead-out portion 3d are arranged so as to face each other, currents directed to the first grounding external terminal 5a and secondly to the grounding external terminal 5b flow in opposite directions. Therefore, in the multilayer capacitor 10, current flows in the opposite direction between the first grounding inner electrode 3a and the second grounding inner conductor 3b in the stacking direction (Z direction). 10, since the current flowing through the ground is in the opposite direction, the directions of the generated magnetic fields are opposite to each other, and the equivalent series inductance (ESL) can be reduced due to the mutual induction effect.

  Therefore, the multilayer capacitor 10 can reduce the equivalent series inductance (ESL) by reducing the inductance of the multilayer capacitor 10 due to the magnetic field canceling action. Therefore, the multilayer capacitor 10 has a low ESL and can shift the resonance frequency to the high frequency region side, so that noise in the high frequency region can be reduced.

Further, the multilayer capacitor 10 is opposed to the first signal internal electrode 2a in the stacking direction (Z direction), with the second grounding internal electrode 3b facing up and down and overlapping in plan view from the stacking direction. Further, in the same plane, the first grounding internal electrodes 3a are arranged to face each other. For example, the noise component that enters the first signal internal electrode 2a is: It is possible to effectively escape to the ground via the second grounding internal electrode 3b positioned in the vertical direction and the first grounding internal electrode 3a positioned in the same plane.

  Similarly, in the multilayer capacitor 10, the first grounding internal electrode 3 a is vertically opposed to the second signal internal electrode 2 b in the stacking direction (Z direction) and viewed in plan from the stacking direction. Further, in the same plane, the second grounding internal electrodes 3b are arranged to face each other. For example, the noise component that enters the second signal internal electrode 2b is It is possible to effectively escape to the ground via the first grounding internal electrode 3a positioned in the vertical direction and the second grounding internal electrode 3b positioned in the same plane.

  For example, when the multilayer capacitor 10 is connected to a signal line or a power supply line of a circuit board (not shown), the first signal external terminal 4a is connected to the input end of the signal line or the power supply line, Further, the second signal external terminal 4b is connected to the output end of the signal line or the power supply line, and the first ground external terminal 5a and the second ground external terminal 5b are connected to the ground end (ground), respectively. Thus, high frequency noise in the signal line or the power supply line can be reduced. In this case, for example, the pattern of the signal line or the power supply line for which noise is desired to be reduced is cut, and the multilayer capacitor 10 has the first signal external terminal 4a and the second signal for the cut portion. External terminals 4b are connected to each other.

  Similarly, since the equivalent series inductance (ESL) of the multilayer capacitor 10 is reduced, for example, by connecting it to the drive power supply line or signal line of the CPU, the high frequency range of the drive power supply line or signal line can be reduced. Noise can be reduced. For example, the multilayer capacitor 10 is connected so that the first signal external terminal 4a and the second signal external terminal 4b are in parallel with the power supply line or signal line on the circuit board (the same potential in the circuit). In addition, the first grounding external terminal 5a and the second grounding external terminal 5b can be connected to the ground terminal (ground) to reduce high-frequency noise in the power supply line or signal line. In this case, for example, the pattern of the power supply line or signal line for which noise is to be reduced is not cut, and the multilayer capacitor 10 has the first signal external terminal 4a and the second signal external terminal 4b as the power supply. It is connected in parallel to the line or signal line.

  Further, in the multilayer capacitor 10, the first signal inner electrode 2a is drawn out only to one of the two opposite end faces (1d, 1e) of the multilayer body 1, for example, the first end face 1d, The two signal inner electrodes 2b may be led out only to one end face of the two opposite end faces (1d, 1e), for example, the second end face 1e. That is, the first signal internal electrode 2a has a gap with respect to the second side surface 1g, and extends in the Y direction so that the end portion in the Y direction is exposed to the first end surface 1d. The second signal internal electrode 2b has a gap with respect to the first side surface 1f, and extends in the Y direction so that the end portion in the Y direction is exposed to the second end surface 1e. You may arrange | position in the laminated body 1. FIG.

By adopting a configuration in which the first and second signal internal electrodes 2a and 2b are drawn out to only one end face (hereinafter referred to as the multilayer capacitor 100), the multilayer capacitor 100 is, for example, a circuit board (not shown). 1), the first signal external terminal 4a and the second signal external terminal 4b are connected to the signal line or the power supply line, and the first grounding external terminal is connected. By connecting the terminal 5a and the second grounding external terminal 5b to the ground end (ground), high frequency noise of the signal line or the power supply line can be reduced. In this case, for example, the pattern of the power supply line or signal line for which noise is to be reduced is not cut, and the first signal external terminal 4a and the second signal external terminal 4b are connected on the line pattern. Has been.

  Similarly, in the multilayer capacitor 100, for example, the first signal external terminal 4a and the second signal external terminal 4b are parallel to the power supply line or signal line on the circuit board (the same potential in the circuit). And the first grounding external terminal 5a and the second grounding external terminal 5b can be connected to a grounding end (ground) to reduce high-frequency noise in the power supply line or signal line. . In this case, the pattern of the power supply line or signal line for which noise is to be reduced is not cut, and the first signal external terminal 4a and the second signal external terminal 4b are connected in parallel to the power supply line. ing.

  Here, the attenuation characteristics of the multilayer capacitor 10 will be described below with reference to the drawings. Here, in order to make a comparison with the multilayer capacitor 10 of the first embodiment (hereinafter referred to as an example), a multilayer capacitor having an internal electrode structure as shown in FIG. First, a conventional multilayer capacitor will be described below.

  As shown in FIG. 8, the multilayer capacitor of the conventional example includes a multilayer body formed by stacking a plurality of dielectric layers 10a and a rectangular parallelepiped shape, and is disposed in the same plane in the multilayer body. Between the grounding internal electrode 30 having a lead portion 30aa to one side surface 10f and a lead portion 30ba to the other side surface 10g, and the grounding internal electrode 30 in the stacking direction, The signal internal electrode 20 drawn out to the opposing two side surfaces 10d and 10e and the first and second grounds disposed on the opposing side surfaces 10f and 10g of the laminate and connected to the grounding internal electrode 30, respectively. External signal terminals 50 a and 50 b and signal external terminals 40 a and 40 b connected to the signal internal electrode 20 and disposed on the two opposite side surfaces 10 d and 10 e of the laminate. As described above, the multilayer capacitor of the conventional example is different from the multilayer capacitor 10 of the embodiment in the configuration of the signal internal electrode 20 and the ground internal electrode 30.

  FIG. 7 shows a characteristic curve A representing the attenuation characteristics of the multilayer capacitor 10 of the example and a characteristic curve B representing the attenuation characteristics of the multilayer capacitor of the conventional example. For example, at 100 (MHz) on the horizontal axis of the graph of FIG. 7, the multilayer capacitor of the conventional example has an attenuation of about −66 (dB) in the characteristic curve B, whereas the multilayer capacitor 10 of the embodiment. Is the attenuation of the characteristic curve A of about -70 (dB). Thus, with respect to the attenuation characteristic at 100 (MHz), the multilayer capacitor 10 of the example has an attenuation of 4 (dB) improved compared to the multilayer capacitor of the conventional example. Note that the multilayer capacitors of the conventional example and the example have a size of 1.0 (mm) × 0.5 (mm) × height 0.5 (mm).

  Further, the ESL of the multilayer capacitors of the conventional example and the example is 60 (pH) in the conventional example, whereas the ESL of the example is 55 (pH), and the multilayer capacitor 10 of the example is the conventional example. Compared with the multilayer capacitor, ESL is reduced.

  Thus, since the multilayer capacitor 10 has a small ESL and the resonance frequency is shifted to the high frequency region side, noise in the high frequency region can be reduced.

  The capacitance of the multilayer capacitor of the conventional example is 4.7 (μF), and the equivalent series resistance (ESR) is 2.5 (mΩ). The capacitance of the multilayer capacitor of the example is 4.7 (μF), and the equivalent series resistance (ESR) is 2.4 (mΩ).

  Here, an example of a manufacturing method of the multilayer capacitor 10 shown in FIG. 1 will be described below.

  A plurality of first and second ceramic green sheets are prepared. The first ceramic green sheet is formed with the first signal internal electrode 2a and the first grounding internal electrode 3a, and the second ceramic green sheet is composed of the second signal internal electrode 2b and A second grounding internal electrode 3b is formed.

  The plurality of first ceramic green sheets are provided with the first signal internal electrode 2a and the first ground internal electrode in order to form the first signal internal electrode 2a and the first ground internal electrode 3a. The first signal internal electrode conductor paste layer is formed using the conductor paste for the first signal internal electrode 2a while arranging the pattern shape with 3a on the same plane at a predetermined interval. A first grounding internal electrode conductor paste layer is formed using the conductive paste for grounding internal electrode 3a. In the first ceramic green sheet, in order to obtain a large number of multilayer capacitors 10, the first signal internal electrode 2a and the first ground internal electrode 3a are combined in one ceramic green sheet. A plurality of them are formed as a set.

  Further, the plurality of second ceramic green sheets form the second signal internal electrode 2b and the second grounding internal electrode 3b to form the second signal internal electrode 2b and the second grounding internal electrode 3b. The pattern shape with the internal electrode 3b is arranged on the same plane with a predetermined interval, and the second signal internal electrode conductor paste layer is formed using the conductor paste for the second signal internal electrode 2b, A second grounding internal electrode conductor paste layer is formed using the conductor paste for the second grounding internal electrode 3b. In the second ceramic green sheet, in order to obtain a large number of multilayer capacitors 10, the second signal internal electrode 2b and the second grounding internal electrode 3b are combined in one ceramic green sheet. A plurality of them are formed as a set.

  The first signal internal electrode conductor paste layer and the first ground internal electrode conductor paste layer described above are formed in a predetermined pattern shape on the ceramic green sheet by using, for example, a screen printing method or the like. It is formed by printing at the same time. Similarly, the second signal internal electrode conductor paste and the second ground internal electrode conductor paste layer are formed by simultaneously printing each conductor paste in a predetermined pattern shape using a screen printing method or the like. .

  The first and second ceramic green sheets become the dielectric layer 1a, the first signal internal electrode conductor paste layer is the first signal internal electrode 2a, and the second signal internal electrode conductor paste layer is The second signal internal electrode 2b is formed, the first ground internal electrode conductor paste layer is the first ground internal electrode 3a, and the second ground internal electrode conductor paste layer is the second ground internal electrode. 3b.

As a material of the ceramic green sheet used as the dielectric layer 1a, for example, a dielectric ceramic such as BaTiO ₃ , CaTiO ₃ , SrTiO ₃ or CaZrO ₃ is mainly used. For example, a Mn compound, Fe compound, Cr compound, Co compound, or Ni compound may be added as the accessory component.

  The first and second ceramic green sheets are prepared by adding a suitable organic solvent or the like to the dielectric ceramic raw material powder and the organic binder, and mixing them with a doctor blade method. It is obtained by doing.

The conductive paste for the first and second signal internal electrodes 2a and 2b and the conductive paste for the first and second grounding internal electrodes 3a and 3b are formed into powders of the respective conductive materials (metal materials) described above. It is produced by adding and kneading an additive (dielectric material), a binder, a solvent, a dispersant and the like. The conductive material of each internal electrode includes, for example, a metal material such as nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), or gold (Au), or one or more of these metal materials. For example, alloy materials, such as an Ag-Pd alloy, are mentioned. The first and second signal internal electrodes 2a, 2b and the first and second ground internal electrodes 3a, 3b are preferably formed of the same metal material or alloy material.

  For example, a first ceramic green sheet, a second ceramic green sheet, a first ceramic green sheet, and a second ceramic green sheet are sequentially laminated in order to obtain the configuration shown in FIG. To do. That is, the first ceramic green sheets and the second ceramic green sheets are alternately stacked. And the ceramic green sheet which does not form an internal electrode is each laminated | stacked on the outermost layer of a lamination direction (Z direction), and it is set as the ceramic laminated body which has a structure as shown in FIG.

  The laminated body composed of the plurality of first and second ceramic green sheets thus laminated becomes a large-sized raw laminated body including a large number of raw laminated bodies 1 by pressing and integrating them. By cutting this large green laminate, a green laminate 1 that becomes the laminate 1 of the multilayer capacitor 10 as shown in FIG. 1 can be obtained. The large green laminate can be cut using, for example, a dicing blade.

  And the laminated body 1 can be obtained by baking the raw laminated body 1 at 800 (degreeC) -1300 (degreeC), for example. By this step, the plurality of first and second ceramic green sheets become the dielectric layer 1a, the first signal internal electrode conductor paste layer becomes the first signal internal electrode 2a, and the second signal internal electrode The conductor paste layer becomes the second signal internal electrode 2b, the first ground internal electrode conductor paste layer becomes the first ground internal electrode 3a, and the second ground internal electrode conductor paste layer becomes the second ground. The internal electrode 3b is used. Moreover, the laminated body 1 is rounded at the corners or sides by using a polishing means such as barrel polishing. The laminated body 1 becomes a thing which a corner | angular part or a side part cannot be easily chipped by rounding a corner | angular part or a side part.

  Next, for example, the signal external terminal 4 is formed by applying and baking a conductive paste for the signal terminal 4 to be the signal external terminal 4 on the first and second end faces 1d and 1e of the laminate 1. . The conductive paste for the signal external terminal 4 is prepared by adding a binder, a solvent, a dispersant, and the like to the metal material powder constituting the signal external terminal 4 and kneading.

  Further, for example, the grounding external terminal 5 is formed by applying a conductive paste for the grounding external terminal 5 to be the grounding external terminal 5 to the first and second side surfaces 1f, 1g of the laminate 1 and baking it. . The conductive paste for the grounding external terminal 5 is prepared by adding a binder, a solvent, a dispersant, etc. to a powder of a metal material constituting the grounding external terminal 5 and kneading.

  The conductive material of the signal external terminal 4 and the ground external terminal 5 is, for example, a metal material such as nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), or gold (Au), or An alloy material such as an Ag—Pd alloy including one or more of these metal materials.

  The signal external terminal 4 and the ground external terminal 5 are formed with a metal layer on the surface in order to protect the signal external terminal 4 and the ground external terminal 5 or to improve the mountability of the multilayer capacitor 10. It is preferable. The metal layer is formed using, for example, a plating method. The signal external terminal 4 and the ground external terminal 5 are, for example, one or a plurality of plating layers such as a nickel (Ni) plating layer, a copper (Cu) plating layer, a gold (Au) plating layer, or a tin (Sn) plating layer. Is preferably formed on the surface. The signal external terminal 4 and the ground external terminal 5 may be formed, for example, by forming a laminate of a Ni plating layer and a Sn plating layer on the surface.

Further, as a method of forming the signal external terminal 4 and the ground external terminal 5, a thin film forming method such as a vapor deposition method, a plating method, or a sputtering method may be used in addition to the method of baking the conductor paste.

  The first signal internal electrode 2a and the first ground internal electrode 3a are arranged on the same plane of the ceramic green sheet, for example, using a screen printing method with a predetermined interval therebetween. The pattern shape of the first grounding internal electrode 3a is simultaneously printed. However, a method for forming the first signal internal electrode 2a (second signal internal electrode 2b) and the first ground internal electrode 3a (second ground internal electrode 3b) on the ceramic green sheet. Is not limited to this.

  For example, the pattern shape to be the first signal internal electrode 2a and the pattern shape to be the first grounding internal electrode 3a are combined into one pattern shape, and the printing plate for screen printing is matched to the pattern shape. Is made. Then, using this printing plate for screen printing, one pattern shape including the pattern shape to be the first signal internal electrode 2a and the pattern shape to be the first grounding internal electrode 3a by the screen printing method is converted into ceramic. Print on a green sheet.

  Next, with respect to one pattern shape printed on the ceramic green sheet, the pattern shape of the first signal internal electrode 2a and the pattern shape of the first ground internal electrode 3a are obtained by using a laser processing method. The boundary is cut to electrically separate the pattern shape of the first signal internal electrode 2a from the pattern shape of the first grounding internal electrode 3a. Thus, the first signal internal electrode 2a and the first grounding internal electrode 3a can be provided on the same plane of the ceramic green sheet with a predetermined interval. The laser is, for example, a carbon dioxide gas laser or a YAG laser, and the wavelength of the laser is appropriately selected according to a predetermined interval. In particular, when a predetermined interval between two pattern shapes is narrow, by using a laser processing method, it is possible to more effectively cut the patterns of the opposing internal electrodes and electrically separate them.

  The present invention is not limited to the multilayer capacitor 10 of the first embodiment described above, and various modifications and improvements can be made without departing from the scope of the present invention. Hereinafter, other embodiments will be described. Note that, among the multilayer capacitors according to other embodiments, the same portions as those of the multilayer capacitor 10 according to the first embodiment are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

<Embodiment 2>
Hereinafter, multilayer capacitors 10A to 10D according to Embodiment 2 of the present invention will be described with reference to the drawings.

  In the multilayer capacitors 10A and 10B, as shown in FIG. 5, the first grounding internal electrode 3aa and the second grounding internal electrode 3ba have the electrode thicknesses of the first signal internal electrode 2aa and the second internal electrode 3aa. This is different from the signal internal electrode 2ba.

  In the multilayer capacitor 10A, the first grounding internal electrode 3aa and the second grounding internal electrode 3ba are thinner than the first signal internal electrode 2aa and the second signal internal electrode 2ba. ing. As described above, the first signal internal electrode 2aa and the second signal internal electrode 2ba have a thick electrode, and the first ground internal electrode 3aa in the stacking direction (Z direction). And the second signal internal electrode 2ba and the distance between the second ground electrode 3ba and the first signal internal electrode 2aa can be reduced. Therefore, since the inductance of the multilayer capacitor 10A is reduced, the equivalent series inductance (ESL) can be reduced.

  In this case, the first grounding internal electrode 3aa and the second grounding internal electrode 3ba have an electrode thickness of 0.5 (μm) to 1 (μm), for example, The signal internal electrode 2aa and the second signal internal electrode 2ba have an electrode thickness of, for example, 1 (μm) to 2 (μm).

  In the multilayer capacitor 10B, the first grounding internal electrode 3ab and the second grounding internal electrode 3bb have electrode thicknesses that are larger than those of the first signal internal electrode 2ab and the second signal internal electrode 2bb. It is thick. As described above, the first grounding internal electrode 3ab and the second grounding internal electrode 3bb have a large thickness, and the first grounding internal electrode 3ab in the stacking direction (Z direction). And the distance between the second signal internal electrode 2bb and the distance between the second ground electrode 3bb and the first signal internal electrode 2ab can be reduced.

  Therefore, since the impedance of the multilayer capacitor 10B is reduced, the equivalent series inductance (ESL) can be reduced. The first grounding internal electrode 3ab and the second grounding internal electrode 3bb are thick in thickness, and can reduce the equivalent series resistance (ESR). Since the resonance frequency inductance is reduced and the attenuation characteristics are improved, the noise reduction effect can be enhanced.

  In this case, the first grounding internal electrode 3ab and the second grounding internal electrode 3bb have an electrode thickness of, for example, 1 (μm) to 2 (μm), and are used for the first signal. The internal electrode 2ab and the second signal internal electrode 2bb have an electrode thickness of, for example, 0.5 (μm) to 1 (μm).

  Thus, in the multilayer capacitor 10A and the multilayer capacitor 10B, the first grounding electrode 3aa (3ab) and the second grounding electrode 3ba (3bb) are seen in a plan view from the stacking direction in the stacking direction. The first side surface 1f and the second side surface 1g are arranged in parallel and facing each other. In the multilayer capacitors 10A and 10B, the lead portion 3c of the first ground electrode 3aa (3ab) and the lead portion 3d of the second ground electrode 3ba (3bb) are arranged so that currents flow in opposite directions. Are arranged on the first side surface 1f and the second side surface 1g, respectively. As a result, in the multilayer capacitor 10A and the multilayer capacitor 10B, the currents flowing to the ground are in opposite directions, so that the directions of the generated magnetic fields are opposite to each other, and the equivalent series inductance (ESL) is reduced by the mutual induction effect. be able to.

  Further, the interval between the first grounding internal electrode 3aa and the second signal internal electrode 2ba and the interval between the second grounding electrode 3ba and the first signal internal electrode 2aa are narrow, and the first Since the distance between the grounding internal electrode 3ab and the second signal internal electrode 2bb and the distance between the second grounding electrode 3bb and the first signal internal electrode 2ab are reduced, the equivalent series inductance ( ESL) can be reduced.

  The multilayer capacitor 10A is not limited to the multilayer structure as shown in FIG. For example, as illustrated in FIG. 6A, the multilayer capacitor 10 </ b> C interchanges the arrangement positions of the first signal internal electrode 2 aa and the second signal internal electrode 2 ba with respect to the multilayer capacitor 10 </ b> A, Further, the arrangement positions of the first grounding internal electrode 3aa and the second grounding internal electrode 3ba may be interchanged.

Further, the multilayer capacitor 10B is not limited to the multilayer structure as shown in FIG. For example, as illustrated in FIG. 6B, the multilayer capacitor 10D switches the left and right positions of the first signal internal electrode 2ab and the second signal internal electrode 2bb with respect to the multilayer capacitor 10B. Moreover, the arrangement positions of the first grounding internal electrode 3ab and the second grounding internal electrode 3bb may be interchanged.

  The present invention is not particularly limited to Embodiment 1 and Embodiment 2 described above, and various changes and improvements can be made within the scope of the present invention.

DESCRIPTION OF SYMBOLS 1 Laminated body 1a Dielectric layer 1b 1st main surface 1c 2nd main surface 1d 1st end surface 1e 2nd end surface 1f 1st side surface 1g 2nd side surface 2 Signal internal electrode 2a For 1st signal Internal electrode 2b Second signal internal electrode 3 Ground internal electrode 3a First ground internal electrode 3b Second ground internal electrode 3c, 3d Lead portion 4 Signal external terminal 4a First signal external terminal 4b Second signal external terminal 5 Grounding external terminal 5a First grounding external terminal 5b Second grounding external terminal 10, 10A, 10B, 10C, 10D, 100 Multilayer capacitor

Claims (1)

A plurality of dielectric layers are stacked to connect the first and second main surfaces facing each other and the first and second main surfaces, and the first and second end surfaces facing each other and the first And a laminated body formed in a substantially rectangular parallelepiped shape having first and second side surfaces that face each other and connect between the second end faces;
At least a first signal internal electrode disposed between the dielectric layers in the laminate and drawn out to the first end face;
The first grounding internal electrode led out to the first side face and disposed opposite to the first signal internal electrode in the same plane as the first signal internal electrode through a predetermined interval When,
At least a second signal internal electrode led out to the second end face and disposed via the dielectric layer at a position overlapping the first grounding internal electrode in the stacking direction;
The first signal internal electrode is disposed at a position overlapping the first signal internal electrode in the stacking direction, and faces the second signal internal electrode through a predetermined interval in the same plane as the second signal internal electrode. A second grounding internal electrode disposed on the second side surface disposed;
At least a first signal external terminal connected to at least the first signal internal electrode and at least the second signal internal electrode disposed on the second end face, disposed on the first end face. A signal external terminal including a connected second signal external terminal;
A first grounding external terminal connected to the first grounding internal electrode disposed on the first side surface and a second grounding internal electrode disposed on the second side surface. A grounding external terminal including a second grounding external terminal ,
The first grounding internal electrode and the second grounding internal electrode have a thickness that is thicker than that of the first signal internal electrode and the second signal internal electrode. Capacitor.