WO2018043397A1 - Stacked capacitor - Google Patents

Stacked capacitor Download PDF

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Publication number
WO2018043397A1
WO2018043397A1 PCT/JP2017/030725 JP2017030725W WO2018043397A1 WO 2018043397 A1 WO2018043397 A1 WO 2018043397A1 JP 2017030725 W JP2017030725 W JP 2017030725W WO 2018043397 A1 WO2018043397 A1 WO 2018043397A1
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WIPO (PCT)
Prior art keywords
internal electrode
capacitor
signal internal
grounding
electrode
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PCT/JP2017/030725
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French (fr)
Japanese (ja)
Inventor
野木　貴文
畠中　英文
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京セラ株式会社
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Publication of WO2018043397A1 publication Critical patent/WO2018043397A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/38—Multiple capacitors, i.e. structural combinations of fixed capacitors

Definitions

  • the present disclosure relates to a multilayer capacitor used for a noise filter or the like with reduced equivalent series inductance (ESL: Equivalent Series Inductance) in a high frequency band.
  • ESL Equivalent Series Inductance
  • the multilayer capacitor of the present disclosure includes a multilayer body, a signal internal electrode, a grounding internal electrode, an external electrode, a grounding external terminal, a first capacitor unit, and a second capacitor unit.
  • the stacked body includes a pair of first and second surfaces, a pair of first and second side surfaces, a pair of first and second end surfaces on which a plurality of dielectric layers are stacked. It has a rectangular parallelepiped shape.
  • the signal internal electrode is a first signal led out to the first end face, which is disposed in the same plane parallel to the first surface and the second surface in the stacked body and spaced from each other. And a second signal internal electrode led out to the second end face.
  • the grounding internal electrode is disposed between the signal internal electrodes adjacent to each other in the stacking direction so as to face the first signal internal electrode and the second signal internal electrode in the stacking direction, and It is pulled out to the side surface and the second side surface.
  • An external electrode is disposed on the first end surface of the laminate, and is disposed on the first external electrode connected to the first signal internal electrode and the second end surface, and the second signal surface.
  • a second external electrode connected to the internal electrode is included.
  • the grounding external terminal is disposed on the first side surface of the laminate, and is disposed on the first grounding external terminal connected to the grounding internal electrode and the second side surface, and the grounding internal electrode And a second grounding external terminal connected to the.
  • the first capacitor portions are arranged according to the stacking direction, and a plurality of the first signal internal electrodes and a plurality of the ground internal electrodes are alternately stacked with the dielectric layer interposed therebetween.
  • the second capacitor sections are arranged according to the stacking direction, and a plurality of the second signal internal electrodes and a plurality of the ground internal electrodes are alternately stacked with the dielectric layer interposed therebetween.
  • the first capacitor unit has a smaller capacity than the second capacitor unit.
  • FIG. 1 is a schematic perspective view showing a multilayer capacitor according to an embodiment.
  • FIG. 2 is a cross-sectional view of the multilayer capacitor shown in FIG. 1 cut along line AA.
  • FIG. 2 is a cross-sectional view of the multilayer capacitor shown in FIG. 1 cut along line BB.
  • FIG. 2 is a schematic exploded perspective view of the multilayer body of the multilayer capacitor shown in FIG. 1.
  • FIG. 2 is a cross-sectional view showing a first signal internal electrode and a second signal internal electrode of a first capacitor section and a second capacitor section in a direction orthogonal to the stacking direction of the multilayer capacitor shown in FIG. 1. .
  • FIG. 1 is a schematic perspective view showing a multilayer capacitor according to an embodiment.
  • FIG. 2 is a cross-sectional view of the multilayer capacitor shown in FIG. 1 cut along line AA.
  • FIG. 2 is a cross-sectional view of the multilayer capacitor shown in FIG. 1 cut along line BB.
  • FIG. 2
  • FIG. 2 is a cross-sectional view showing a grounding internal electrode of a first capacitor part and a second capacitor part in a direction orthogonal to the lamination direction of the multilayer capacitor shown in FIG. 1.
  • FIG. 7 is a cross-sectional view taken along a line corresponding to the line AA in FIG. 1 of another embodiment of the multilayer capacitor shown in FIG.
  • FIG. 7 is a cross-sectional view taken along a line corresponding to the line BB in FIG. 1 of another embodiment of the multilayer capacitor shown in FIG.
  • FIG. 6 is a schematic exploded perspective view of the multilayer capacitor multilayer body shown in FIGS. 5A and 5B. It is sectional drawing of the multilayer capacitor
  • a multilayer capacitor is used in an LSI power supply circuit such as a CPU in order to reduce noise from entering the LSI from a power supply line or other device, and to reduce malfunction due to LSI noise. It is done.
  • the multilayer capacitor needs to further reduce the equivalent series inductance (ESL) in order to reduce noise in a high frequency band such as a signal line or a power supply line.
  • ESL equivalent series inductance
  • the multilayer capacitor of the present disclosure two capacitor parts are arranged side by side in a direction perpendicular to the stacking direction of the multilayer body.
  • the multilayer capacitor of the present disclosure can reduce the equivalent series inductance (ESL) and the equivalent series resistance (ESR).
  • ESL equivalent series inductance
  • ESR equivalent series resistance
  • the multilayer capacitor 10 defines an orthogonal coordinate system XYZ, and uses the term “upper surface” or “lower surface” with the positive side in the Z direction as the upper side.
  • the overlapping description is abbreviate
  • the multilayer capacitor 10 includes a multilayer body 1, a signal internal electrode 2 (first signal internal electrode 2a and second signal internal electrode 2b), and a ground internal electrode. 3, external electrode 4 (first external electrode 4 a and second external electrode 4 b), ground external terminal 5 (first ground external terminal 5 a and second ground external terminal 5 b), 1 capacitor section 6a and second capacitor section 6b.
  • the first capacitor section 6a is formed of a plurality of first signal internal electrodes 2a and a plurality of grounding internal electrodes 3 arranged in the stacking direction.
  • the second capacitor portion 6b is formed of a plurality of second signal internal electrodes 2b and a plurality of grounding internal electrodes 3 arranged in the stacking direction.
  • the multilayer capacitor 10 includes a first capacitor unit 6a and a second capacitor unit 6b, and is formed so that the first capacitor unit 6a and the second capacitor unit 6b have different capacities.
  • the laminated body 1 is a sintered body obtained by laminating and firing a plurality of ceramic green sheets to be the dielectric layer 1g, in which a plurality of dielectric layers 1g are laminated to form a rectangular parallelepiped shape.
  • the laminated body 1 is formed in a rectangular parallelepiped shape, and has a pair of surfaces, a pair of end surfaces, and a pair of side surfaces.
  • the pair of surfaces are a first surface 1a and a second surface 1b that face each other.
  • the pair of end surfaces are a first end surface 1c and a second end surface 1d that are orthogonal to the first surface 1a and the second surface 1b and face each other.
  • the pair of side surfaces are a first side surface 1e and a second side surface 1f that are orthogonal to the first end surface 1c and the second end surface 1d and face each other.
  • the laminated body 1 has a rectangular plane as shown in FIGS. 4A and 4B, which is a cross section (XY plane) orthogonal to the laminating direction (Z direction) of the dielectric layer 1 g.
  • the multilayer capacitor 10 has a length in the longitudinal direction (X direction) of, for example, 0.6 (mm) to 2.2 (mm), and a length in the short side direction (Y direction) of, for example, 0. .3 (mm) to 1.2 (mm), and the length in the height direction (Z direction) is, for example, 0.3 (mm) to 1.5 (mm).
  • the multilayer capacitor 10 includes a first capacitor portion 6 a and a second capacitor portion 6 b arranged in the longitudinal direction (X direction) in the multilayer body 1.
  • the capacitor is formed in the height direction (Z direction).
  • the length in the height direction (Z direction) may be longer than the length in the short direction (Y direction) depending on the capacitance of the first capacitor portion 6a and the second capacitor portion 6b.
  • the multilayer capacitor 10 has a length in the longitudinal direction (X direction) of 1.15 (mm), a length in the short direction (Y direction) of 0.65 (mm), and a height direction (Z direction). This is a so-called high-back type capacitor in which the length is 0, 8 (mm) longer than the length in the short direction (Y direction).
  • the dielectric layer 1g is rectangular in a plan view from the stacking direction (Z direction), and the thickness per layer is, for example, 0.5 ( ⁇ m) to 3 ( ⁇ m).
  • the laminated body 1 for example, a plurality of dielectric layers 1g of 10 (layers) to 1000 (layers) are laminated in the Z direction.
  • the dielectric layer 1g is, for example, barium titanate (BaTiO 3 ), calcium titanate (CaTiO 3 ), strontium titanate (SrTiO 3 ), or calcium zirconate (CaZrO 3 ).
  • the dielectric layer 1g may use barium titanate as a ferroelectric material having a high dielectric constant, particularly from the viewpoint of a high dielectric constant.
  • the signal internal electrode 2 includes a first signal internal electrode 2a and a second signal internal electrode 2b. As shown in FIG. 4A, each of the first signal internal electrode 2a and the second signal internal electrode 2b has a quadrangular shape, and is parallel to the first surface and the second surface in the multilayer body 1. Are arranged side by side in the same plane. That is, as shown in FIG. 4A, the first signal internal electrode 2a and the second signal internal electrode 2b are arranged side by side in the same plane in the direction orthogonal to the stacking direction. The first signal internal electrode 2a is drawn out to the first end face 1c. The second signal internal electrode 2b is drawn out to the second end face 1d.
  • the first signal internal electrode 2a has a length X1 in the longitudinal direction (X direction) of, for example, 125 ( ⁇ m) to 225 ( ⁇ m).
  • the second signal internal electrode 2b has a length X2 in the longitudinal direction (X direction) of, for example, 850 ( ⁇ m) to 950 ( ⁇ m).
  • the length X1 and the length X2 are appropriately set according to the capacitances of the first capacitor unit 6a and the second capacitor unit 6b.
  • the distance between the first signal internal electrode 2a and the second signal internal electrode 2b is, for example, 30 ( ⁇ m) to 100 ( ⁇ m).
  • the signal internal electrode 2 has a length X1 in the longitudinal direction (X direction) of the first signal internal electrode 2a that is equal to the longitudinal direction (X direction) of the second signal internal electrode 2b. ) Is smaller than the length X2.
  • the area of the first signal internal electrode 2 a facing the ground internal electrode 3 is smaller than the area of the second signal internal electrode 2 b facing the ground internal electrode 3. ing. That is, in plan view from the stacking direction, the area of the first signal internal electrode 2a is smaller than the area of the second signal internal electrode 2b.
  • the grounding internal electrode 3 has a quadrangular shape, and between the signal internal electrodes 2 adjacent in the stacking direction, the first signal internal electrode 2a and the second signal internal electrode 2 in the stacking direction. It is arranged to face the internal electrode 2b. As shown in FIG. 4B, the grounding internal electrode 3 has a lead portion 3a leading to the first side face 1e and a lead portion 3b leading to the second side face 1f. In addition, as shown in FIG. 4B, the grounding internal electrode 3 has the lead-out portion 3a exposed at the first side face 1e and the lead-out portion 3b exposed at the second side face 1f.
  • the conductive material of the signal internal electrode 2 and the ground internal electrode 3 is a metal material such as nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), or gold (Au).
  • the conductive material of the signal internal electrode 2 and the ground internal electrode 3 is an alloy material such as an Ag—Pd alloy including at least one of these metal materials.
  • the same metal material or alloy material may be used for the conductive material of the signal internal electrode 2 and the ground internal electrode 3.
  • the signal internal electrode 2 and the ground internal electrode 3 have a thickness of, for example, 0.5 ( ⁇ m) to 2 ( ⁇ m).
  • the external electrode 4 includes a first external electrode 4a and a second external electrode 4b as shown in FIG.
  • the first external electrode 4a is disposed on the first end face 1c of the multilayer body 1 and connected to the first signal internal electrode 2a.
  • the second external electrode 4b is disposed on the second end face 1d and connected to the second signal internal electrode 2b.
  • the first external electrode 4a is provided so as to cover the entire first end face 1c
  • the second external electrode 4b is provided so as to cover the entire second end face 1d. ing.
  • the grounding external terminal 5 includes a first grounding external terminal 5a and a second grounding external terminal 5b.
  • the first grounding external terminal 5 a is disposed on the first side surface 1 e of the multilayer body 1 and is connected to the lead portion 3 a of the grounding internal electrode 3.
  • the second ground external terminal 5 b is disposed on the second side surface 1 f of the multilayer body 1 and is connected to the lead portion 3 b of the ground internal electrode 3.
  • the first ground external terminal 5a is provided so as to extend from the first side face 1e to the first face 1a and the second face 1b, respectively.
  • the second ground external terminal 5b is provided so as to extend from the second side face 1f to the first face 1a and the second face 1b, respectively.
  • the first external electrode 4a and the second external electrode 4b are connected to, for example, a signal line or a current line on the mounting substrate 8 on which the multilayer capacitor 10 is mounted.
  • the first grounding external terminal 5a and the second grounding external terminal 5b are connected to, for example, a ground line on the mounting substrate 8 on which the multilayer capacitor 10 is mounted.
  • the external electrode 4 and the grounding external terminal 5 include a base electrode and a plating layer.
  • the base electrode is provided on the surface of the multilayer body 1 and is electrically connected to the first signal internal electrode 2a exposed on the first end face 1c and the second signal internal electrode 2b exposed on the second end face 1d. It is connected.
  • the base electrode is provided on the surface of the multilayer body 1 and is electrically connected to the grounding internal electrode 3 exposed on the first side face 1e and the second side face 1f.
  • the plating layer is provided on the surface of the base electrode so as to cover the base electrode formed on the surface of the multilayer body 1.
  • the plating layer is provided so as to cover the base electrode in order to protect the base electrode.
  • the conductive material of the base electrode is, for example, a metal material such as nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), or gold (Au).
  • the conductive material of the base electrode is an alloy material such as an Ag—Pd alloy including one or more of these metal materials.
  • the plating layer is, for example, a nickel (Ni) plating layer, a copper (Cu) plating layer, a gold (Au) plating layer, a tin (Sn) plating layer, or the like.
  • the plating layer is provided on the surface of the base electrode using, for example, an electrolytic plating method.
  • the plating layer may be formed of a single plating layer or a plurality of plating layers on the surface of the base electrode.
  • the plating layer is a two-layer laminate of a first plating layer and a second plating layer formed on the surface of the first plating layer.
  • the plating layer can be formed as a two-layered structure of a Ni plating layer and a Sn plating layer by providing a Ni plating layer on the surface of the base electrode and further providing a Sn plating layer on the surface of the Ni plating layer.
  • the first signal internal electrode 2a and the second signal internal electrode 2b are arranged side by side along the longitudinal direction (X direction).
  • the first capacitor portion 6a is formed by a plurality of first signal internal electrodes 2a and a plurality of ground internal electrodes 3 facing the first signal internal electrodes 2a arranged in the stacking direction.
  • the second capacitor portion 6b is formed of a plurality of second signal internal electrodes 2b arranged in the stacking direction and a plurality of grounding internal electrodes 3 facing the second signal internal electrodes 2b.
  • the grounding internal electrode 3 is provided opposite to the signal internal electrode 2 and is used in common for the first capacitor portion 6a and the second capacitor portion 6b.
  • the first capacitor portion 6a includes the first signal internal electrode 2a, the dielectric layer 1g, and the ground internal electrode 3, and includes the first signal internal electrode 6a.
  • a dielectric layer 1g is disposed between the electrode 2a and the grounding internal electrode 3.
  • the first capacitor portion 6a is arranged from the first surface 1a side to the second surface 1b side so that the first signal internal electrode 2a and the ground internal electrode 3 face each other with the dielectric layer 1g therebetween. It is arranged alternately.
  • the second capacitor portion 6b includes a second signal internal electrode 2b, a dielectric layer 1g, and a grounding internal electrode 3, and the second signal internal electrode 2b. 1 g of dielectric layer is disposed between the internal electrode 3 and the grounding internal electrode 3.
  • the second capacitor portion 6b extends from the first surface 1a side to the second surface 1b side so that the second signal internal electrode 2b and the ground internal electrode 3 face each other with the dielectric layer 1g therebetween. It is arranged alternately.
  • the first capacitor portion 6 a forms a capacitance with the first signal internal electrode 2 a and the ground internal electrode 3 in the stacking direction in the multilayer body 1
  • the second capacitor portion 6b forms a capacitance with the second signal internal electrode 2b and the ground internal electrode 3.
  • the multilayer capacitor 10 is provided with two capacitor parts, the first capacitor part 6a and the second capacitor part 6b, in the multilayer body 1.
  • the first capacitor portion 6a and the second capacitor portion 6b have different capacities.
  • the first signal internal electrode 2a has a smaller area facing the grounding internal electrode 3 than the second signal internal electrode 2b.
  • the capacitance of the first capacitor portion 6a is smaller than the capacitance of the second capacitor portion 6b.
  • the first capacitor portion 6a includes a first signal internal electrode 2a and a grounding internal electrode 3 from the first surface 1a toward the second surface 1b.
  • the dielectric layers 1g are alternately stacked in this order.
  • the second capacitor portion 6b includes the second signal internal electrode 2b and the ground internal electrode 3 from the first surface 1a side to the second surface 1b side. Are alternately stacked in this order across the dielectric layer 1g.
  • the multilayer capacitor 10 is not limited to such an arrangement of the signal internal electrode 2 and the ground internal electrode 3. In the multilayer capacitor 10, the number of stacked layers of the signal internal electrode 2 and the ground internal electrode 3 is appropriately designed according to characteristics and the like.
  • the grounding internal electrode 3 is disposed on the outermost layer on the first surface 1a side and the second surface 1b side in the stacking direction. be able to. That is, as shown in FIGS. 5A, 5B, and 6, the multilayer capacitor 10A includes the grounding internal electrode 3 and the signal internal electrode 2 from the first surface 1a side to the second surface 1b side. By alternately arranging in this order, the grounding internal electrodes 3 can be arranged on the outermost layer on the second surface 1b side.
  • the multilayer capacitor 10A when the grounding internal electrode 3 is connected to the ground line, the multilayer capacitor 10A includes the first capacitor portion 6a and the second capacitor portion 6b on the first surface 1a side and The grounding internal electrode 3 can be disposed on the outermost layer on the second surface 1b side. That is, the multilayer capacitor 10A is shielded by arranging the grounding internal electrode 3 connected to the ground line on the first surface 1a side and the second surface 1b side, thereby blocking the electric field from the outside. Can be improved.
  • the multilayer capacitor 10A is connected to the ground line on the outermost layer on the first surface 1a side and the second surface 1b side of the first capacitor unit 6a and the second capacitor unit 6b.
  • the shielding property is improved.
  • the multilayer capacitor 10A can reduce the influence of disturbance noise such as noise exceeding input tolerance or discharge due to static electricity.
  • the capacitance of the first capacitor portion 6a is 1 ( ⁇ F), and the capacitance of the second capacitor portion 6b is 15 ( ⁇ F).
  • the capacitance of the first capacitor portion 6a is set within a range of 1 ( ⁇ F) to 3 ( ⁇ F), for example, and the capacitance of the second capacitor portion 6b is, for example, 10 ( ⁇ F) to 15 ( ⁇ F).
  • the multilayer capacitor 10B is a cross-sectional view taken along the line AA of the multilayer capacitor 10 shown in FIG. 1, and includes two capacitor portions 6A and a capacitor in the multilayer body 1. It has a part 6B.
  • the first capacitor portion 6a and the second capacitor portion 6b are arranged in the X direction.
  • the capacitor part 6A and the capacitor part 6B are arranged in the Z direction.
  • the multilayer capacitor 10 has the capacitor portion 6A arranged as the first capacitor portion 6a in the stacking direction in the multilayer body 1, and the capacitor portion 6B is arranged in the stacking direction in the multilayer body 1 as the second capacitor.
  • the multilayer capacitor 10B when the capacitance of the capacitor unit 6A is 1 ( ⁇ F) and the capacitance of the capacitor unit 6B is 15 ( ⁇ F), the multilayer capacitor 10 has the capacitance of the first capacitor unit 6a. Is 1 ( ⁇ F), and the capacitance of the second capacitor portion 6b is 15 ( ⁇ F).
  • the first capacitor portion 6a and the second capacitor portion 6b are arranged in a direction perpendicular to the lamination direction of the multilayer body 1, and the capacitor portion 6A and the capacitor portion are arranged like the multilayer capacitor 10B. It is not necessary to provide an interval between the capacitor 6B and the length in the height direction (Z direction) can be made smaller than that of the multilayer capacitor 10B.
  • FIG. 8A and 8B are cross-sectional views when the multilayer capacitor 10 and the multilayer capacitor 10B are mounted on the mounting substrate 8.
  • FIG. 8B L0 is an inductor component of the capacitor unit 6A having a small capacity
  • L1 is an inductor component of the capacitor unit 6B having a large capacity
  • L2 is an inductor component of the first capacitor unit 6a
  • L3 is an inductor component of the second capacitor unit 6b.
  • the capacitor portion 6A has a small distance from the surface of the mounting substrate 8 (distance in the Z direction).
  • the physical length (loop length) of the current path flowing from the terminal 8a1 to the GND terminal 8b of the mounting substrate 8 is reduced, and the inductor component L0 is reduced.
  • the capacitor section 6B has a large distance (distance in the Z direction) from the surface of the mounting board 8, the physical length (loop) of the current path flowing from the input terminal 8a2 of the mounting board 8 to the GND terminal 8b of the mounting board 8 Length) becomes longer, and the inductor component L1 becomes larger.
  • the first capacitor portion 6a and the second capacitor portion 6b are separated from the surface of the mounting substrate 8 (in the Z direction). Distance) is the same.
  • the physical length (loop length) of the current path flowing from the input terminal 8a1 of the mounting substrate 8 to the GND terminal 8b of the mounting substrate 8 is shortened.
  • the physical length (loop length) of the current path flowing from the input terminal 8a2 of the mounting board 8 to the GND terminal 8b of the mounting board 8 is shortened.
  • the first capacitor unit 6a and the second capacitor unit 6b have the shortest physical length (loop length) as well as the physical length (loop length) of the current path, and the multilayer capacitor 10 includes the first capacitor
  • the inductor component L2 of the part 6a and the inductor component L3 of the second capacitor part 6b can be reduced.
  • the inductor component L2 of the first capacitor portion 6a is substantially the same as the inductor component L0 of the capacitor portion 6A of the multilayer capacitor 10B.
  • the inductor component L3 of the second capacitor unit 6b is smaller than the inductor component L1 of the capacitor unit 6B of the multilayer capacitor 10B, and the inductor component is smaller than that of the multilayer capacitor 10B. Therefore, in the multilayer capacitor 10, the inductor component L3 becomes small, and the resonance frequency can be shifted to the high frequency side.
  • the first capacitor unit 6a and the second capacitor unit 6b are provided in the multilayer body 1, and the capacitance of the first capacitor unit 6a is smaller than the capacitance of the second capacitor unit 6b. It has become.
  • the first capacitor section 6a has a capacitance formed in the stacking direction, and the number of stacks of the first signal internal electrode 2a and the grounding internal electrode 3 increases.
  • the multilayer capacitor 10 has an equivalent series resistance (ESR). Becomes smaller. Therefore, the multilayer capacitor 10 has different capacities of the first capacitor unit 6a and the second capacitor unit 6b, and has two resonance frequencies having different frequencies as shown in FIG. Overall smaller.
  • the multilayer capacitor 10 can improve the impedance characteristic in the high frequency band and can widen the band in which noise is reduced in the high frequency band.
  • the multilayer capacitor 10 is provided with the first capacitor portion 6a and the second capacitor portion 6b having different capacities, thereby reducing the equivalent series inductance (ESL), shifting the resonance frequency to the high frequency band side, and equivalently.
  • ESL equivalent series inductance
  • the series resistance (ESR) is reduced, and the impedance at the resonance frequency can be reduced.
  • the lowest point of the resonance frequency on the high frequency side is located on the lower side, the impedance is reduced, and noise in the high frequency band can be reduced.
  • FIG. 9 is a graph showing impedance characteristics in the frequency band of the multilayer capacitor 10 and the multilayer capacitor 10B.
  • A shows the impedance characteristic of the multilayer capacitor 10
  • B shows the impedance characteristic of the multilayer capacitor 10B. .
  • the capacity of the first capacitor section 6a is 1 ( ⁇ F), and the capacity of the second capacitor section 6b is 15 ( ⁇ F).
  • the capacitance of the capacitor unit 6A is 1 ( ⁇ F), and the capacitance of the capacitor unit 6B is 15 ( ⁇ F).
  • Other configurations are the same.
  • the multilayer capacitor 10 and the multilayer capacitor 10B have a length in the longitudinal direction (X direction) of 1.15 (mm) and a length in the lateral direction (Y direction) of 0.65 (mm). The length in the height direction (Z direction) is 0.8 (mm).
  • the multilayer capacitor 10 has a small equivalent series inductance (ESL), a resonance frequency shifts to the high frequency band side, a small equivalent series resistance (ESR), and a small impedance at the resonance frequency.
  • ESL small equivalent series inductance
  • ESR small equivalent series resistance
  • impedance in the high frequency band is smaller than that of the multilayer capacitor 10B.
  • the first signal internal electrode 2a and the second signal internal electrode 2b are arranged with a space therebetween.
  • no electrode is provided between the first signal internal electrode 2a and the second signal internal electrode 2b.
  • the multilayer capacitor 10 has a different shrinkage ratio between a portion having an electrode and a portion having no electrode at the time of firing, and the space between the first signal internal electrode 2a and the second signal internal electrode 2b is further contracted. Therefore, in the multilayer capacitor 10, the dent 7 is formed on the surface of the multilayer body 1 at a position corresponding to between the first capacitor portion 6a and the second capacitor portion 6b.
  • the first surface 1a or the second surface 1b has a recessed portion corresponding to the region between the adjacent first signal internal electrode 2a and the second signal internal electrode 2b.
  • the multilayer capacitor 10 has a recess 7 formed over the first surface 1 a, the first side surface 1 e, the second surface 1 b, and the second side surface 1 f of the multilayer body 1.
  • the dent 7 is easily formed remarkably on the first surface 1a or the second surface 1b.
  • the multilayer capacitor 10 determines whether it is connected to the electrode 4b. For example, as shown in FIG. 2A, when the multilayer capacitor 10 is viewed from the side (Y direction) perpendicular to the first side surface 1 e (second side surface 1 f), the multilayer capacitor 10 has a recess 7. By being located on the first external electrode 4a side, the first capacitor portion 6a is arranged on the positive side in the X direction. That is, in the multilayer capacitor 10, it can be seen that the first signal internal electrode 2a is connected to the first external electrode 4a. In addition, when the multilayer capacitor 10 is viewed in plan from the direction (X direction) perpendicular to the first surface 1a (second surface 1b), the first signal internal electrode 2a is connected to the first external electrode 4a. You can see that it is connected to.
  • the multilayer capacitor 10 includes the first capacitor portion 6a provided on the first external electrode 4a side, the second capacitor portion 6b provided on the second external electrode 4b side, and the recess 7 The direction becomes clear. Thereby, the multilayer capacitor 10 can be mounted in a desired direction when mounted on the mounting substrate 8.
  • the direction of the multilayer capacitor 10 is clarified by the recess 7 and can be inserted in a desired direction when being inserted into the pocket of the taping carrier tape.
  • the first ceramic green sheet is formed with a first signal internal electrode 2a and a second signal internal electrode 2b.
  • the second ceramic green sheet has a grounding internal electrode 3 formed thereon.
  • the plurality of first ceramic green sheets are formed by using the conductor paste for the signal internal electrode 2 on the ceramic green sheet.
  • a plurality of signal internal electrodes 2 are formed in one ceramic green sheet in order to obtain a large number of multilayer capacitors 10.
  • the plurality of second ceramic green sheets are formed on the ceramic green sheet by using the conductive paste layer for the grounding internal electrode 3 with the conductive paste layer for the grounding internal electrode 3.
  • a plurality of grounding internal electrodes 3 are formed in one ceramic green sheet in order to obtain a large number of multilayer capacitors 10.
  • the conductor paste layers of the signal internal electrode 2 and the ground internal electrode 3 described above are formed on the ceramic green sheet, for example, by using a screen printing method or the like with each conductor paste in a predetermined pattern shape.
  • the first and second ceramic green sheets serve as the dielectric layer 1g, and the conductor paste layer of the signal internal electrode 2 serves as the first signal internal electrode 2a and the second signal internal electrode 2b.
  • the conductive paste layer of the internal electrode 3 becomes the ground internal electrode 3.
  • the material of the ceramic green sheet is mainly composed of dielectric ceramics such as BaTiO 3 , CaTiO 3 , SrTiO 3 or CaZrO 3 .
  • dielectric ceramics such as BaTiO 3 , CaTiO 3 , SrTiO 3 or CaZrO 3 .
  • a material to which a Mn compound, Fe compound, Cr compound, Co compound, Ni compound or the like is added may be used.
  • the first and second ceramic green sheets are produced by adding a suitable organic solvent to the dielectric ceramic raw material powder and the organic binder and mixing them, and using a doctor blade method or the like. Mold.
  • the conductor paste for the signal internal electrode 2 and the ground internal electrode 3 is made by adding an additive (dielectric material), a binder, a solvent, a dispersing agent, etc. to the above-mentioned powder of the conductive material (metal material) of each internal electrode. And kneading.
  • the conductive material of the signal internal electrode 2 and the ground internal electrode 3 is, for example, a metal material such as nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), or gold (Au).
  • the signal internal electrode 2 and the ground internal electrode 3 are alloy materials including one or more of these metal materials, such as an Ag—Pd alloy.
  • the signal internal electrode 2 and the ground internal electrode 3 may use the same metal material or alloy material.
  • first and second ceramic green sheets are sequentially laminated as shown in FIG.
  • the ceramic green sheet in which an internal electrode is not formed is each laminated
  • the laminated body thus laminated becomes a large green laminated body including a large number of raw laminated bodies by pressing and integrating.
  • a green laminate that becomes the laminate 1 of the multilayer capacitor 10 as shown in FIG. 1 can be obtained.
  • the large green laminate can be cut using, for example, a dicing blade.
  • the laminate 1 is obtained by firing the raw laminate at, for example, 800 (° C.) to 1300 (° C.).
  • the plurality of first and second ceramic green sheets become the dielectric layer 1g
  • the conductor paste layer of the signal internal electrode 2 becomes the first signal internal electrode 2a and the second signal internal electrode 2b
  • the conductive paste layer of the grounding internal electrode 3 becomes the grounding internal electrode 3.
  • the corners or sides are not easily chipped by rounding the corners or sides using a polishing means such as barrel polishing.
  • the first external electrode 4a and the second external electrode 4b are formed on the first end surface 1c and the second end surface 1d of the multilayer body 1 for the first external electrode 4a and the second external electrode 4b, for example.
  • the conductive paste is applied and baked.
  • the conductive paste for the first external electrode 4a and the second external electrode 4b is obtained by adding a binder, a solvent, a dispersant and the like to the powder of the metal material of the first external electrode 4a and the second external electrode 4b. In addition, it is produced by kneading.
  • first grounding external terminal 5a and the second grounding external terminal 5b are formed by using, for example, a roller transfer method to apply the conductive paste for the grounding external terminal 5 to the first side surface 1e and the second side surface 2e. It is formed on the side surface 1f.
  • the conductive paste is transferred to the first side face 1e and the second side face 1f by using a roller transfer method to transfer the conductive paste for the grounding external terminal 5 to the first side face 1e. And provided on the second side surface 1f and extending to the first surface 1a and the second surface 1b.
  • the external electrode 4 and the grounding external terminal 5 are formed with a metal layer on the surface in order to protect the surface or improve the mountability of the multilayer capacitor 10 with the mounting substrate.
  • the metal layer is formed using, for example, a plating method.
  • the metal layer is, for example, a nickel (Ni) plating layer, a copper (Cu) plating layer, a gold (Au) plating layer, a tin (Sn) plating layer, or the like.
  • the metal layer can be formed by forming a single plating layer or a plurality of plating layers on the surfaces of the external electrode 4 and the grounding external terminal 5.
  • the external electrode 4 and the grounding external terminal 5 may be a laminate in which the metal layer is a nickel plating layer and a tin plating layer.
  • the external electrode 4 and the grounding external terminal 5 may use a thin film forming method such as a vapor deposition method, a plating method, or a sputtering method in addition to the method of baking the conductor paste.
  • the present disclosure is not limited to the multilayer capacitor of the above-described embodiment, and various modifications can be made without departing from the gist of the present disclosure.

Abstract

A stacked capacitor according to the present invention is provided with: a laminated body in which a plurality of dielectric layers are stacked; a first signal internal electrode led out to a first end face and a second signal internal electrode led out to a second end face, said first and second signal internal electrodes being arranged side by side within the same surface in the laminated body; a grounding internal electrode arranged so as to face the first signal internal electrode and the second signal internal electrode; a first capacitor unit in which a plurality of the first signal internal electrodes and a plurality of the grounding internal electrodes arrayed in the lamination direction are stacked with the dielectric layers interposed therebetween; and a second capacitor unit in which a plurality of the second signal internal electrodes and the plurality of grounding internal electrodes arrayed in the lamination direction are stacked with the dielectric layers interposed therebetween, wherein the first capacitor unit has a smaller capacitance than the second capacitor unit.

Description

積層型コンデンサMultilayer capacitor
　本開示は、高周波数帯域での等価直列インダクタンス（ＥＳＬ：Equivalent Series Inductance）を低減した、ノイズフィルタ等に用いられる積層型コンデンサに関する。 The present disclosure relates to a multilayer capacitor used for a noise filter or the like with reduced equivalent series inductance (ESL: Equivalent Series Inductance) in a high frequency band.
　近年、情報処理機器または通信機器等はデジタル化されており、これらの機器は情報処理能力の高速化に伴って取り扱われるデジタル信号の高周波数化が進んでいる。したがって、これらの機器は、発生するノイズも高周波数帯域で増大する傾向にあり、ノイズ対策のために、例えば、積層型コンデンサ等の電子部品が使用される。このような積層型コンデンサは、例えば、特許文献１に開示されている。 In recent years, information processing equipment, communication equipment, and the like have been digitized, and the frequency of digital signals handled by these equipments has been increasing with the increase in information processing capability. Therefore, in these devices, generated noise tends to increase in a high frequency band, and for example, electronic components such as multilayer capacitors are used for noise countermeasures. Such a multilayer capacitor is disclosed in Patent Document 1, for example.
特開２００９－６０１１４号公報JP 2009-60114 A
　本開示の積層型コンデンサは、積層体と、信号用内部電極と、接地用内部電極と、外部電極と、接地用外部端子と、第１のキャパシタ部と、第２のキャパシタ部と、を備えている。積層体は、複数の誘電体層が積層された、一対の第１の面および第２の面、一対の第１の側面および第２の側面、一対の第１の端面および第２の端面を有する直方体状である。信号用内部電極は、前記積層体内の前記第１の面、前記第２の面と平行となる同一面内に間隔をおいて配置された、前記第１の端面に引き出された第１の信号用内部電極および前記第２の端面に引き出された第２の信号用内部電極を含んでいる。接地用内部電極は、積層方向に隣り合う前記信号用内部電極の間に積層方向に前記第１の信号用内部電極および前記第２の信号用内部電極に対向して配置され、前記第１の側面および第２の側面に引き出されている。外部電極は、前記積層体の前記第１の端面に配置され、前記第１の信号用内部電極に接続された第１の外部電極および前記第２の端面に配置され、前記第２の信号用内部電極に接続された第２の外部電極を含んでいる。接地用外部端子は、前記積層体の前記第１の側面に配置され、前記接地用内部電極に接続された第１の接地用外部端子および前記第２の側面に配置され、前記接地用内部電極に接続された第２の接地用外部端子を含んでいる。第１のキャパシタ部は、積層方向に従って配列され、複数の前記第１の信号用内部電極と複数の前記接地用内部電極とが前記誘電体層を挟んで交互に積層されている。第２のキャパシタ部は、積層方向に従って配列され、複数の前記第２の信号用内部電極と複数の前記接地用内部電極とが前記誘電体層を挟んで交互に積層されている。前記第１のキャパシタ部は、前記第２のキャパシタ部よりも容量が小さい。 The multilayer capacitor of the present disclosure includes a multilayer body, a signal internal electrode, a grounding internal electrode, an external electrode, a grounding external terminal, a first capacitor unit, and a second capacitor unit. ing. The stacked body includes a pair of first and second surfaces, a pair of first and second side surfaces, a pair of first and second end surfaces on which a plurality of dielectric layers are stacked. It has a rectangular parallelepiped shape. The signal internal electrode is a first signal led out to the first end face, which is disposed in the same plane parallel to the first surface and the second surface in the stacked body and spaced from each other. And a second signal internal electrode led out to the second end face. The grounding internal electrode is disposed between the signal internal electrodes adjacent to each other in the stacking direction so as to face the first signal internal electrode and the second signal internal electrode in the stacking direction, and It is pulled out to the side surface and the second side surface. An external electrode is disposed on the first end surface of the laminate, and is disposed on the first external electrode connected to the first signal internal electrode and the second end surface, and the second signal surface. A second external electrode connected to the internal electrode is included. The grounding external terminal is disposed on the first side surface of the laminate, and is disposed on the first grounding external terminal connected to the grounding internal electrode and the second side surface, and the grounding internal electrode And a second grounding external terminal connected to the. The first capacitor portions are arranged according to the stacking direction, and a plurality of the first signal internal electrodes and a plurality of the ground internal electrodes are alternately stacked with the dielectric layer interposed therebetween. The second capacitor sections are arranged according to the stacking direction, and a plurality of the second signal internal electrodes and a plurality of the ground internal electrodes are alternately stacked with the dielectric layer interposed therebetween. The first capacitor unit has a smaller capacity than the second capacitor unit.
一実施の形態に係る積層型コンデンサを示す概略の斜視図である。1 is a schematic perspective view showing a multilayer capacitor according to an embodiment. 図１に示す積層型コンデンサのＡ－Ａ線で切断した断面図である。FIG. 2 is a cross-sectional view of the multilayer capacitor shown in FIG. 1 cut along line AA. 図１に示す積層型コンデンサのＢ－Ｂ線で切断した断面図である。FIG. 2 is a cross-sectional view of the multilayer capacitor shown in FIG. 1 cut along line BB. 図１に示す積層型コンデンサの積層体の概略の分解斜視図である。FIG. 2 is a schematic exploded perspective view of the multilayer body of the multilayer capacitor shown in FIG. 1. 図１に示す積層型コンデンサの積層方向に対して直交する方向の第１のキャパシタ部および第２のキャパシタ部の第１の信号用内部電極および第２の信号用内部電極を示す断面図である。FIG. 2 is a cross-sectional view showing a first signal internal electrode and a second signal internal electrode of a first capacitor section and a second capacitor section in a direction orthogonal to the stacking direction of the multilayer capacitor shown in FIG. 1. . 図１に示す積層型コンデンサの積層方向に対して直交する方向の第１のキャパシタ部および第２のキャパシタ部の接地用内部電極を示す断面図である。FIG. 2 is a cross-sectional view showing a grounding internal electrode of a first capacitor part and a second capacitor part in a direction orthogonal to the lamination direction of the multilayer capacitor shown in FIG. 1. 図１に示す積層型コンデンサの他の実施の形態の図１のＡ－Ａ線に相当する線で切断した断面図である。FIG. 7 is a cross-sectional view taken along a line corresponding to the line AA in FIG. 1 of another embodiment of the multilayer capacitor shown in FIG. 図１に示す積層型コンデンサの他の実施の形態の図１のＢ－Ｂ線に相当する線で切断した断面図である。FIG. 7 is a cross-sectional view taken along a line corresponding to the line BB in FIG. 1 of another embodiment of the multilayer capacitor shown in FIG. 図５Ａおよび図５Ｂに示す積層型コンデンサの積層体の概略の分解斜視図である。FIG. 6 is a schematic exploded perspective view of the multilayer capacitor multilayer body shown in FIGS. 5A and 5B. 積層体内に複数のキャパシタ部を有する積層型コンデンサの断面図である。It is sectional drawing of the multilayer capacitor | condenser which has a some capacitor part in a laminated body. 積層型コンデンサのインダクタ成分を説明するための説明図である。It is explanatory drawing for demonstrating the inductor component of a multilayer capacitor. 積層型コンデンサのインダクタ成分を説明するための説明図である。It is explanatory drawing for demonstrating the inductor component of a multilayer capacitor. 一実施の形態に係る積層型コンデンサの周波数帯のインピーダンス特性を示すグラフである。It is a graph which shows the impedance characteristic of the frequency band of the multilayer capacitor which concerns on one embodiment.
　例えば、積層型コンデンサは、ＣＰＵ等のＬＳＩの電源回路等において、電源ラインまたは他のデバイスからＬＳＩへのノイズの入り込みを低減するために、また、ＬＳＩのノイズによる誤動作等を低減するために用いられる。 For example, a multilayer capacitor is used in an LSI power supply circuit such as a CPU in order to reduce noise from entering the LSI from a power supply line or other device, and to reduce malfunction due to LSI noise. It is done.
　しかしながら、情報処理機器または通信機器等は、高周波数化の傾向がさらに増加しつつある。積層型コンデンサは、例えば、信号ラインまたは電源ライン等の高周波数帯域のノイズを低減するために、等価直列インダクタンス（ＥＳＬ）をさらに低くする必要がある。 However, the trend toward higher frequencies is increasing further in information processing equipment or communication equipment. The multilayer capacitor needs to further reduce the equivalent series inductance (ESL) in order to reduce noise in a high frequency band such as a signal line or a power supply line.
　本開示の積層型コンデンサは、２つのキャパシタ部を積層体の積層方向に垂直な方向に並べて配置している。これにより、本開示の積層型コンデンサは、等価直列インダクタンス（ＥＳＬ）および等価直列抵抗（ＥＳＲ）を低くすることができる。以下、本開示の積層型コンデンサについて、詳細に説明する。 In the multilayer capacitor of the present disclosure, two capacitor parts are arranged side by side in a direction perpendicular to the stacking direction of the multilayer body. Thereby, the multilayer capacitor of the present disclosure can reduce the equivalent series inductance (ESL) and the equivalent series resistance (ESR). Hereinafter, the multilayer capacitor of the present disclosure will be described in detail.
　＜実施の形態＞
　以下、本開示の実施の形態に係る積層型コンデンサ１０について、図面を参照しながら説明する。 <Embodiment>
Hereinafter, the multilayer capacitor 10 according to the embodiment of the present disclosure will be described with reference to the drawings.
　積層型コンデンサ１０は、便宜的に、直交座標系ＸＹＺを定義するとともに、Ｚ方向の正側を上方として、上面もしくは下面の用語を用いる。なお、各図面において、同じ部材および同じ部分に関しては、共通の符号を用いて、重複する説明は省略する。 For convenience, the multilayer capacitor 10 defines an orthogonal coordinate system XYZ, and uses the term “upper surface” or “lower surface” with the positive side in the Z direction as the upper side. In addition, in each drawing, about the same member and the same part, the overlapping description is abbreviate | omitted using a common code | symbol.
　積層型コンデンサ１０は、図１乃至図３に示すように、積層体１と、信号用内部電極２（第１の信号用内部電極２ａおよび第２の信号用内部電極２ｂ）、接地用内部電極３と、外部電極４（第１の外部電極４ａおよび第２の外部電極４ｂ）と、接地用外部端子５（第１の接地用外部端子５ａおよび第２の接地用外部端子５ｂ）と、第１のキャパシタ部６ａと、第２のキャパシタ部６ｂと、を備えている。 As shown in FIGS. 1 to 3, the multilayer capacitor 10 includes a multilayer body 1, a signal internal electrode 2 (first signal internal electrode 2a and second signal internal electrode 2b), and a ground internal electrode. 3, external electrode 4 (first external electrode 4 a and second external electrode 4 b), ground external terminal 5 (first ground external terminal 5 a and second ground external terminal 5 b), 1 capacitor section 6a and second capacitor section 6b.
　第１のキャパシタ部６ａは、積層方向に従って配列された複数の第１の信号用内部電極２ａおよび複数の接地用内部電極３で形成されている。また、第２のキャパシタ部６ｂは、積層方向に従って配列された複数の第２の信号用内部電極２ｂおよび複数の接地用内部電極３で形成されている。積層型コンデンサ１０は、第１のキャパシタ部６ａおよび第２のキャパシタ部６ｂを有し、第１のキャパシタ部６ａおよび第２のキャパシタ部６ｂが互い異なる容量を有するように形成される。 The first capacitor section 6a is formed of a plurality of first signal internal electrodes 2a and a plurality of grounding internal electrodes 3 arranged in the stacking direction. The second capacitor portion 6b is formed of a plurality of second signal internal electrodes 2b and a plurality of grounding internal electrodes 3 arranged in the stacking direction. The multilayer capacitor 10 includes a first capacitor unit 6a and a second capacitor unit 6b, and is formed so that the first capacitor unit 6a and the second capacitor unit 6b have different capacities.
　積層体１は、複数の誘電体層１ｇが積層されて直方体状に形成されており、誘電体層１ｇとなるセラミックグリーンシートを複数枚積層して焼成することで得られる焼結体である。このように、積層体１は、直方体状に形成されており、一対の面、一対の端面および一対の側面を有している。一対の面は、互いに対向する第１の面１ａおよび第２の面１ｂである。一対の端面は、第１の面１ａおよび第２の面１ｂに直交し、互いに対向する第１の端面１ｃおよび第２の端面１ｄである。また、一対の側面は、第１の端面１ｃおよび第２の端面１ｄに直交し、互いに対向する第１の側面１ｅおよび第２の側面１ｆである。また、積層体１は、誘電体層１ｇの積層方向（Ｚ方向）に対して、直交する断面（ＸＹ面）となる平面が、図４Ａおよび図４Ｂに示すように長方形状となっている。 The laminated body 1 is a sintered body obtained by laminating and firing a plurality of ceramic green sheets to be the dielectric layer 1g, in which a plurality of dielectric layers 1g are laminated to form a rectangular parallelepiped shape. Thus, the laminated body 1 is formed in a rectangular parallelepiped shape, and has a pair of surfaces, a pair of end surfaces, and a pair of side surfaces. The pair of surfaces are a first surface 1a and a second surface 1b that face each other. The pair of end surfaces are a first end surface 1c and a second end surface 1d that are orthogonal to the first surface 1a and the second surface 1b and face each other. The pair of side surfaces are a first side surface 1e and a second side surface 1f that are orthogonal to the first end surface 1c and the second end surface 1d and face each other. Moreover, the laminated body 1 has a rectangular plane as shown in FIGS. 4A and 4B, which is a cross section (XY plane) orthogonal to the laminating direction (Z direction) of the dielectric layer 1 g.
　積層型コンデンサ１０は、長手方向（Ｘ方向）の長さが、例えば、０．６（ｍｍ）～２．２（ｍｍ）であり、短手方向（Ｙ方向）の長さが、例えば、０．３（ｍｍ）～１．２（ｍｍ）であり、高さ方向（Ｚ方向）の長さが、例えば、０．３（ｍｍ）～１．５（ｍｍ）である。 The multilayer capacitor 10 has a length in the longitudinal direction (X direction) of, for example, 0.6 (mm) to 2.2 (mm), and a length in the short side direction (Y direction) of, for example, 0. .3 (mm) to 1.2 (mm), and the length in the height direction (Z direction) is, for example, 0.3 (mm) to 1.5 (mm).
　また、積層型コンデンサ１０は、図２Ａおよび図２Ｂに示すように、積層体１内に、第１のキャパシタ部６ａおよび第２のキャパシタ部６ｂが長手方向（Ｘ方向）に並んで形成されており、高さ方向（Ｚ方向）で容量を形成している。積層型コンデンサ１０は、第１のキャパシタ部６ａおよび第２のキャパシタ部６ｂの容量によって、高さ方向（Ｚ方向）の長さが短手方向（Ｙ方向）の長さよりも大きくなることがある。例えば、積層型コンデンサ１０は、長手方向（Ｘ方向）の長さが１．１５（ｍｍ）、短手方向（Ｙ方向）の長さが０．６５（ｍｍ）、高さ方向（Ｚ方向）の長さが短手方向（Ｙ方向）の長さよりも長い、０、８（ｍｍ）である、いわゆる、高背型のコンデンサである。 Further, as shown in FIGS. 2A and 2B, the multilayer capacitor 10 includes a first capacitor portion 6 a and a second capacitor portion 6 b arranged in the longitudinal direction (X direction) in the multilayer body 1. The capacitor is formed in the height direction (Z direction). In the multilayer capacitor 10, the length in the height direction (Z direction) may be longer than the length in the short direction (Y direction) depending on the capacitance of the first capacitor portion 6a and the second capacitor portion 6b. . For example, the multilayer capacitor 10 has a length in the longitudinal direction (X direction) of 1.15 (mm), a length in the short direction (Y direction) of 0.65 (mm), and a height direction (Z direction). This is a so-called high-back type capacitor in which the length is 0, 8 (mm) longer than the length in the short direction (Y direction).
　誘電体層１ｇは、積層方向（Ｚ方向）からの平面視において長方形状であり、１層当たりの厚みが、例えば、０．５（μｍ）～３（μｍ）である。積層体１は、例えば、１０（層）～１０００（層）の複数の誘電体層１ｇがＺ方向に積層されている。 The dielectric layer 1g is rectangular in a plan view from the stacking direction (Z direction), and the thickness per layer is, for example, 0.5 (μm) to 3 (μm). In the laminated body 1, for example, a plurality of dielectric layers 1g of 10 (layers) to 1000 (layers) are laminated in the Z direction.
　誘電体層１ｇは、例えば、チタン酸バリウム（ＢａＴｉＯ３）、チタン酸カルシウム（ＣａＴｉＯ３）、チタン酸ストロンチウム（ＳｒＴｉＯ３）またはジルコン酸カルシウム（ＣａＺｒＯ３）等である。また、誘電体層１ｇは、高い誘電率の点から、特に、誘電率の高い強誘電体材料としてチタン酸バリウムを用いてもよい。 The dielectric layer 1g is, for example, barium titanate (BaTiO 3 ), calcium titanate (CaTiO 3 ), strontium titanate (SrTiO 3 ), or calcium zirconate (CaZrO 3 ). In addition, the dielectric layer 1g may use barium titanate as a ferroelectric material having a high dielectric constant, particularly from the viewpoint of a high dielectric constant.
　信号用内部電極２は、第１の信号用内部電極２ａおよび第２の信号用内部電極２ｂを含んでいる。第１の信号用内部電極２ａおよび第２の信号用内部電極２ｂは、図４Ａに示すように、それぞれ四角形状であり、積層体１内の前記第１の面、前記第２の面と平行となる同一面内に間隔をおいて並んで配置されている。すなわち、第１の信号用内部電極２ａおよび第２の信号用内部電極２ｂは、図４Ａに示すように、積層方向に直交する方向の同一面内に間隔をおいて並んで配置されている。第１の信号用内部電極２ａは、第１の端面１ｃに引き出されている。また、第２の信号用内部電極２ｂは、第２の端面１ｄに引き出されている。 The signal internal electrode 2 includes a first signal internal electrode 2a and a second signal internal electrode 2b. As shown in FIG. 4A, each of the first signal internal electrode 2a and the second signal internal electrode 2b has a quadrangular shape, and is parallel to the first surface and the second surface in the multilayer body 1. Are arranged side by side in the same plane. That is, as shown in FIG. 4A, the first signal internal electrode 2a and the second signal internal electrode 2b are arranged side by side in the same plane in the direction orthogonal to the stacking direction. The first signal internal electrode 2a is drawn out to the first end face 1c. The second signal internal electrode 2b is drawn out to the second end face 1d.
　図４Ａに示すように、第１の信号用内部電極２ａは、長手方向（Ｘ方向）の長さＸ１が、例えば、１２５（μｍ）～２２５（μｍ）である。第２の信号用内部電極２ｂは、長手方向（Ｘ方向）の長さＸ２が、例えば、８５０（μｍ）～９５０（μｍ）である。長さＸ１および長さＸ２は、第１のキャパシタ部６ａおよび第２のキャパシタ部６ｂのそれぞれの容量によって適宜設定される。また、第１の信号用内部電極２ａと第２の信号用内部電極２ｂとの間隔は、例えば、３０（μｍ）～１００（μｍ）である。 As shown in FIG. 4A, the first signal internal electrode 2a has a length X1 in the longitudinal direction (X direction) of, for example, 125 (μm) to 225 (μm). The second signal internal electrode 2b has a length X2 in the longitudinal direction (X direction) of, for example, 850 (μm) to 950 (μm). The length X1 and the length X2 are appropriately set according to the capacitances of the first capacitor unit 6a and the second capacitor unit 6b. The distance between the first signal internal electrode 2a and the second signal internal electrode 2b is, for example, 30 (μm) to 100 (μm).
　このように、第１の信号用内部電極２ａは、図４Ａに示すように、一端が第１の端面１ｃに露出し、第１の外部電極４ａに電気的に接続されている。第２の信号用内部電極２ｂは、一端が第２の端面１ｄに露出し、第２の外部電極４ｂに電気的に接続されている。また、信号用内部電極２は、図４Ａに示すように、第１の信号用内部電極２ａの長手方向（Ｘ方向）の長さＸ１が第２の信号用内部電極２ｂの長手方向（Ｘ方向）の長さＸ２よりも小さくなっている。積層方向から平面視して、接地用内部電極３に対向する第１の信号用内部電極２ａの面積は、接地用内部電極３に対向する第２の信号用内部電極２ｂの面積よりも小さくなっている。すなわち、積層方向から平面視して、第１の信号用内部電極２ａの面積は、第２の信号用内部電極２ｂの面積よりも小さい。 Thus, as shown in FIG. 4A, one end of the first signal internal electrode 2a is exposed to the first end face 1c and is electrically connected to the first external electrode 4a. One end of the second signal internal electrode 2b is exposed at the second end face 1d and is electrically connected to the second external electrode 4b. Further, as shown in FIG. 4A, the signal internal electrode 2 has a length X1 in the longitudinal direction (X direction) of the first signal internal electrode 2a that is equal to the longitudinal direction (X direction) of the second signal internal electrode 2b. ) Is smaller than the length X2. In plan view from the stacking direction, the area of the first signal internal electrode 2 a facing the ground internal electrode 3 is smaller than the area of the second signal internal electrode 2 b facing the ground internal electrode 3. ing. That is, in plan view from the stacking direction, the area of the first signal internal electrode 2a is smaller than the area of the second signal internal electrode 2b.
　接地用内部電極３は、図４Ｂに示すように、四角形状であり、積層方向に隣り合う信号用内部電極２の間に、積層方向に第１の信号用内部電極２ａおよび第２の信号用内部電極２ｂに対向して配置されている。接地用内部電極３は、図４Ｂに示すように、第１の側面１ｅへの引出部３ａおよび第２の側面１ｆへの引出部３ｂを有している。また、接地用内部電極３は、図４Ｂに示すように、引出部３ａが第１の側面１ｅに露出し、引出部３ｂが第２の側面１ｆに露出している。 As shown in FIG. 4B, the grounding internal electrode 3 has a quadrangular shape, and between the signal internal electrodes 2 adjacent in the stacking direction, the first signal internal electrode 2a and the second signal internal electrode 2 in the stacking direction. It is arranged to face the internal electrode 2b. As shown in FIG. 4B, the grounding internal electrode 3 has a lead portion 3a leading to the first side face 1e and a lead portion 3b leading to the second side face 1f. In addition, as shown in FIG. 4B, the grounding internal electrode 3 has the lead-out portion 3a exposed at the first side face 1e and the lead-out portion 3b exposed at the second side face 1f.
　信号用内部電極２および接地用内部電極３の導電材料は、例えば、ニッケル（Ｎｉ）、銅（Ｃｕ）、銀（Ａｇ）、パラジウム（Ｐｄ）または金（Ａｕ）等の金属材料である。また、信号用内部電極２および接地用内部電極３の導電材料は、これらの金属材料の１種以上を含む、例えば、Ａｇ－Ｐｄ合金等の合金材料である。信号用内部電極２および接地用内部電極３の導電材料は、同一の金属材料または合金材料を用いてもよい。また、信号用内部電極２および接地用内部電極３は、厚みが、例えば、０．５（μｍ）～２（μｍ）である。 The conductive material of the signal internal electrode 2 and the ground internal electrode 3 is a metal material such as nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), or gold (Au). In addition, the conductive material of the signal internal electrode 2 and the ground internal electrode 3 is an alloy material such as an Ag—Pd alloy including at least one of these metal materials. The same metal material or alloy material may be used for the conductive material of the signal internal electrode 2 and the ground internal electrode 3. The signal internal electrode 2 and the ground internal electrode 3 have a thickness of, for example, 0.5 (μm) to 2 (μm).
　外部電極４は、図１に示すように、第１の外部電極４ａおよび第２の外部電極４ｂを含んでいる。第１の外部電極４ａは、積層体１の第１の端面１ｃに配置され、第１の信号用内部電極２ａに接続されている。第２の外部電極４ｂは、第２の端面１ｄに配置され、第２の信号用内部電極２ｂに接続されている。図１に示すように、第１の外部電極４ａは、第１の端面１ｃの全体を覆うように設けられ、第２の外部電極４ｂは、第２の端面１ｄの全体を覆うように設けられている。 The external electrode 4 includes a first external electrode 4a and a second external electrode 4b as shown in FIG. The first external electrode 4a is disposed on the first end face 1c of the multilayer body 1 and connected to the first signal internal electrode 2a. The second external electrode 4b is disposed on the second end face 1d and connected to the second signal internal electrode 2b. As shown in FIG. 1, the first external electrode 4a is provided so as to cover the entire first end face 1c, and the second external electrode 4b is provided so as to cover the entire second end face 1d. ing.
　接地用外部端子５は、図１に示すように、第１の接地用外部端子５ａおよび第２の接地用外部端子５ｂを含んでいる。第１の接地用外部端子５ａは、図４Ｂに示すように、積層体１の第１の側面１ｅに配置され、接地用内部電極３の引出部３ａに接続されている。第２の接地用外部端子５ｂは、図４Ｂに示すように、積層体１の第２の側面１ｆに配置され、接地用内部電極３の引出部３ｂに接続されている。第１の接地用外部端子５ａは、図１に示すように、第１の側面１ｅから第１の面１ａおよび第２の面１ｂにそれぞれ延在するように設けられている。また、第２の接地用外部端子５ｂは、図１に示すように、第２の側面１ｆから第１の面１ａおよび第２の面１ｂにそれぞれ延在するように設けられている。 As shown in FIG. 1, the grounding external terminal 5 includes a first grounding external terminal 5a and a second grounding external terminal 5b. As shown in FIG. 4B, the first grounding external terminal 5 a is disposed on the first side surface 1 e of the multilayer body 1 and is connected to the lead portion 3 a of the grounding internal electrode 3. As shown in FIG. 4B, the second ground external terminal 5 b is disposed on the second side surface 1 f of the multilayer body 1 and is connected to the lead portion 3 b of the ground internal electrode 3. As shown in FIG. 1, the first ground external terminal 5a is provided so as to extend from the first side face 1e to the first face 1a and the second face 1b, respectively. Further, as shown in FIG. 1, the second ground external terminal 5b is provided so as to extend from the second side face 1f to the first face 1a and the second face 1b, respectively.
　第１の外部電極４ａおよび第２の外部電極４ｂは、図８Ａに示すように、積層型コンデンサ１０が搭載される実装基板８上の、例えば、信号ラインまたは電流ラインにそれぞれ接続されることになる。また、第１の接地用外部端子５ａおよび第２の接地用外部端子５ｂは、積層型コンデンサ１０が搭載される実装基板８上の、例えば、グランド用ラインにそれぞれ接続されることになる。 As shown in FIG. 8A, the first external electrode 4a and the second external electrode 4b are connected to, for example, a signal line or a current line on the mounting substrate 8 on which the multilayer capacitor 10 is mounted. Become. The first grounding external terminal 5a and the second grounding external terminal 5b are connected to, for example, a ground line on the mounting substrate 8 on which the multilayer capacitor 10 is mounted.
　外部電極４および接地用外部端子５は、下地電極とめっき層とを含んでいる。下地電極は、積層体１の表面に設けられ、第１の端面１ｃに露出した第１の信号用内部電極２ａおよび第２の端面１ｄに露出した第２の信号用内部電極２ｂに電気的に接続されている。また、下地電極は、積層体１の表面に設けられ、第１の側面１ｅおよび第２の側面１ｆに露出した接地用内部電極３に電気的に接続されている。めっき層は、積層体１の表面に形成された下地電極を覆うように下地電極の表面上に設けられている。めっき層は、下地電極を保護するために下地電極を覆うように設けられる。 The external electrode 4 and the grounding external terminal 5 include a base electrode and a plating layer. The base electrode is provided on the surface of the multilayer body 1 and is electrically connected to the first signal internal electrode 2a exposed on the first end face 1c and the second signal internal electrode 2b exposed on the second end face 1d. It is connected. The base electrode is provided on the surface of the multilayer body 1 and is electrically connected to the grounding internal electrode 3 exposed on the first side face 1e and the second side face 1f. The plating layer is provided on the surface of the base electrode so as to cover the base electrode formed on the surface of the multilayer body 1. The plating layer is provided so as to cover the base electrode in order to protect the base electrode.
　下地電極の導電材料は、例えば、ニッケル（Ｎｉ）、銅（Ｃｕ）、銀（Ａｇ）、パラジウム（Ｐｄ）または金（Ａｕ）等の金属材料である。または、下地電極の導電材料は、これらの金属材料の一種以上を含む、例えば、Ａｇ－Ｐｄ合金等の合金材料である。 The conductive material of the base electrode is, for example, a metal material such as nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), or gold (Au). Alternatively, the conductive material of the base electrode is an alloy material such as an Ag—Pd alloy including one or more of these metal materials.
　また、めっき層は、例えば、ニッケル（Ｎｉ）めっき層、銅（Ｃｕ）めっき層、金（Ａｕ）めっき層またはスズ（Ｓｎ）めっき層等である。また、めっき層は、例えば、電解めっき法を用いて下地電極の表面上に設けられる。 The plating layer is, for example, a nickel (Ni) plating layer, a copper (Cu) plating layer, a gold (Au) plating layer, a tin (Sn) plating layer, or the like. The plating layer is provided on the surface of the base electrode using, for example, an electrolytic plating method.
　めっき層は、下地電極の表面上に、単一のめっき層で形成しても、また、複数のめっき層で形成してもよい。例えば、複数のめっき層の場合、めっき層は、第１のめっき層および第１のめっき層の表面に形成された第２のめっき層の２層の積層体である。例えば、めっき層は、下地電極の表面にＮｉめっき層を設け、さらに、Ｎｉめっき層の表面にＳｎめっき層を設け、Ｎｉめっき層およびＳｎめっき層の２層の積層体にすることができる。 The plating layer may be formed of a single plating layer or a plurality of plating layers on the surface of the base electrode. For example, in the case of a plurality of plating layers, the plating layer is a two-layer laminate of a first plating layer and a second plating layer formed on the surface of the first plating layer. For example, the plating layer can be formed as a two-layered structure of a Ni plating layer and a Sn plating layer by providing a Ni plating layer on the surface of the base electrode and further providing a Sn plating layer on the surface of the Ni plating layer.
　積層型コンデンサ１０は、図３に示すように、第１の信号用内部電極２ａおよび第２の信号用内部電極２ｂが長手方向（Ｘ方向）に沿って間隔をおいて並んで配置されている。第１のキャパシタ部６ａは、積層方向に従って配列された複数の第１の信号用内部電極２ａおよび第１の信号用内部電極２ａに対向する複数の接地用内部電極３とで形成される。また、第２のキャパシタ部６ｂは、積層方向に従って配列された複数の第２の信号用内部電極２ｂおよび第２の信号用内部電極２ｂに対向する複数の接地用内部電極３とで形成される。また、接地用内部電極３は、信号用内部電極２に対向して設けられ、第１のキャパシタ部６ａおよび第２のキャパシタ部６ｂに対して共通に用いられる。 In the multilayer capacitor 10, as shown in FIG. 3, the first signal internal electrode 2a and the second signal internal electrode 2b are arranged side by side along the longitudinal direction (X direction). . The first capacitor portion 6a is formed by a plurality of first signal internal electrodes 2a and a plurality of ground internal electrodes 3 facing the first signal internal electrodes 2a arranged in the stacking direction. The second capacitor portion 6b is formed of a plurality of second signal internal electrodes 2b arranged in the stacking direction and a plurality of grounding internal electrodes 3 facing the second signal internal electrodes 2b. . The grounding internal electrode 3 is provided opposite to the signal internal electrode 2 and is used in common for the first capacitor portion 6a and the second capacitor portion 6b.
　このように、第１のキャパシタ部６ａは、図２Ａおよび図２Ｂに示すように、第１の信号用内部電極２ａ、誘電体層１ｇおよび接地用内部電極３からなり、第１の信号用内部電極２ａと接地用内部電極３との間には誘電体層１ｇが配置される。第１のキャパシタ部６ａは、第１の信号用内部電極２ａと接地用内部電極３が誘電体層１ｇを介して互いに対向するように、第１の面１ａ側から第２の面１ｂ側に向かって交互に配置されている。 Thus, as shown in FIGS. 2A and 2B, the first capacitor portion 6a includes the first signal internal electrode 2a, the dielectric layer 1g, and the ground internal electrode 3, and includes the first signal internal electrode 6a. A dielectric layer 1g is disposed between the electrode 2a and the grounding internal electrode 3. The first capacitor portion 6a is arranged from the first surface 1a side to the second surface 1b side so that the first signal internal electrode 2a and the ground internal electrode 3 face each other with the dielectric layer 1g therebetween. It is arranged alternately.
　また、第２のキャパシタ部６ｂは、図２Ａおよび図２Ｂに示すように、第２の信号用内部電極２ｂ、誘電体層１ｇおよび接地用内部電極３からなり、第２の信号用内部電極２ｂと接地用内部電極３との間には誘電体層１ｇが配置される。第２のキャパシタ部６ｂは、第２の信号用内部電極２ｂと接地用内部電極３が誘電体層１ｇを介して互いに対向するように、第１の面１ａ側から第２の面１ｂ側に向かって交互に配置されている。 Further, as shown in FIGS. 2A and 2B, the second capacitor portion 6b includes a second signal internal electrode 2b, a dielectric layer 1g, and a grounding internal electrode 3, and the second signal internal electrode 2b. 1 g of dielectric layer is disposed between the internal electrode 3 and the grounding internal electrode 3. The second capacitor portion 6b extends from the first surface 1a side to the second surface 1b side so that the second signal internal electrode 2b and the ground internal electrode 3 face each other with the dielectric layer 1g therebetween. It is arranged alternately.
　したがって、積層型コンデンサ１０は、積層体１内の積層方向において、第１のキャパシタ部６ａが第１の信号用内部電極２ａと接地用内部電極３とで容量を形成し、第２のキャパシタ部６ｂが第２の信号用内部電極２ｂと接地用内部電極３とで容量を形成している。 Therefore, in the multilayer capacitor 10, the first capacitor portion 6 a forms a capacitance with the first signal internal electrode 2 a and the ground internal electrode 3 in the stacking direction in the multilayer body 1, and the second capacitor portion 6b forms a capacitance with the second signal internal electrode 2b and the ground internal electrode 3.
　このように、積層型コンデンサ１０は、図２Ａおよび図２Ｂに示すように、積層体１内に第１のキャパシタ部６ａおよび第２のキャパシタ部６ｂの２つのキャパシタ部が設けられている。また、積層型コンデンサ１０は、第１のキャパシタ部６ａおよび第２のキャパシタ部６ｂが互いに異なる容量を有している。 Thus, as shown in FIGS. 2A and 2B, the multilayer capacitor 10 is provided with two capacitor parts, the first capacitor part 6a and the second capacitor part 6b, in the multilayer body 1. In the multilayer capacitor 10, the first capacitor portion 6a and the second capacitor portion 6b have different capacities.
　積層方向から平面視して、図４Ａに示すように、第１の信号用内部電極２ａは、第２の信号用内部電極２ｂよりも接地用内部電極３に対向する面積が小さい。これにより、積層型コンデンサ１０は、第１のキャパシタ部６ａの容量が第２のキャパシタ部６ｂの容量よりも小さい。 As seen in a plan view from the stacking direction, as shown in FIG. 4A, the first signal internal electrode 2a has a smaller area facing the grounding internal electrode 3 than the second signal internal electrode 2b. Thereby, in the multilayer capacitor 10, the capacitance of the first capacitor portion 6a is smaller than the capacitance of the second capacitor portion 6b.
　第１のキャパシタ部６ａは、図２Ａおよび図２Ｂに示すように、第１の面１ａ側から第２の面１ｂ側に向かって第１の信号用内部電極２ａと接地用内部電極３とが誘電体層１ｇを挟んでこの順に交互に積層されている。また、第２のキャパシタ部６ｂは、図２Ａおよび図２Ｂに示すように、第１の面１ａ側から第２の面１ｂ側に向かって第２の信号用内部電極２ｂと接地用内部電極３とが誘電体層１ｇを挟んでこの順に交互に積層されている。積層型コンデンサ１０は、このような信号用内部電極２および接地用内部電極３の配置に限定されない。積層型コンデンサ１０は、信号用内部電極２および接地用内部電極３のそれぞれの積層数が特性等に応じて適宜設計される。 As shown in FIGS. 2A and 2B, the first capacitor portion 6a includes a first signal internal electrode 2a and a grounding internal electrode 3 from the first surface 1a toward the second surface 1b. The dielectric layers 1g are alternately stacked in this order. Further, as shown in FIGS. 2A and 2B, the second capacitor portion 6b includes the second signal internal electrode 2b and the ground internal electrode 3 from the first surface 1a side to the second surface 1b side. Are alternately stacked in this order across the dielectric layer 1g. The multilayer capacitor 10 is not limited to such an arrangement of the signal internal electrode 2 and the ground internal electrode 3. In the multilayer capacitor 10, the number of stacked layers of the signal internal electrode 2 and the ground internal electrode 3 is appropriately designed according to characteristics and the like.
　例えば、積層型コンデンサ１０Ａは、図５Ａ、図５Ｂおよび図６に示すように、積層方向において、第１の面１ａ側および第２の面１ｂ側の最外層に接地用内部電極３を配置することができる。すなわち、積層型コンデンサ１０Ａは、図５Ａ、図５Ｂおよび図６に示すように、第１の面１ａ側から第２の面１ｂ側に向かって接地用内部電極３と信号用内部電極２とをこの順に交互に配置し、第２の面１ｂ側の最外層に接地用内部電極３を配置することができる。 For example, in the multilayer capacitor 10A, as shown in FIGS. 5A, 5B, and 6, the grounding internal electrode 3 is disposed on the outermost layer on the first surface 1a side and the second surface 1b side in the stacking direction. be able to. That is, as shown in FIGS. 5A, 5B, and 6, the multilayer capacitor 10A includes the grounding internal electrode 3 and the signal internal electrode 2 from the first surface 1a side to the second surface 1b side. By alternately arranging in this order, the grounding internal electrodes 3 can be arranged on the outermost layer on the second surface 1b side.
　積層型コンデンサ１０Ａは、例えば、接地用内部電極３がグランド用ラインに接続される場合には、積層方向において、第１のキャパシタ部６ａおよび第２のキャパシタ部６ｂの第１の面１ａ側および第２の面１ｂ側の最外層に接地用内部電極３を配置することができる。すなわち、積層型コンデンサ１０Ａは、第１の面１ａ側および第２の面１ｂ側にグランド用ラインに接続される接地用内部電極３を配置することにより、外部からの電界等が遮られるのでシールド性を向上させることができる。 For example, when the grounding internal electrode 3 is connected to the ground line, the multilayer capacitor 10A includes the first capacitor portion 6a and the second capacitor portion 6b on the first surface 1a side and The grounding internal electrode 3 can be disposed on the outermost layer on the second surface 1b side. That is, the multilayer capacitor 10A is shielded by arranging the grounding internal electrode 3 connected to the ground line on the first surface 1a side and the second surface 1b side, thereby blocking the electric field from the outside. Can be improved.
　このように、積層型コンデンサ１０Ａは、第１のキャパシタ部６ａおよび第２のキャパシタ部６ｂの第１の面１ａ側および第２の面１ｂ側の最外層にグランド用ラインに接続される接地用内部電極３をそれぞれ配置することにより、シールド性が向上する。積層型コンデンサ１０Ａは、例えば、入力耐性以上のノイズまたは静電気による放電等の外乱ノイズの影響を低減することができる。 As described above, the multilayer capacitor 10A is connected to the ground line on the outermost layer on the first surface 1a side and the second surface 1b side of the first capacitor unit 6a and the second capacitor unit 6b. By arranging the internal electrodes 3 respectively, the shielding property is improved. The multilayer capacitor 10A can reduce the influence of disturbance noise such as noise exceeding input tolerance or discharge due to static electricity.
　積層型コンデンサ１０は、例えば、第１のキャパシタ部６ａの容量が１（μＦ）であり、第２のキャパシタ部６ｂの容量が１５（μＦ）である。また、積層型コンデンサ１０は、第１のキャパシタ部６ａの容量が、例えば、１（μＦ）～３（μＦ）の範囲内に設定され、第２のキャパシタ部６ｂの容量が、例えば、１０（μＦ）～１５（μＦ）の範囲内に設定される。 In the multilayer capacitor 10, for example, the capacitance of the first capacitor portion 6a is 1 (μF), and the capacitance of the second capacitor portion 6b is 15 (μF). In the multilayer capacitor 10, the capacitance of the first capacitor portion 6a is set within a range of 1 (μF) to 3 (μF), for example, and the capacitance of the second capacitor portion 6b is, for example, 10 ( μF) to 15 (μF).
　積層型コンデンサ１０Ｂは、図７に示すように、図１に示す積層型コンデンサ１０のＡ－Ａ線に相当する線で切断した断面図であり、積層体１内に２つのキャパシタ部６Ａおよびキャパシタ部６Ｂを有している。積層型コンデンサ１０は、図２Ａに示すように、第１のキャパシタ部６ａおよび第２のキャパシタ部６ｂがＸ方向に配置されている。一方、積層型コンデンサ１０Ｂは、キャパシタ部６Ａおよびキャパシタ部６ＢがＺ方向に配置されている。このように、積層型コンデンサ１０は、キャパシタ部６Ａを積層体１内の積層方向に第１のキャパシタ部６ａとして配列し、また、キャパシタ部６Ｂを積層体１内の積層方向に第２のキャパシタ部６ｂとして配列している。例えば、積層型コンデンサ１０Ｂは、キャパシタ部６Ａの容量が１（μＦ）であり、キャパシタ部６Ｂの容量が１５（μＦ）であるとすると、積層型コンデンサ１０は、第１のキャパシタ部６ａの容量が１（μＦ）であり、第２のキャパシタ部６ｂの容量が１５（μＦ）である。 As shown in FIG. 7, the multilayer capacitor 10B is a cross-sectional view taken along the line AA of the multilayer capacitor 10 shown in FIG. 1, and includes two capacitor portions 6A and a capacitor in the multilayer body 1. It has a part 6B. In the multilayer capacitor 10, as shown in FIG. 2A, the first capacitor portion 6a and the second capacitor portion 6b are arranged in the X direction. On the other hand, in the multilayer capacitor 10B, the capacitor part 6A and the capacitor part 6B are arranged in the Z direction. As described above, the multilayer capacitor 10 has the capacitor portion 6A arranged as the first capacitor portion 6a in the stacking direction in the multilayer body 1, and the capacitor portion 6B is arranged in the stacking direction in the multilayer body 1 as the second capacitor. It arranges as part 6b. For example, in the multilayer capacitor 10B, when the capacitance of the capacitor unit 6A is 1 (μF) and the capacitance of the capacitor unit 6B is 15 (μF), the multilayer capacitor 10 has the capacitance of the first capacitor unit 6a. Is 1 (μF), and the capacitance of the second capacitor portion 6b is 15 (μF).
　積層型コンデンサ１０は、第１のキャパシタ部６ａおよび第２のキャパシタ部６ｂを積層体１の積層方向に垂直な方向に並べて配置しており、積層型コンデンサ１０Ｂのようにキャパシタ部６Ａとキャパシタ部６Ｂとの間の間隔を設けなくてもよく、積層型コンデンサ１０Ｂよりも高さ方向（Ｚ方向）の長さを小さくすることができる。 In the multilayer capacitor 10, the first capacitor portion 6a and the second capacitor portion 6b are arranged in a direction perpendicular to the lamination direction of the multilayer body 1, and the capacitor portion 6A and the capacitor portion are arranged like the multilayer capacitor 10B. It is not necessary to provide an interval between the capacitor 6B and the length in the height direction (Z direction) can be made smaller than that of the multilayer capacitor 10B.
　ここで、積層型コンデンサ１０および積層型コンデンサ１０Ｂのインダクタ成分について説明する。図８Ａおよび図８Ｂは、積層型コンデンサ１０および積層型コンデンサ１０Ｂを実装基板８上に実装した場合の断面図を示している。積層型コンデンサ１０Ｂにおいて、図８Ｂに示すように、Ｌ０は、容量の小さいキャパシタ部６Ａのインダクタ成分であり、Ｌ１は、容量の大きいキャパシタ部６Ｂのインダクタ成分である。また、積層型コンデンサ１０において、図８Ａに示すように、Ｌ２は、第１のキャパシタ部６ａのインダクタ成分であり、Ｌ３は、第２のキャパシタ部６ｂのインダクタ成分である。 Here, the inductor components of the multilayer capacitor 10 and the multilayer capacitor 10B will be described. 8A and 8B are cross-sectional views when the multilayer capacitor 10 and the multilayer capacitor 10B are mounted on the mounting substrate 8. FIG. In the multilayer capacitor 10B, as shown in FIG. 8B, L0 is an inductor component of the capacitor unit 6A having a small capacity, and L1 is an inductor component of the capacitor unit 6B having a large capacity. In the multilayer capacitor 10, as shown in FIG. 8A, L2 is an inductor component of the first capacitor unit 6a, and L3 is an inductor component of the second capacitor unit 6b.
　図８Ｂに示すように、積層型コンデンサ１０Ｂを実装基板８上に実装した場合、キャパシタ部６Ａは、実装基板８の表面からの距離（Ｚ方向の距離）が小さいことから、実装基板８の入力端子８ａ１から実装基板８のＧＮＤ端子８ｂに流れる電流経路の物理長（ループ長）が短くなり、インダクタ成分Ｌ０が小さくなる。一方、キャパシタ部６Ｂは、実装基板８の表面からの距離（Ｚ方向の距離）が大きいことから、実装基板８の入力端子８ａ２から実装基板８のＧＮＤ端子８ｂに流れる電流経路の物理長（ループ長）が長くなり、インダクタ成分Ｌ１が大きくなる。 As shown in FIG. 8B, when the multilayer capacitor 10B is mounted on the mounting substrate 8, the capacitor portion 6A has a small distance from the surface of the mounting substrate 8 (distance in the Z direction). The physical length (loop length) of the current path flowing from the terminal 8a1 to the GND terminal 8b of the mounting substrate 8 is reduced, and the inductor component L0 is reduced. On the other hand, since the capacitor section 6B has a large distance (distance in the Z direction) from the surface of the mounting board 8, the physical length (loop) of the current path flowing from the input terminal 8a2 of the mounting board 8 to the GND terminal 8b of the mounting board 8 Length) becomes longer, and the inductor component L1 becomes larger.
　一方、図８Ａに示すように、積層型コンデンサ１０を実装基板８上に実装した場合、第１のキャパシタ部６ａおよび第２のキャパシタ部６ｂは、実装基板８の表面からの距離（Ｚ方向の距離）が同じになる。第１のキャパシタ部６ａは、実装基板８の入力端子８ａ１から実装基板８のＧＮＤ端子８ｂに流れる電流経路の物理長（ループ長）が短くなる。また、第２のキャパシタ部６ｂは、実装基板８の入力端子８ａ２から実装基板８のＧＮＤ端子８ｂに流れる電流経路の物理長（ループ長）が短くなる。第１のキャパシタ部６ａおよび第２のキャパシタ部６ｂは、電流経路の物理長（ループ長）が短くなるとともに、最短の物理長（ループ長）になり、積層型コンデンサ１０は、第１のキャパシタ部６ａのインダクタ成分Ｌ２および第２のキャパシタ部６ｂのインダクタ成分Ｌ３を小さくすることができる。 On the other hand, as shown in FIG. 8A, when the multilayer capacitor 10 is mounted on the mounting substrate 8, the first capacitor portion 6a and the second capacitor portion 6b are separated from the surface of the mounting substrate 8 (in the Z direction). Distance) is the same. In the first capacitor unit 6a, the physical length (loop length) of the current path flowing from the input terminal 8a1 of the mounting substrate 8 to the GND terminal 8b of the mounting substrate 8 is shortened. Further, in the second capacitor unit 6b, the physical length (loop length) of the current path flowing from the input terminal 8a2 of the mounting board 8 to the GND terminal 8b of the mounting board 8 is shortened. The first capacitor unit 6a and the second capacitor unit 6b have the shortest physical length (loop length) as well as the physical length (loop length) of the current path, and the multilayer capacitor 10 includes the first capacitor The inductor component L2 of the part 6a and the inductor component L3 of the second capacitor part 6b can be reduced.
　積層型コンデンサ１０は、第１のキャパシタ部６ａのインダクタ成分Ｌ２が積層型コンデンサ１０Ｂのキャパシタ部６Ａのインダクタ成分Ｌ０がほぼ同じである。一方、積層型コンデンサ１０は、第２のキャパシタ部６ｂのインダクタ成分Ｌ３が積層型コンデンサ１０Ｂのキャパシタ部６Ｂのインダクタ成分Ｌ１よりも小さく、積層型コンデンサ１０Ｂよりもインダクタ成分が小さくなる。したがって、積層型コンデンサ１０は、インダクタ成分Ｌ３が小さくなり、共振周波数を高周波数側へシフトさせることができる。 In the multilayer capacitor 10, the inductor component L2 of the first capacitor portion 6a is substantially the same as the inductor component L0 of the capacitor portion 6A of the multilayer capacitor 10B. On the other hand, in the multilayer capacitor 10, the inductor component L3 of the second capacitor unit 6b is smaller than the inductor component L1 of the capacitor unit 6B of the multilayer capacitor 10B, and the inductor component is smaller than that of the multilayer capacitor 10B. Therefore, in the multilayer capacitor 10, the inductor component L3 becomes small, and the resonance frequency can be shifted to the high frequency side.
　また、積層型コンデンサ１０は、積層体１内に第１のキャパシタ部６ａおよび第２のキャパシタ部６ｂが設けられ、第１のキャパシタ部６ａの容量が第２のキャパシタ部６ｂの容量よりも小さくなっている。第１のキャパシタ部６ａは、容量を積層方向で形成し、第１の信号用内部電極２ａと接地用内部電極３との積層数が多くなり、積層型コンデンサ１０は、等価直列抵抗（ＥＳＲ）が小さくなる。したがって、積層型コンデンサ１０は、第１のキャパシタ部６ａおよび第２のキャパシタ部６ｂの容量が異なり、図９に示すように、周波数の異なる２つの共振周波数を有し、高周波数帯域のインピーダンスが全体的に小さくなる。 In the multilayer capacitor 10, the first capacitor unit 6a and the second capacitor unit 6b are provided in the multilayer body 1, and the capacitance of the first capacitor unit 6a is smaller than the capacitance of the second capacitor unit 6b. It has become. The first capacitor section 6a has a capacitance formed in the stacking direction, and the number of stacks of the first signal internal electrode 2a and the grounding internal electrode 3 increases. The multilayer capacitor 10 has an equivalent series resistance (ESR). Becomes smaller. Therefore, the multilayer capacitor 10 has different capacities of the first capacitor unit 6a and the second capacitor unit 6b, and has two resonance frequencies having different frequencies as shown in FIG. Overall smaller.
　このように、積層型コンデンサ１０は、高周波数帯域でのインピーダンス特性が向上し、高周波数帯域においてノイズが低減される帯域を広くすることができる。 As described above, the multilayer capacitor 10 can improve the impedance characteristic in the high frequency band and can widen the band in which noise is reduced in the high frequency band.
　積層型コンデンサ１０は、容量の異なる第１のキャパシタ部６ａおよび第２のキャパシタ部６ｂを設けることにより、等価直列インダクタンス（ＥＳＬ）が小さくなり、共振周波数が高周波数帯域側にシフトするとともに、等価直列抵抗（ＥＳＲ）が小さくなり、共振周波数のインピーダンスを小さくすることができる。積層型コンデンサ１０は、高周波数側の共振周波数の最下点が下方側に位置し、インピーダンスが小さくなり、高周波数帯域のノイズを低減することができる。 The multilayer capacitor 10 is provided with the first capacitor portion 6a and the second capacitor portion 6b having different capacities, thereby reducing the equivalent series inductance (ESL), shifting the resonance frequency to the high frequency band side, and equivalently. The series resistance (ESR) is reduced, and the impedance at the resonance frequency can be reduced. In the multilayer capacitor 10, the lowest point of the resonance frequency on the high frequency side is located on the lower side, the impedance is reduced, and noise in the high frequency band can be reduced.
　図９は、積層型コンデンサ１０および積層型コンデンサ１０Ｂの周波数帯のインピーダンス特性を示すグラフであり、Ａは積層型コンデンサ１０のインピーダンス特性を示し、Ｂは積層型コンデンサ１０Ｂのインピーダンス特性を示している。 FIG. 9 is a graph showing impedance characteristics in the frequency band of the multilayer capacitor 10 and the multilayer capacitor 10B. A shows the impedance characteristic of the multilayer capacitor 10, and B shows the impedance characteristic of the multilayer capacitor 10B. .
　積層型コンデンサ１０は、第１のキャパシタ部６ａの容量が１（μＦ）であり、第２のキャパシタ部６ｂの容量が１５（μＦ）である。また、積層型コンデンサ１０Ｂは、キャパシタ部６Ａの容量が１（μＦ）、キャパシタ部６Ｂの容量が１５（μＦ）である。その他の構成は同じである。なお、積層型コンデンサ１０および積層型コンデンサ１０Ｂは、長手方向（Ｘ方向）の長さが１．１５（ｍｍ）であり、短手方向（Ｙ方向）の長さが０．６５（ｍｍ）であり、高さ方向（Ｚ方向）の長さが０，８（ｍｍ）である。 In the multilayer capacitor 10, the capacity of the first capacitor section 6a is 1 (μF), and the capacity of the second capacitor section 6b is 15 (μF). In the multilayer capacitor 10B, the capacitance of the capacitor unit 6A is 1 (μF), and the capacitance of the capacitor unit 6B is 15 (μF). Other configurations are the same. The multilayer capacitor 10 and the multilayer capacitor 10B have a length in the longitudinal direction (X direction) of 1.15 (mm) and a length in the lateral direction (Y direction) of 0.65 (mm). The length in the height direction (Z direction) is 0.8 (mm).
　積層型コンデンサ１０は、図９に示すように、等価直列インダクタンス（ＥＳＬ）が小さく、共振周波数が高周波数帯域側にシフトするとともに、等価直列抵抗（ＥＳＲ）が小さく、共振周波数のインピーダンスが小さくなる。積層型コンデンサ１０は、高周波側の共振周波数の最下点が下方側に位置しており、高周波数帯域のインピーダンスが積層型コンデンサ１０Ｂよりも小さくなっている。 As shown in FIG. 9, the multilayer capacitor 10 has a small equivalent series inductance (ESL), a resonance frequency shifts to the high frequency band side, a small equivalent series resistance (ESR), and a small impedance at the resonance frequency. . In the multilayer capacitor 10, the lowest point of the resonance frequency on the high frequency side is located on the lower side, and the impedance in the high frequency band is smaller than that of the multilayer capacitor 10B.
　また、積層型コンデンサ１０は、図２Ａに示すように、第１の信号用内部電極２ａと第２の信号用内部電極２ｂとが間隔をおいて配置されている。このように、積層型コンデンサ１０は、第１の信号用内部電極２ａと第２の信号用内部電極２ｂとの間には電極が設けられていない。積層型コンデンサ１０は、焼成時において電極がある部分と電極が無い部分とで収縮率が異なり、第１の信号用内部電極２ａと第２の信号用内部電極２ｂの間がより収縮する。したがって、積層型コンデンサ１０は、第１のキャパシタ部６ａと第２のキャパシタ部６ｂとの間に相当する位置の積層体１の表面に凹み７が形成される。すなわち、第１の面１ａまたは第２の面１ｂは、隣り合う第１の信号用内部電極２ａと第２の信号用内部電極２ｂとの間の領域に対応する部分が凹んでいる。積層型コンデンサ１０は、図１に示すように、積層体１の第１の面１ａ、第１の側面１ｅ、第２の面１ｂおよび第２の側面１ｆにわたって凹み７が形成されている。また、凹み７は、第１の面１ａまたは第２の面１ｂに顕著に形成されやすい。 In the multilayer capacitor 10, as shown in FIG. 2A, the first signal internal electrode 2a and the second signal internal electrode 2b are arranged with a space therebetween. Thus, in the multilayer capacitor 10, no electrode is provided between the first signal internal electrode 2a and the second signal internal electrode 2b. The multilayer capacitor 10 has a different shrinkage ratio between a portion having an electrode and a portion having no electrode at the time of firing, and the space between the first signal internal electrode 2a and the second signal internal electrode 2b is further contracted. Therefore, in the multilayer capacitor 10, the dent 7 is formed on the surface of the multilayer body 1 at a position corresponding to between the first capacitor portion 6a and the second capacitor portion 6b. That is, the first surface 1a or the second surface 1b has a recessed portion corresponding to the region between the adjacent first signal internal electrode 2a and the second signal internal electrode 2b. As shown in FIG. 1, the multilayer capacitor 10 has a recess 7 formed over the first surface 1 a, the first side surface 1 e, the second surface 1 b, and the second side surface 1 f of the multilayer body 1. Moreover, the dent 7 is easily formed remarkably on the first surface 1a or the second surface 1b.
　積層型コンデンサ１０は、積層体１の表面の凹み７の位置によって、第１の信号用内部電極２ａが外部電極４のうちの第１の外部電極４ａに接続されているのか、第２の外部電極４ｂに接続されているかを判定することができる。例えば、図２Ａに示すように、積層型コンデンサ１０を第１の側面１ｅ（第２の側面１ｆ）に垂直な方向（Ｙ方向）から側面視した場合に、積層型コンデンサ１０は、凹み７が第１の外部電極４ａ側に位置していることにより第１のキャパシタ部６ａがＸ方向の正側に配置されている。すなわち、積層型コンデンサ１０は、第１の信号用内部電極２ａが第１の外部電極４ａに接続されていることがわかる。また、積層型コンデンサ１０を第１の面１ａ（第２の面１ｂ）に垂直な方向（Ｘ方向）から平面視した場合にも、第１の信号用内部電極２ａが第１の外部電極４ａに接続されていることがわかる。 In the multilayer capacitor 10, whether the first signal internal electrode 2a is connected to the first external electrode 4a of the external electrodes 4 or not according to the position of the recess 7 on the surface of the multilayer body 1, It can be determined whether it is connected to the electrode 4b. For example, as shown in FIG. 2A, when the multilayer capacitor 10 is viewed from the side (Y direction) perpendicular to the first side surface 1 e (second side surface 1 f), the multilayer capacitor 10 has a recess 7. By being located on the first external electrode 4a side, the first capacitor portion 6a is arranged on the positive side in the X direction. That is, in the multilayer capacitor 10, it can be seen that the first signal internal electrode 2a is connected to the first external electrode 4a. In addition, when the multilayer capacitor 10 is viewed in plan from the direction (X direction) perpendicular to the first surface 1a (second surface 1b), the first signal internal electrode 2a is connected to the first external electrode 4a. You can see that it is connected to.
　このように、積層型コンデンサ１０は、第１のキャパシタ部６ａが第１の外部電極４ａ側に設けられ、第２のキャパシタ部６ｂが第２の外部電極４ｂ側に設けられており、凹み７によって方向性が明確になる。これによって、積層型コンデンサ１０は、実装基板８に実装する際に所望の方向に実装することができる。 As described above, the multilayer capacitor 10 includes the first capacitor portion 6a provided on the first external electrode 4a side, the second capacitor portion 6b provided on the second external electrode 4b side, and the recess 7 The direction becomes clear. Thereby, the multilayer capacitor 10 can be mounted in a desired direction when mounted on the mounting substrate 8.
　また、積層型コンデンサ１０は、凹み７によって方向性が明確になり、テーピングのキャリアテープのポケットに挿入する際に所望の方向に挿入することができる。 Further, the direction of the multilayer capacitor 10 is clarified by the recess 7 and can be inserted in a desired direction when being inserted into the pocket of the taping carrier tape.
　ここで、図１に示す積層型コンデンサ１０の製造方法の一例について説明する。 Here, an example of a method for manufacturing the multilayer capacitor 10 shown in FIG. 1 will be described.
　複数の第１および第２のセラミックグリーンシートを準備する。第１のセラミックグリーンシートは第１の信号用内部電極２ａおよび第２の信号用内部電極２ｂが形成される。第２のセラミックグリーンシートは接地用内部電極３が形成される。 Prepare a plurality of first and second ceramic green sheets. The first ceramic green sheet is formed with a first signal internal electrode 2a and a second signal internal electrode 2b. The second ceramic green sheet has a grounding internal electrode 3 formed thereon.
　複数の第１のセラミックグリーンシートは、セラミックグリーンシート上に、信号用内部電極２の導体ペースト層を信号用内部電極２用の導体ペーストを用いて形成する。なお、第１のセラミックグリーンシートには、多数個の積層型コンデンサ１０を得るために、１枚のセラミックグリーンシート内に複数の信号用内部電極２が形成される。 The plurality of first ceramic green sheets are formed by using the conductor paste for the signal internal electrode 2 on the ceramic green sheet. In the first ceramic green sheet, a plurality of signal internal electrodes 2 are formed in one ceramic green sheet in order to obtain a large number of multilayer capacitors 10.
　また、複数の第２のセラミックグリーンシートは、セラミックグリーンシート上に、接地用内部電極３の導体ペースト層を接地用内部電極３用の導体ペーストを用いて形成する。なお、第２のセラミックグリーンシートには、多数個の積層型コンデンサ１０を得るために、１枚のセラミックグリーンシート内に複数の接地用内部電極３が形成される。 Further, the plurality of second ceramic green sheets are formed on the ceramic green sheet by using the conductive paste layer for the grounding internal electrode 3 with the conductive paste layer for the grounding internal electrode 3. In the second ceramic green sheet, a plurality of grounding internal electrodes 3 are formed in one ceramic green sheet in order to obtain a large number of multilayer capacitors 10.
　上述の信号用内部電極２および接地用内部電極３の導体ペースト層は、セラミックグリーンシート上に、例えば、それぞれの導体ペーストを所定のパターン形状でスクリーン印刷法等を用いて形成される。 The conductor paste layers of the signal internal electrode 2 and the ground internal electrode 3 described above are formed on the ceramic green sheet, for example, by using a screen printing method or the like with each conductor paste in a predetermined pattern shape.
　なお、第１および第２のセラミックグリーンシートは、誘電体層１ｇとなり、信号用内部電極２の導体ペースト層は、第１の信号用内部電極２ａおよび第２の信号用内部電極２ｂとなり、接地用内部電極３の導体ペースト層は、接地用内部電極３となる。 The first and second ceramic green sheets serve as the dielectric layer 1g, and the conductor paste layer of the signal internal electrode 2 serves as the first signal internal electrode 2a and the second signal internal electrode 2b. The conductive paste layer of the internal electrode 3 becomes the ground internal electrode 3.
　セラミックグリーンシートの材料は、例えば、ＢａＴｉＯ３、ＣａＴｉＯ３、ＳｒＴｉＯ３またはＣａＺｒＯ３等の誘電体セラミックスを主成分とする。副成分として、例えば、Ｍｎ化合物、Ｆｅ化合物、Ｃｒ化合物、Ｃｏ化合物またはＮｉ化合物等が添加されたものを用いてもよい。 The material of the ceramic green sheet is mainly composed of dielectric ceramics such as BaTiO 3 , CaTiO 3 , SrTiO 3 or CaZrO 3 . As an auxiliary component, for example, a material to which a Mn compound, Fe compound, Cr compound, Co compound, Ni compound or the like is added may be used.
　第１および第２のセラミックグリーンシートは、誘電体セラミックスの原料粉末および有機バインダに適当な有機溶剤等を添加して混合することによって泥漿状のセラミックスラリーを作製し、ドクターブレード法等を用いて成形する。 The first and second ceramic green sheets are produced by adding a suitable organic solvent to the dielectric ceramic raw material powder and the organic binder and mixing them, and using a doctor blade method or the like. Mold.
　信号用内部電極２および接地用内部電極３用の導体ペーストは、上述したそれぞれの内部電極の導体材料（金属材料）の粉末に添加剤（誘電体材料）、バインダ、溶剤、分散剤等を加えて混練することで作製される。信号用内部電極２および接地用内部電極３の導電材料は、例えば、ニッケル（Ｎｉ）、銅（Ｃｕ）、銀（Ａｇ）、パラジウム（Ｐｄ）または金（Ａｕ）等の金属材料である。または、信号用内部電極２および接地用内部電極３は、これらの金属材料の１種以上を含む、例えば、Ａｇ－Ｐｄ合金等の合金材料である。信号用内部電極２および接地用内部電極３は、同一の金属材料または合金材料を用いてもよい。 The conductor paste for the signal internal electrode 2 and the ground internal electrode 3 is made by adding an additive (dielectric material), a binder, a solvent, a dispersing agent, etc. to the above-mentioned powder of the conductive material (metal material) of each internal electrode. And kneading. The conductive material of the signal internal electrode 2 and the ground internal electrode 3 is, for example, a metal material such as nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), or gold (Au). Alternatively, the signal internal electrode 2 and the ground internal electrode 3 are alloy materials including one or more of these metal materials, such as an Ag—Pd alloy. The signal internal electrode 2 and the ground internal electrode 3 may use the same metal material or alloy material.
　例えば、第１および第２のセラミックグリーンシートを図３に示すように順次積層する。そして、内部電極が形成されていないセラミックグリーンシートを積層方向（Ｚ方向）の最外層にそれぞれ積層して、図３に示すような積層体とする。 For example, first and second ceramic green sheets are sequentially laminated as shown in FIG. And the ceramic green sheet in which an internal electrode is not formed is each laminated | stacked on the outermost layer of a lamination direction (Z direction), and it is set as a laminated body as shown in FIG.
　このように積層された積層体は、プレスして一体化することよって、多数個の生積層体を含む大型の生積層体となる。この大型の生積層体を切断することによって、図１に示すような積層型コンデンサ１０の積層体１となる生積層体を得ることができる。大型の生積層体の切断は、例えば、ダイシングブレード等を用いて行なうことができる。 The laminated body thus laminated becomes a large green laminated body including a large number of raw laminated bodies by pressing and integrating. By cutting this large green laminate, a green laminate that becomes the laminate 1 of the multilayer capacitor 10 as shown in FIG. 1 can be obtained. The large green laminate can be cut using, for example, a dicing blade.
　そして、積層体１は、生積層体を、例えば、８００（℃）～１３００（℃）で焼成して得られる。焼成により、複数の第１および第２のセラミックグリーンシートは誘電体層１ｇとなり、信号用内部電極２の導体ペースト層は第１の信号用内部電極２ａおよび第２の信号用内部電極２ｂとなり、接地用内部電極３の導体ペースト層は接地用内部電極３となる。積層体１は、例えば、バレル研磨等の研磨手段を用いて角部または辺部が丸められることにより、角部または辺部が欠けにくいものとなる。 The laminate 1 is obtained by firing the raw laminate at, for example, 800 (° C.) to 1300 (° C.). By firing, the plurality of first and second ceramic green sheets become the dielectric layer 1g, the conductor paste layer of the signal internal electrode 2 becomes the first signal internal electrode 2a and the second signal internal electrode 2b, The conductive paste layer of the grounding internal electrode 3 becomes the grounding internal electrode 3. In the laminated body 1, for example, the corners or sides are not easily chipped by rounding the corners or sides using a polishing means such as barrel polishing.
　次に、第１の外部電極４ａおよび第２の外部電極４ｂは、例えば、積層体１の第１の端面１ｃおよび第２の端面１ｄに第１の外部電極４ａおよび第２の外部電極４ｂ用の導電ペーストを塗布して、焼き付けることによって形成する。また、第１の外部電極４ａおよび第２の外部電極４ｂ用の導電ペーストは、上述した第１の外部電極４ａおよび第２の外部電極４ｂの金属材料の粉末にバインダ、溶剤および分散剤等を加えて混練することで作製される。 Next, the first external electrode 4a and the second external electrode 4b are formed on the first end surface 1c and the second end surface 1d of the multilayer body 1 for the first external electrode 4a and the second external electrode 4b, for example. The conductive paste is applied and baked. In addition, the conductive paste for the first external electrode 4a and the second external electrode 4b is obtained by adding a binder, a solvent, a dispersant and the like to the powder of the metal material of the first external electrode 4a and the second external electrode 4b. In addition, it is produced by kneading.
　また、第１の接地用外部端子５ａおよび第２の接地用外部端子５ｂは、例えば、ローラ転写法を用いて、接地用外部端子５用の導電性ペーストを第１の側面１ｅおよび第２の側面１ｆに形成する。具体的には、ローラ転写法を用いて、接地用外部端子５用の導電性ペーストを第１の側面１ｅおよび第２の側面１ｆに転写することより、導電性ペーストは、第１の側面１ｅおよび第２の側面１ｆに設けられるとともに、第１の面１ａおよび第２の面１ｂに延在することになる。 Further, the first grounding external terminal 5a and the second grounding external terminal 5b are formed by using, for example, a roller transfer method to apply the conductive paste for the grounding external terminal 5 to the first side surface 1e and the second side surface 2e. It is formed on the side surface 1f. Specifically, the conductive paste is transferred to the first side face 1e and the second side face 1f by using a roller transfer method to transfer the conductive paste for the grounding external terminal 5 to the first side face 1e. And provided on the second side surface 1f and extending to the first surface 1a and the second surface 1b.
　外部電極４および接地用外部端子５は、表面の保護または積層型コンデンサ１０の実装基板との実装性の向上等のために、表面に金属層が形成される。金属層は、例えば、めっき法を用いて形成される。金属層は、例えば、ニッケル（Ｎｉ）めっき層、銅（Ｃｕ）めっき層、金（Ａｕ）めっき層または錫（Ｓｎ）めっき層等である。また、金属層は、単一のめっき層または複数のめっき層を外部電極４および接地用外部端子５の表面に形成することができる。例えば、外部電極４および接地用外部端子５は、金属層がニッケルめっき層および錫めっき層の積層体であってもよい。 The external electrode 4 and the grounding external terminal 5 are formed with a metal layer on the surface in order to protect the surface or improve the mountability of the multilayer capacitor 10 with the mounting substrate. The metal layer is formed using, for example, a plating method. The metal layer is, for example, a nickel (Ni) plating layer, a copper (Cu) plating layer, a gold (Au) plating layer, a tin (Sn) plating layer, or the like. The metal layer can be formed by forming a single plating layer or a plurality of plating layers on the surfaces of the external electrode 4 and the grounding external terminal 5. For example, the external electrode 4 and the grounding external terminal 5 may be a laminate in which the metal layer is a nickel plating layer and a tin plating layer.
　また、外部電極４および接地用外部端子５は、導体ペーストを焼き付ける方法以外に、蒸着法、めっき法またはスパッタリング法等の薄膜形成法を用いてもよい。 Further, the external electrode 4 and the grounding external terminal 5 may use a thin film forming method such as a vapor deposition method, a plating method, or a sputtering method in addition to the method of baking the conductor paste.
　本開示は、上述の一実施の形態の積層型コンデンサに限定されるものではなく、本開示の要旨を逸脱しない範囲において種々の変更等が可能である。 The present disclosure is not limited to the multilayer capacitor of the above-described embodiment, and various modifications can be made without departing from the gist of the present disclosure.
１　積層体
１ａ　第１の面
１ｂ　第２の面
１ｃ　第１の端面
１ｄ　第２の端面
１ｅ　第１の側面
１ｆ　第２の側面
１ｇ　誘電体層
２　信号用内部電極
２ａ　第１の信号用内部電極
２ｂ　第２の信号用内部電極
３　接地用内部電極
４　外部電極
４ａ　第１の外部電極
４ｂ　第２の外部電極
５　接地用外部端子
５ａ　第１の接地用外部端子
５ｂ　第２の接地用外部端子
６ａ　第１のキャパシタ部
６ｂ　第２のキャパシタ部
７　凹み
８　実装基板
８ａ　入力端子
８ｂ　ＧＮＤ端子
１０、１０Ａ、１０Ｂ　積層型コンデンサ
  DESCRIPTION OF SYMBOLS 1 Laminated body 1a 1st surface 1b 2nd surface 1c 1st end surface 1d 2nd end surface 1e 1st side surface 1f 2nd side surface 1g Dielectric layer 2 Signal internal electrode 2a 1st signal internal electrode 2b Second signal internal electrode 3 Ground internal electrode 4 External electrode 4a First external electrode 4b Second external electrode 5 Ground external terminal 5a First ground external terminal 5b Second ground external terminal 6a First capacitor portion 6b Second capacitor portion 7 Recess 8 Mounting substrate 8a Input terminal 8b GND terminal 10, 10A, 10B Multilayer capacitor

Claims (4)

  1. 　複数の誘電体層が積層された、一対の第１の面および第２の面、一対の第１の側面および第２の側面、一対の第１の端面および第２の端面を有する直方体状の積層体と、
    該積層体内の前記第１の面、前記第２の面と平行となる同一面内に間隔をおいて配置された、前記第１の端面に引き出された第１の信号用内部電極および前記第２の端面に引き出された第２の信号用内部電極を含む信号用内部電極と、
    積層方向に隣り合う前記信号用内部電極の間に積層方向に前記第１の信号用内部電極および前記第２の信号用内部電極に対向して配置され、前記第１の側面および第２の側面に引き出された接地用内部電極と、
    前記積層体の前記第１の端面に配置され、前記第１の信号用内部電極に接続された第１の外部電極および前記第２の端面に配置され、前記第２の信号用内部電極に接続された第２の外部電極を含む外部電極と、
    前記積層体の前記第１の側面に配置され、前記接地用内部電極に接続された第１の接地用外部端子および前記第２の側面に配置され、前記接地用内部電極に接続された第２の接地用外部端子を含む接地用外部端子と、
    積層方向に従って配列され、複数の前記第１の信号用内部電極と複数の前記接地用内部電極とが前記誘電体層を挟んで交互に積層された第１のキャパシタ部と、
    積層方向に従って配列され、複数の前記第２の信号用内部電極と複数の前記接地用内部電極とが前記誘電体層を挟んで交互に積層された第２のキャパシタ部と、を備えており、
    第１のキャパシタ部は、第２のキャパシタ部よりも容量が小さいことを特徴とする積層型コンデンサ。     A rectangular parallelepiped having a pair of first and second surfaces, a pair of first side surfaces and a second side surface, a pair of first end surfaces and a second end surface, wherein a plurality of dielectric layers are stacked. A laminate,
    The first signal internal electrode led out to the first end face and spaced apart in the same plane parallel to the first plane and the second plane in the laminated body, and the first A signal internal electrode including a second signal internal electrode drawn out to the end face of 2;
    Between the signal internal electrodes adjacent to each other in the stacking direction, the first signal internal electrode and the second signal internal electrode are arranged to face each other in the stacking direction, and the first side surface and the second side surface are disposed. An internal electrode for grounding drawn to
    A first external electrode disposed on the first end face of the stacked body and connected to the first signal internal electrode and a second end face disposed on the first end face and connected to the second signal internal electrode An external electrode including a second external electrode formed;
    A first grounding external terminal disposed on the first side surface of the laminate and connected to the grounding internal electrode, and a second grounding terminal disposed on the second side surface and connected to the grounding internal electrode. A grounding external terminal including the grounding external terminal,
    A plurality of first signal internal electrodes and a plurality of ground internal electrodes arranged alternately according to the stacking direction, and alternately stacked with the dielectric layer in between;
    A plurality of second signal internal electrodes and a plurality of ground internal electrodes arranged alternately according to the stacking direction, and a second capacitor portion stacked alternately with the dielectric layer in between,
    The first capacitor portion has a smaller capacity than the second capacitor portion.
  2. 　前記接地用内部電極は、前記積層体の積層方向に位置する前記第１の面または前記第２の面と前記信号用内部電極との間に積層方向に前記信号用内部電極に対向して配置されていることを特徴とする請求項１に記載の積層型コンデンサ。 The grounding internal electrode is disposed opposite to the signal internal electrode in the stacking direction between the first surface or the second surface located in the stacking direction of the stacked body and the signal internal electrode. The multilayer capacitor according to claim 1, wherein the multilayer capacitor is provided.
  3. 　前記積層体の積層方向に位置する前記第１の面または前記第２の面は、隣り合う前記第１の信号用内部電極と前記第２の信号用内部電極との間の領域に対応する部分が凹んでいることを特徴とする請求項１または請求項２に記載の積層型コンデンサ。 The first surface or the second surface located in the stacking direction of the stacked body corresponds to a region between the adjacent first signal internal electrode and the second signal internal electrode The multilayer capacitor according to claim 1, wherein the capacitor is recessed.
  4. 　前記積層体の積層方向に直交する方向に位置する前記第１の側面または前記第２の側面には、隣り合う前記第１の信号用内部電極と前記第２の信号用内部電極との間の領域に対応する部分が凹んでいることを特徴とする請求項１乃至請求項３のいずれかに記載の積層型コンデンサ。
          The first side surface or the second side surface located in a direction orthogonal to the stacking direction of the stacked body is between the first signal internal electrode and the second signal internal electrode adjacent to each other. 4. The multilayer capacitor according to claim 1, wherein a portion corresponding to the region is recessed.
PCT/JP2017/030725 2016-08-29 2017-08-28 Stacked capacitor WO2018043397A1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022541973A (en) * 2019-04-25 2022-09-29 キョーセラ・エイブイエックス・コンポーネンツ・コーポレーション Low inductance component
JP7423340B2 (en) 2020-02-18 2024-01-29 太陽誘電株式会社 Laminated ceramic electronic components, tape packaging and circuit boards

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000299249A (en) * 1999-04-14 2000-10-24 Maruwa Kck:Kk Multilayer capacitor and manufacture thereof
JP2015216201A (en) * 2014-05-09 2015-12-03 株式会社村田製作所 Multilayer capacitor and method for using the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000299249A (en) * 1999-04-14 2000-10-24 Maruwa Kck:Kk Multilayer capacitor and manufacture thereof
JP2015216201A (en) * 2014-05-09 2015-12-03 株式会社村田製作所 Multilayer capacitor and method for using the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022541973A (en) * 2019-04-25 2022-09-29 キョーセラ・エイブイエックス・コンポーネンツ・コーポレーション Low inductance component
JP7423340B2 (en) 2020-02-18 2024-01-29 太陽誘電株式会社 Laminated ceramic electronic components, tape packaging and circuit boards

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