KR102345117B1 - Multilayered capacitor - Google Patents

Abstract

It includes first and second surfaces facing each other and third and fourth surfaces connected to the first and second surfaces and facing each other, wherein the third and fourth surfaces are alternately disposed with a dielectric layer and the dielectric layer interposed therebetween. a capacitor body exposed through a surface and including first and second internal electrodes exposed through the first and second surfaces, respectively; and an amorphous dielectric thin film formed on at least a portion of the third and fourth surfaces of the capacitor body to cover the exposed portions of the first and second internal electrodes.

Description

Multilayer Capacitor {MULTILAYERED CAPACITOR}

The present invention relates to a multilayer capacitor.

Multilayer capacitors are widely used as parts of mobile communication devices such as computers, PDAs, and mobile phones because of their small size, high capacity, and easy mounting.

Recently, as electronic products are miniaturized and multifunctional, increasing the effective volume ratio, which means the ratio of the volume contributing to the capacity to the total volume, has become a major issue in the field of multilayer capacitors.

As a conventional technique for increasing the effective volume ratio, a technique has been developed in which a side portion of a capacitor body formed by lamination of dielectric layers is cut off to expose internal electrodes as a cut surface, and then a dielectric sheet is transferred to the cut surface and fired.

However, in the case of this sheet transfer method, not only a lot of pressure is applied to the capacitor body during the manufacturing process, but also a lot of processes are added to form dielectric sheets on both sides of the body, so the number of defects in the process increases and mass production is low. and there are many difficulties in preventing quality dispersion. In addition, in the case of the sheet transfer method, since the firing process is performed after the sheet transfer, the dielectric layer and the dielectric sheet must inevitably be made of the same dielectric. there was.

One of several objects of the present invention is to provide a high-capacity multilayer capacitor having excellent moisture resistance.

One aspect of the present invention includes first and second surfaces facing each other and third and fourth surfaces connected to the first and second surfaces and facing each other, and arranged alternately with a dielectric layer and the dielectric layer interposed therebetween. a capacitor body comprising first and second internal electrodes exposed through the third and fourth surfaces and exposed through the first and second surfaces, respectively, and the third and fourth surfaces of the capacitor body; Provided is a multilayer capacitor including an amorphous dielectric thin film formed to cover exposed portions of first and second internal electrodes.

According to another aspect of the present invention, a first ceramic green sheet in which a plurality of stripe-type first internal electrode patterns are formed at predetermined intervals and a second ceramic green sheet in which a plurality of stripe-type second internal electrode patterns are formed at predetermined intervals are provided. forming a ceramic green sheet laminate by stacking the first ceramic green sheet and the second ceramic green sheet so that the stripe-shaped first internal electrode pattern and the stripe-shaped second internal electrode pattern intersect. , the ceramic green sheet laminate is cut in a direction perpendicular to the formation direction of the first and second internal electrode patterns to include a plurality of first and second internal electrodes having a predetermined width, and the plurality of first internal electrodes and obtaining a rod-shaped laminate having third and fourth surfaces exposed in the width direction of the second internal electrode, wherein the rod-shaped laminate is arranged in a direction parallel to the formation direction of the first and second internal electrode patterns. cutting to obtain a laminate having first and second surfaces in which one ends of the plurality of first and second internal electrodes are exposed, respectively, sintering the laminate to obtain a capacitor body, and the capacitor body It provides a method of manufacturing a multilayer capacitor comprising the step of forming an amorphous dielectric thin film on the surface of the.

The multilayer capacitor according to an embodiment of the present invention has an advantage in that the effective negative ratio is high and thus the capacitor capacity is large.

In addition, the multilayer capacitor according to an embodiment of the present invention has the advantage of excellent moisture resistance reliability.

1 is a perspective view schematically illustrating a multilayer capacitor according to an embodiment of the present invention.
FIG. 2 is a perspective view schematically illustrating a capacitor body in FIG. 1 in which first and second external electrodes and a dielectric thin film are excluded.
3 is a cross-sectional view taken along line A-A' of FIG. 1 , and FIG. 4 is a cross-sectional view taken along line B-B' of FIG. 1 .
5 to 13 show an example of a schematic manufacturing process of a multilayer capacitor according to an embodiment of the present invention.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present embodiments may be modified in other forms or various embodiments may be combined with each other, and the scope of the present invention is not limited to the embodiments described below. In addition, the present embodiments are provided to more completely explain the present invention to those of ordinary skill in the art. For example, shapes and sizes of elements in the drawings may be exaggerated for clearer description.

Meanwhile, the expression “one example” used in this specification does not mean the same embodiment as each other, and is provided to emphasize and explain different unique features. However, the embodiments presented in the description below are not excluded from being implemented in combination with features of other embodiments. For example, even if a matter described in a particular embodiment is not described in another embodiment, it may be understood as a description related to another embodiment unless a description contradicts or contradicts the matter in another embodiment.

1 is a perspective view schematically showing a multilayer capacitor according to an embodiment of the present invention, FIG. 2 is a perspective view schematically showing a capacitor body in FIG. 1 , in which first and second external electrodes and a dielectric thin film are excluded, and FIG. 3 is a cross-sectional view taken along line A-A' of FIG. 1 , and FIG. 4 is a cross-sectional view taken along line B-B' of FIG. 1 .

1, in the following description, the 'length' direction may be defined as the 'L' direction of FIG. 1, the 'width' direction may be defined as the 'W' direction, and the 'thickness' direction may be defined as the 'T' direction. . Here, the 'thickness direction' may be used as the same concept as the direction in which the dielectric layers are stacked, that is, the 'stacking direction'.

Hereinafter, a multilayer capacitor, which is an aspect of the present invention, will be described in detail with reference to FIGS. 1 to 4 .

1 to 4 , a multilayer capacitor according to an embodiment of the present invention includes a capacitor body 110 ; It may be configured to include an amorphous dielectric thin film 113 and first and second external electrodes 131 and 132 .

The shape of the capacitor body 110 is not particularly limited, but as shown in FIG. 2 , the capacitor body 110 may have a hexahedral shape. Due to the firing shrinkage of the dielectric powder during chip firing, the capacitor body 110 may not have a perfect hexahedral shape, but may have a substantially hexahedral shape. In this case, the capacitor body 110 is connected to the first and second surfaces S1 and S2 opposite to each other in the longitudinal direction, the first and second surfaces, and third and fourth surfaces opposite to each other in the width direction ( S3 and S4), and may have fifth and sixth surfaces S5 and S6 connected to the first and second surfaces and facing each other in the height direction.

The capacitor body 110 includes first and second internal electrodes 121, which are alternately disposed with a dielectric layer 112 and the dielectric layer 112 interposed therebetween and exposed through the first and second surfaces S1 and S2, respectively. 122). The plurality of dielectric layers 112 constituting the capacitor body 110 are in a sintered state, and the boundary between adjacent dielectric layers may be integrated to the extent that it cannot be confirmed without using a scanning electron microscope (SEM).

The dielectric layer 112 may include a crystalline ceramic powder having a high dielectric constant, for example, barium titanate (BaTiO ₃ )-based, lead composite perovskite-based, or strontium titanate (SrTiO ₃ )-based powder, and the like, preferably titanic acid. A barium (BaTiO ₃ )-based powder may be used, but the present invention is not necessarily limited thereto. Meanwhile, at least one of a ceramic additive, an organic solvent, a plasticizer, a binder, and a dispersant may be further added to the dielectric layer 112 together with the crystalline ceramic powder as needed.

At least one of the fifth and sixth surfaces S5 and S6 of the capacitor body 110 may include a cover region in which an internal electrode pattern is not formed. Such a cover region may be provided by laminating one or two or more dielectric layers on which an electrode pattern is not formed on the top and/or bottom of the capacitor body. Basically, the first and second internal electrodes ( 121, 122) may serve to prevent damage.

The first and second internal electrodes 121 and 122 are electrodes having different polarities, and are alternately disposed in the thickness direction with the dielectric layer 112 in the capacitor body 110 interposed therebetween. and through the second surfaces S1 and S2, respectively.

The first and second internal electrodes 121 and 122 may be formed by printing a conductive paste including a conductive metal to a predetermined thickness on the dielectric layer 112 , and may be formed from each other by the dielectric layer 112 disposed therebetween. may be electrically insulated.

The metal included in the conductive paste may be, for example, nickel (Ni), copper (Cu), palladium (Pd), or an alloy thereof, but the present invention is not limited thereto.

In addition, the conductive paste may be printed by a screen printing method, a gravure printing method, or the like, but the present invention is not necessarily limited thereto.

An area overlapping each other in the thickness direction of the first and second internal electrodes 121 and 122 is related to the formation of capacitance of the capacitor, and as the area increases, the capacitance of the capacitor increases. As can be seen from FIG. 2 , in the case of the multilayer capacitor according to the present invention, since each of the first and second internal electrodes 121 and 122 is formed entirely in the width direction of the dielectric layer 112 , the overlapping area of the internal electrodes is increased. This can be maximized, and accordingly, there is an advantage in that the capacity of the capacitor compared to the volume of the multilayer capacitor is large.

The amorphous dielectric thin film 113 is formed on at least the third and fourth surfaces of the capacitor body to prevent external exposure of the first and second internal electrodes 121 and 122 to implement electrical insulation, and It prevents moisture from penetrating into the interior and contributes to the improvement of the moisture resistance reliability of the multilayer capacitor.

In general, as a dielectric constituting a multilayer capacitor, a crystalline dielectric is used to secure a high dielectric constant, but the crystalline dielectric has a disadvantage in that electrical insulation is low due to weak withstand voltage characteristics. Accordingly, in the present invention, the electrical insulation of the first and second internal electrodes is implemented by an amorphous dielectric thin film, and accordingly, the advantage of achieving electrical insulation of the first and second internal electrodes even with a very thin thickness have.

The amorphous dielectric thin film 113 may be formed over an area of the capacitor body 110 in which the first and second external electrodes 131 and 132 are not formed, but is not limited thereto.

As the dielectric material forming the amorphous dielectric thin film 113 , a material having excellent moisture resistance is preferably selected, and examples of the dielectric material having excellent moisture resistance include Al ₂ O ₃ , Si ₃ N ₄ , SiO _{2 ,} and perylene. (parylene). This is because, if moisture resistance is poor, the amorphous dielectric thin film must be formed to be thicker than a certain level in order to secure reliability, and in this case, it is difficult to achieve the purpose of maximizing the overlapping area of the internal electrodes.

However, as described above, in the case of the conventional sheet transfer method, the dielectric layer and the dielectric sheet must inevitably be made of the same dielectric in that the firing process is performed after the dielectric sheet is transferred. At the same time, there were problems that were difficult to achieve.

However, in the case of the present invention, as will be described later, since the amorphous dielectric thin film 113 is formed by deposition, there is no limitation to the type of dielectric included in the amorphous dielectric thin film 113 and the amorphous dielectric thin film 113 is not limited. Since ultrathin (113) is possible, there is an advantage in that capacitor capacity improvement and moisture resistance reliability can be achieved at the same time.

According to a non-limiting example, the maximum thickness d of the amorphous dielectric thin film 113 may be 5 μm or less (excluding 0 μm), and more preferably, 5 μm or less (excluding 0 μm). If the maximum thickness d of the amorphous dielectric thin film 113 exceeds 5 μm, the dielectric thin film may become unstable due to internal stress of the dielectric thin film.

The first and second external electrodes 131 and 132 are respectively formed on the first and second surfaces S1 and S2 of the capacitor body 110 , and first and second exposed through the first and second surfaces. They are respectively connected to the internal electrodes 121 and 122 .

The first and second external electrodes 131 and 132 may be formed of a conductive paste including a conductive metal.

In addition, the conductive metal may be, for example, nickel (Ni), copper (Cu), palladium (Pd), gold (Au), or an alloy thereof, but the present invention is not limited thereto.

Hereinafter, a method for manufacturing a multilayer capacitor, which is another aspect of the present invention, will be described in detail.

5 to 13 show an example of a schematic manufacturing process of a multilayer capacitor according to an embodiment of the present invention.

First, as shown in FIG. 5 , a plurality of stripe-shaped first internal electrode patterns 221a are formed on the ceramic green sheet 212a with a predetermined interval d1 . In this case, the plurality of stripe-shaped first internal electrode patterns 221a may be formed parallel to each other. In this case, the predetermined distance d1 corresponds to twice the distance for the inner electrode to be insulated from the outer electrode having different polarities.

The ceramic green sheet 212a may be formed of a ceramic paste including crystalline ceramic powder, an organic solvent, and an organic binder. The crystalline ceramic powder is a material having a high dielectric constant, and barium titanate (BaTiO ₃ )-based, lead composite perovskite-based, or strontium titanate (SrTiO ₃ )-based powder may be used, and preferably barium titanate (BaTiO3)-based powder. may be used, but is not necessarily limited thereto. When the ceramic green sheet 212a is fired, it becomes a dielectric layer constituting the capacitor body.

The stripe-shaped first internal electrode pattern 221a may be formed of an internal electrode paste including a conductive metal. The conductive metal is not limited thereto, but may be nickel (Ni), copper (Cu), palladium (Pd), or an alloy thereof.

A method of forming the stripe-type first internal electrode pattern 221a on the ceramic green sheet 212a is not particularly limited, but may be formed by, for example, a printing method such as a screen printing method or a gravure printing method.

Also, although not shown, a plurality of stripe-type second internal electrode patterns 222a may be formed on another ceramic green sheet 212a at predetermined intervals.

Hereinafter, the ceramic green sheet on which the first internal electrode pattern 221a is formed may be referred to as a first ceramic green sheet, and the ceramic green sheet on which the second internal electrode pattern 222a is formed may be referred to as a second ceramic green sheet. have.

Next, as shown in FIG. 6 , the first and second ceramic green sheets are alternately stacked so that the stripe-shaped first internal electrode pattern 221a and the stripe-shaped second internal electrode pattern 222a are cross-stacked to form a ceramic material. A green sheet laminate 211a may be formed. The stripe-shaped first internal electrode pattern 221a may form a first internal electrode 121 , and the stripe-shaped second internal electrode pattern 222a may form a second internal electrode 122 .

In this case, although not shown, a cover area in which a plurality of ceramic green sheets on which internal electrode patterns are not formed are stacked may be provided on at least one of the upper and lower surfaces of the ceramic green sheet laminate 211a.

7 is a cross-sectional view illustrating a ceramic green sheet laminate 211a in which first and second ceramic green sheets are laminated according to an embodiment of the present invention, and FIG. 8 is a cross-sectional view in which the first and second ceramic green sheets are laminated. It is a perspective view which shows the ceramic green sheet laminated body 211a.

7 and 8 , a first ceramic green sheet on which a plurality of parallel stripe-type first internal electrode patterns 221a are printed and a second ceramic green sheet on which a plurality of parallel stripe-type second internal electrode patterns 222a are printed 2 Ceramic green sheets are alternately stacked on each other.

In this case, a predetermined distance between the center of each of the stripe-shaped first internal electrode patterns 221a printed on the first ceramic green sheet and the plurality of stripe-shaped second internal electrode patterns 222a printed on the second ceramic green sheet is used. may be stacked so that the width direction centers of the intervals of .

Next, as shown in FIG. 8 , the ceramic green sheet laminate 211a may be cut in a direction perpendicular to the formation direction of the first and second internal electrode patterns 221a and 222a. That is, the ceramic green sheet laminate 211a may be cut into the bar-type laminate 211b along the C1-C1 cutting line.

More specifically, the stripe-shaped first internal electrode pattern 221a and the stripe-shaped second internal electrode pattern 222a may be cut in the longitudinal direction to be divided into a plurality of internal electrodes having a constant width. At this time, the laminated ceramic green sheet is also cut together with the internal electrode pattern. Accordingly, the dielectric layer may be formed to have the same width as that of the internal electrode.

In this case, the first and second internal electrodes are exposed through the cut surfaces of the rod-shaped laminate 211b, and the cut surfaces of the rod-shaped stacked body may be referred to as third and fourth surfaces of the rod-shaped laminate, respectively.

Next, as shown in FIG. 9 , the rod-shaped laminate 211b may be cut in a direction parallel to the formation direction of the first and second internal electrodes. That is, the rod-shaped laminate 211b is cut to fit individual chip sizes along the C2-C2 cutting line to obtain an individual laminate 211c.

More specifically, the C2-C2 cut line is the center of each of the stripe-shaped first internal electrode patterns 221a printed on the first ceramic green sheet in the width direction and the plurality of stripe-shaped second internal electrodes printed on the second ceramic green sheet. Penetrating through the center of the width direction with a predetermined interval between the patterns 222a, and accordingly, the individual stacked body 221c has first and second surfaces in which one ends of the first and second internal electrodes are exposed, respectively.

Next, as shown in FIG. 10 , the individual laminates 221c are fired to obtain a capacitor body 221 . _{The firing may be performed in an N 2} -H ₂ atmosphere of 1100° C. to 1300° C., but is not necessarily limited thereto.

Next, as shown in FIG. 11 , an amorphous dielectric thin film 213 is formed on the surface of the capacitor body 221 . The amorphous dielectric thin film 213 may be formed by deposition, and in this case, as described above, there is no limitation on the type of dielectric included in the amorphous dielectric thin film 213 , and the polarity of the amorphous dielectric thin film 213 is not limited. Since it can be thinned, there is an advantage in that it is possible to improve capacitor capacity and secure moisture resistance at the same time.

The amorphous dielectric thin film 213 may _{include at least one dielectric selected from the group consisting of Al 2} O ₃ , Si ₃ N ₄ , SiO ₂ and parylene, and thus, improving capacitor capacity and securing moisture resistance. objectives can be achieved at the same time.

Next, as shown in FIG. 12 , the amorphous dielectric thin film 213 formed on the first and second surfaces of the capacitor body 221 is removed. This is to form the first and second external electrodes, as will be described later. A specific method of removing the amorphous dielectric thin film 213 is not particularly limited, but according to one non-limiting example, wet etching or sand blasting may be used.

Next, as shown in FIG. 13 , first and second external electrodes 231 and 232 are formed on the first and second surfaces of the capacitor body 221 , respectively. The first and second external electrodes 231 and 232 are respectively connected to the first and second internal electrodes.

The first and second external electrodes 231 and 232 may be formed of a conductive paste including a conductive metal. The conductive metal may be, for example, nickel (Ni), copper (Cu), palladium (Pd), gold (Au), or an alloy thereof, but the present invention is not limited thereto.

The present invention is not limited by the above-described embodiments and the accompanying drawings, but is intended to be limited by the appended claims. Therefore, various types of substitution, modification and change will be possible by those skilled in the art within the scope not departing from the technical spirit of the present invention described in the claims, and it is also said that it falls within the scope of the present invention. something to do.

110: capacitor body
112: dielectric layer
113: amorphous dielectric thin film
121, 122: first and second internal electrodes
131, 132: first and second external electrodes
211: capacitor body
211a: ceramic green sheet laminate
211b: rod-shaped laminate
211c: Individual Laminate
212a: first and second ceramic green sheets
213: amorphous dielectric thin film
221a: stripe-type first internal electrode pattern
222a: stripe-type second internal electrode pattern
231, 232: first and second external electrodes

Claims (7)

It includes first and second surfaces facing each other and third and fourth surfaces connected to the first and second surfaces and facing each other, the third and fourth surfaces being alternately disposed with a dielectric layer and the dielectric layer interposed therebetween. a capacitor body exposed through a surface and including first and second internal electrodes exposed through the first and second surfaces, respectively;
first and second external electrodes respectively formed on first and second surfaces of the capacitor body and respectively connected to first and second internal electrodes exposed through the first and second surfaces; and
Exposed portions of the first and second internal electrodes are covered in regions where the first and second external electrodes are not formed on the third and fourth surfaces of the capacitor body to directly communicate with the first and second internal electrodes an amorphous dielectric film formed to be in contact; including,
The dielectric layer includes a crystalline ceramic, and the amorphous dielectric layer includes at least one selected from the group consisting of _{Al 2} O ₃ , Si ₃ N ₄ , SiO _{2 and parylene,}
The maximum thickness of the amorphous dielectric film is 5 μm or less (excluding 0 μm), the multilayer capacitor.
delete According to claim 1,
wherein the amorphous dielectric film is formed by vapor deposition.
4. The method of claim 3,
The deposition is a multilayer capacitor in any one of Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), and Molecular Vapor Deposition (MVD).
delete delete According to claim 1,
A multilayer capacitor further comprising a cover region formed of a dielectric layer on upper and lower surfaces of the capacitor body in a stacking direction.

Images