JP2005012199A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

Info

Publication number
JP2005012199A
JP2005012199A JP2004155066A JP2004155066A JP2005012199A JP 2005012199 A JP2005012199 A JP 2005012199A JP 2004155066 A JP2004155066 A JP 2004155066A JP 2004155066 A JP2004155066 A JP 2004155066A JP 2005012199 A JP2005012199 A JP 2005012199A
Authority
JP
Japan
Prior art keywords
semiconductor device
passive
semiconductor
substrate
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2004155066A
Other languages
Japanese (ja)
Other versions
JP4740555B2 (en
Inventor
Hitoshi Kawaguchi
均 川口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Bakelite Co Ltd
Original Assignee
Sumitomo Bakelite Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Bakelite Co Ltd filed Critical Sumitomo Bakelite Co Ltd
Priority to JP2004155066A priority Critical patent/JP4740555B2/en
Publication of JP2005012199A publication Critical patent/JP2005012199A/en
Application granted granted Critical
Publication of JP4740555B2 publication Critical patent/JP4740555B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92227—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19103—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor package having a high space efficiency in a semiconductor package having a passive element incorporated therein in addition to a semiconductor element. <P>SOLUTION: In a method of manufacturing a semiconductor device, in a semiconductor package having a passive element 24 incorporated therein, the passive element that has been mounted on a substrate 20 is polished and thinned, and height variation of the top is suppressed, and then a semiconductor element 22 is mounted on the polished surface of the passive element. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、半導体チップと受動部品をひとつのパッケージに搭載した半導体装置に関するものであり、特に、小型・軽量化及び高機能・大容量化を目的とする半導体チップの3次元積層技術に係わるものである。   The present invention relates to a semiconductor device in which a semiconductor chip and passive components are mounted in one package, and particularly relates to a three-dimensional stacking technique of semiconductor chips for the purpose of miniaturization, weight reduction, high functionality, and large capacity. It is.

近年の電子機器の高機能化並びに軽薄短小化の要求に伴い、電子部品の高密度集積化、さらには高密度実装化が進んできている。これらの電子機器に使用される半導体パッケージは、小型化かつ多ピン化してきており、また、半導体パッケージを含めた電子部品を実装する、実装用基板も小型化してきている。さらには電子機器への収納性を高めるため、リジット基板とフレキシブル基板を積層し一体化して、折り曲げを可能としたリジットフレックス基板が、実装用基板として使われるようになってきている。   With recent demands for higher functionality and lighter, thinner and smaller electronic devices, electronic components have been increasingly integrated and densely packaged. Semiconductor packages used in these electronic devices have been reduced in size and increased in pin count, and mounting substrates on which electronic components including the semiconductor package are mounted have also been reduced in size. Furthermore, in order to improve the storage property in an electronic device, a rigid flex board that can be bent by laminating and integrating a rigid board and a flexible board has been used as a mounting board.

半導体パッケージはその小型化に伴って、従来のようなリードフレームを使用した形態のパッケージでは、小型化に限界がきているため、最近では回路基板上にチップを実装したものとして、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）や、ＣＳＰ（Ｃｈｉｐ Ｓｃａｌｅ Ｐａｃｋａｇｅ）と言った、エリア実装型の新しいパッケージ方式が提案されている。これらの半導体パッケージにおいて、半導体チップの電極と従来型半導体パッケージのリードフレームの機能を有する、半導体パッケージ用基板と呼ばれる、プラスチックやセラミックス等各種材料を使って構成される、サブストレートの端子との電気的接続方法として、ワイヤーボンディング方式やＴＡＢ（Ｔａｐｅ Ａｕｔｏｍａｔｅｄ Ｂｏｎｄｉｎｇ）方式、さらにはＦＣ（Ｆｒｉｐ Ｃｈｉｐ）方式などが知られているが、最近では、半導体パッケージの小型化に有利なＦＣ接続方式を用いた、ＢＧＡやＣＳＰの構造が盛んに提案されている。   With the miniaturization of semiconductor packages, the conventional package using a lead frame has a limit on miniaturization. Therefore, recently, it is assumed that a chip is mounted on a circuit board, and BGA (Ball Grid) is used. Array) and a new area mounting type package system such as CSP (Chip Scale Package) have been proposed. In these semiconductor packages, the electrical connection between the electrodes of the semiconductor chip and the terminals of the substrate, which is made of various materials such as plastics and ceramics, called the semiconductor package substrate, has the function of the lead frame of the conventional semiconductor package. As a general connection method, a wire bonding method, a TAB (Tape Automated Bonding) method, and an FC (Flip Chip) method are known, but recently, an FC connection method advantageous for miniaturization of a semiconductor package has been used. BGA and CSP structures have been actively proposed.

しかしながら、上記工法では一つの半導体パッケージに対し半導体素子を一つしか収納できないため、半導体パッケージの小型化には自ずと限界がある。
加えて半導体素子が動作するために必要な受動素子を半導体パッケージの外部に配置するため、電子機器の小型化に限界が生じると共に、配線長が長くなるため高速信号を扱う場合には設計上の制約が大きくなってきている。 However, since the above method can accommodate only one semiconductor element in one semiconductor package, there is a limit to downsizing the semiconductor package.
In addition, since passive elements necessary for the operation of the semiconductor elements are arranged outside the semiconductor package, there is a limit to miniaturization of electronic devices, and the wiring length is long, so that high-speed signals are handled when designing. The constraints are getting bigger.

このため、半導体パッケージに受動素子を内蔵する検討が種々行われており、半導体パッケージ内部の半導体素子の周辺に受動素子を配置する方法（特許文献１）や半導体素子上に受動素子を形成する方法（特許文献２）が提案されているが、搭載できる小型化や受動素子数に限界があった。
特公２０００−１２７６９号公報 特公平８−１６２６０８号公報 For this reason, various studies have been made to incorporate a passive element in a semiconductor package. A method of disposing a passive element around a semiconductor element in a semiconductor package (Patent Document 1) and a method of forming a passive element on a semiconductor element. (Patent Document 2) has been proposed, but there are limits to the size and number of passive elements that can be mounted.
Japanese Patent Publication No. 2000-12769 Japanese Patent Publication No. 8-162608

本発明は、従来のこのような問題点を解決するためになされたもので、その目的とするところは、半導体パッケージの容積を抑えたまま受動態素子を多数内蔵した半導体パッケージを効率よく製造する方法を提供することにある。   The present invention has been made to solve such a conventional problem, and an object of the present invention is to efficiently manufacture a semiconductor package containing a large number of passive elements while keeping the volume of the semiconductor package small. Is to provide.

発明者らは種々検討の結果、回路形成した基板の上に機能面が基板と正対する向きで受動素子を実装した後、研磨することにより、半導体パッケージに内蔵された際の受動素子の高さを抑制すると共に、実装ばらつきにより生じる基板上での受動素子同士の高さばらつきを均一にすることにより、複数の受動素子の上に半導体素子を搭載する技術を発明した。   As a result of various studies, the inventors have mounted a passive element on a circuit-formed substrate so that the functional surface faces the substrate, and then polishing the substrate to polish the height of the passive element when incorporated in a semiconductor package. Invented a technique for mounting a semiconductor element on a plurality of passive elements by suppressing the above-mentioned and making the height variations of the passive elements on the substrate caused by mounting variations uniform.

すなわち本発明は、
［１］ 回路形成された基板上に実装された受動素子の上に半導体素子が搭載されていることを特徴とする半導体装置、
［２］ 受動素子が表面実装型の抵抗素子及び／又は薄膜コンデンサーである［１］項記載の半導体素子、
［３］ 抵抗素子の抵抗回路形成面及び／又は薄膜コンデンサーの薄膜コンデンサー形成面が回路形成された基板と正対している［２］項記載の半導体素子、
［４］ 回路形成された基板上に実装された受動素子の上面が研磨されることにより、受動素子の高さが低減され、かつ受動素子の高さが略同一である［１］項記載の半導体装置、
［５］ 回路形成された基板上に受動素子を実装し、さらに受動素子の上に半導体素子が搭載することを特徴とする半導体装置の製造方法、
［６］ 受動素子が表面実装型の抵抗素子及び／又は薄膜コンデンサーである［５］項記載の半導体素子の製造方法、
［７］ 抵抗素子の抵抗回路形成面及び／又は薄膜コンデンサーの薄膜コンデンサー形成面が回路形成された基板と正対している［６］項記載の半導体素子の製造方法、
［８］ 回路形成された基板上に実装された受動素子の上面を研磨することにより、受動素子の高さを低減し、かつ受動素子の高さを略同一にする［５］項記載の半導体装置の製造方法を提供する。 That is, the present invention
[1] A semiconductor device, wherein a semiconductor element is mounted on a passive element mounted on a circuit-formed substrate,
[2] The semiconductor element according to item [1], wherein the passive element is a surface-mounted resistor element and / or a thin film capacitor,
[3] The semiconductor element according to item [2], wherein the resistance circuit formation surface of the resistance element and / or the thin film capacitor formation surface of the thin film capacitor faces the substrate on which the circuit is formed,
[4] The height of the passive element is reduced by polishing the upper surface of the passive element mounted on the circuit-formed substrate, and the height of the passive element is substantially the same. Semiconductor devices,
[5] A method of manufacturing a semiconductor device, wherein a passive element is mounted on a circuit-formed substrate, and further a semiconductor element is mounted on the passive element.
[6] The method for manufacturing a semiconductor element according to [5], wherein the passive element is a surface-mounted resistance element and / or a thin film capacitor,
[7] The method for manufacturing a semiconductor element according to [6], wherein the resistance circuit forming surface of the resistance element and / or the thin film capacitor forming surface of the thin film capacitor is directly opposed to the substrate on which the circuit is formed.
[8] The semiconductor according to item [5], wherein the height of the passive element is reduced and the height of the passive element is made substantially the same by polishing the upper surface of the passive element mounted on the circuit-formed substrate. An apparatus manufacturing method is provided.

具体的には、本発明に係る半導体装置は、基板と、前記基板上に実装される複数の受動素子と、前記受動素子の表面（上面）に積層される半導体素子と、を含む。   Specifically, a semiconductor device according to the present invention includes a substrate, a plurality of passive elements mounted on the substrate, and a semiconductor element stacked on the surface (upper surface) of the passive element.

また、この半導体装置は、前記受動素子が、複数設けられていることが好ましい。   Moreover, this semiconductor device is preferably provided with a plurality of the passive elements.

また、この半導体装置において、前記複数の受動素子は、前記基板上に二次元方向に平面的に配列されることが好ましい。   In the semiconductor device, it is preferable that the plurality of passive elements are arranged in a two-dimensional direction on the substrate in a two-dimensional direction.

また、この半導体装置において、前記複数の受動素子は、薄化されて同じ高さまで平坦化されることが好ましい。   In the semiconductor device, the plurality of passive elements are preferably thinned and flattened to the same height.

また、この半導体装置において、前記受動素子が表面実装型の抵抗素子または薄膜コンデンサーであることが好ましい。   In this semiconductor device, it is preferable that the passive element is a surface-mount resistance element or a thin film capacitor.

また、この半導体装置において、前記抵抗素子の抵抗回路形成面または前記薄膜コンデンサーの薄膜コンデンサー形成面が回路形成された基板と正対するように構成されることが好ましい。   Further, in this semiconductor device, it is preferable that the resistor circuit forming surface of the resistor element or the thin film capacitor forming surface of the thin film capacitor is opposed to the substrate on which the circuit is formed.

また、この半導体装置において、前記受動素子と受動素子との間には樹脂が充填されていることが好ましい。   Moreover, in this semiconductor device, it is preferable that a resin is filled between the passive elements.

このような半導体装置によれば、容積を抑えたまま抵抗素子、薄膜コンデンサーなどの受動素子を多数内臓した半導体装置、すなわち半導体パッケージが得られる。   According to such a semiconductor device, a semiconductor device having a large number of passive elements such as resistance elements and thin film capacitors, that is, a semiconductor package, can be obtained while the volume is suppressed.

また、本発明に係る半導体装置の製造方法は、回路形成された基板上に受動素子を実装する実装工程と、前記実装された受動素子を薄化する薄化工程と、前記平坦化された受動素子の表面に半導体素子を積層する積層工程と、を含む。   The semiconductor device manufacturing method according to the present invention includes a mounting step of mounting a passive element on a circuit-formed substrate, a thinning step of thinning the mounted passive element, and the flattened passive Laminating a semiconductor element on the surface of the element.

この半導体装置の製造方法において、前記実装工程では、複数の受動素子を基板上に実装し、前記薄化工程では、前記複数の受動素子を薄化して同じ高さまで平坦化することが好ましい。   In this method of manufacturing a semiconductor device, it is preferable that a plurality of passive elements are mounted on a substrate in the mounting step, and the plurality of passive elements are thinned and flattened to the same height in the thinning step.

また、この半導体装置の製造方法において、前記薄化工程では、当該受動素子の表面を研磨することが好ましい。   In the method for manufacturing a semiconductor device, it is preferable that the surface of the passive element is polished in the thinning step.

また、この半導体装置の製造方法において、前記実装工程と前記薄化工程との間に、前記受動素子間に樹脂層を形成する樹脂層形成工程をさらに含むことが好ましい。   Moreover, in this semiconductor device manufacturing method, it is preferable that a resin layer forming step of forming a resin layer between the passive elements is further included between the mounting step and the thinning step.

また、この半導体装置の製造方法において、前記実装工程では、複数の受動素子を基板上に実装し、前記薄化工程と前記積層工程との間に、前記受動素子間に充填する樹脂充填工程をさらに含むことが好ましい。   Further, in this semiconductor device manufacturing method, in the mounting step, a resin filling step of mounting a plurality of passive elements on a substrate and filling between the passive elements between the thinning step and the stacking step. Furthermore, it is preferable to include.

このような半導体装置の製造方法によれば、薄化処理により受動素子の高さを抑えるようにして、容積を抑えたままで容積を抑えたまま抵抗素子、薄膜コンデンサーなどの受動素子を多数内臓した半導体装置、すなわち半導体パッケージが得られる。   According to such a method of manufacturing a semiconductor device, the height of the passive element is suppressed by the thinning process, and a large number of passive elements such as a resistance element and a thin film capacitor are incorporated while the volume is suppressed while the volume is suppressed. A semiconductor device, that is, a semiconductor package is obtained.

特に受動素子を複数設けた場合、薄化工程で受動素子の高さを揃える平坦化処理を行って実装ばらつきを補正する形になるため、受動素子と半導体素子とを積層して強固に接着させることが可能になる。また、薄化工程を行う前に受動素子同士の間に樹脂層を設けることで、研磨などの薄化の際に受動素子の端部の欠けなどの不具合が生じることが少ない。また、平坦化処理後に受動素子同士の間に樹脂層を設けることで、樹脂層がない状態では半導体素子を積層した後に生じる空間が埋められることになり、半導体素子の積層の際にさらに強固な接着を可能にして、半導体装置の信頼性が向上する。   In particular, when a plurality of passive elements are provided, a flattening process is performed to make the height of the passive elements uniform in the thinning process and the mounting variation is corrected. Therefore, the passive elements and the semiconductor elements are stacked and firmly bonded. It becomes possible. In addition, by providing a resin layer between the passive elements before performing the thinning step, problems such as chipping of the end portions of the passive elements are less likely to occur during thinning such as polishing. In addition, by providing a resin layer between the passive elements after the planarization treatment, a space generated after the semiconductor elements are stacked is filled in the absence of the resin layer, and the semiconductor elements are more firmly stacked. Adhesion is possible, and the reliability of the semiconductor device is improved.

本発明によれば、受動素子が内蔵された半導体装置を効率よく製造することが可能となる。   According to the present invention, it is possible to efficiently manufacture a semiconductor device in which a passive element is built.

以下、本発明に係る半導体装置およびその製造方法の実施形態について、図面を参照しながら詳細に説明する。なお、図面の説明においては、同一要素には同一符号を付し、重複する説明を省略する。   DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be described in detail with reference to the drawings. In the description of the drawings, the same reference numerals are assigned to the same elements, and duplicate descriptions are omitted.

（半導体装置）
図１は、実施の形態に係る半導体装置の断面図を示す図であり、図２は、当該半導体装置を上面からみた透視図である。
図１に示したように、半導体装置１０は、基板２０と、基板２０上に実装される複数の受動素子２４と、受動素子２４の表面に積層される半導体素子２２とを含む。 (Semiconductor device)
FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment, and FIG. 2 is a perspective view of the semiconductor device as viewed from above.
As shown in FIG. 1, the semiconductor device 10 includes a substrate 20, a plurality of passive elements 24 mounted on the substrate 20, and a semiconductor element 22 stacked on the surface of the passive element 24.

図２に示したように、受動素子２４は基板２０上で二次元的に平面的に配列されるように設けられている。   As shown in FIG. 2, the passive elements 24 are provided on the substrate 20 so as to be two-dimensionally arranged in a plane.

基板２０としては、プリント回路基板（ＰＣＢ）などを用いることができる。また、受動素子２４としては、素子の片面のみに機能面を有する受動素子であって、例えば裏面が研削可能な表面実装型の抵抗素子、薄層化が可能な薄膜コンデンサーが挙げられる。   As the substrate 20, a printed circuit board (PCB) or the like can be used. The passive element 24 is a passive element having a functional surface only on one side of the element, and includes, for example, a surface-mounted resistance element whose back surface can be ground and a thin film capacitor capable of being thinned.

また、受動素子２４の形成面３２、例えば抵抗素子の抵抗回路形成面、薄膜コンデンサーの薄膜コンデンサー形成面が、基板２０の回路形成面３０と正対するように構成されることが好ましい。   Further, it is preferable that the formation surface 32 of the passive element 24, for example, the resistance circuit formation surface of the resistance element and the thin film capacitor formation surface of the thin film capacitor are configured to face the circuit formation surface 30 of the substrate 20.

通常、受動素子２４を実装すると、実装された受動素子の高さに差が出るなどの実装ばらつきが生じ、この実装ばらつきに起因して複数の受動素子の表面に安定した半導体素子の積層が困難であることが多い。そこで、受動素子２４の表面に半導体素子２２を積層するために、平坦化されていることが好ましい。すなわち、受動素子２４の形成面３２の裏面、すなわち半導体素子積層側の表面を研削するなどして薄化して、全部の受動素子２４の高さを揃えるように構成することが好ましい。   Usually, when the passive element 24 is mounted, mounting variations such as a difference in the height of the mounted passive elements occur, and it is difficult to stably stack semiconductor elements on the surfaces of a plurality of passive elements due to the mounting variations. Often. Therefore, in order to stack the semiconductor element 22 on the surface of the passive element 24, it is preferably flattened. In other words, it is preferable that the back surface of the formation surface 32 of the passive element 24, that is, the surface on the semiconductor element stacking side is thinned by grinding or the like so that all the passive elements 24 have the same height.

また、基板２０と半導体素子２２との間であって、受動素子２４の間には間隙２６が形成されている。この空隙には、樹脂が充填されていることが好ましい。このように間隙２６を樹脂で充填するように構成することで、基板２０と半導体素子２２との間には空間が生じなくなるため、半導体素子２２の積層の際に強固な接着を可能にして、半導体装置１０の信頼性が向上する。   A gap 26 is formed between the substrate 20 and the semiconductor element 22 and between the passive elements 24. This void is preferably filled with a resin. Since the space 26 is configured to be filled with the resin in this way, no space is generated between the substrate 20 and the semiconductor element 22, thereby enabling strong adhesion when the semiconductor elements 22 are stacked. The reliability of the semiconductor device 10 is improved.

（半導体装置の製造方法）
半導体装置の製造方法の実施形態は、図３（ａ）に示したように、回路形成された基板２０上に受動素子２４を実装する実装工程と、図３（ｃ）に示したように、実装された受動素子２４を薄化して同じ高さまで平坦化する平坦化工程と、図３（ｄ）に示したように、平坦化された受動素子２４の表面に半導体素子２２を積層する積層工程とを含んでいる。 (Semiconductor device manufacturing method)
As shown in FIG. 3A, an embodiment of a method for manufacturing a semiconductor device includes a mounting step of mounting a passive element 24 on a circuit-formed substrate 20, and a step of mounting a passive element 24 as shown in FIG. A flattening step of thinning and flattening the mounted passive element 24 to the same height, and a stacking step of stacking the semiconductor element 22 on the surface of the flattened passive element 24 as shown in FIG. Including.

本実施形態では、まず第一のステップとして、図３（ａ）に示したように、回路形成された基板２０の上に所定の受動素子２４を実装する。これに適用可能な受動素子は、表面実装型受動素子であり素子の片面のみに機能面を有する、抵抗素子及び薄膜コンデンサー素子である。セラミック積層コンデンサーについては容量が小さく電極を片側面に局所的に配置させた構造のものならば適用が可能である。   In the present embodiment, as a first step, a predetermined passive element 24 is mounted on the circuit board 20 as shown in FIG. Passive elements applicable to this are surface-mounted passive elements, which are a resistive element and a thin film capacitor element having a functional surface only on one side of the element. A ceramic multilayer capacitor is applicable if it has a small capacity and a structure in which electrodes are locally arranged on one side.

また実装の方法としては、半田を用いた従来の表面実装技術を用いることが可能であり、そのほかには、導電ペーストを用いる方法、スタッドバンプを用いる方法などいかなる既存の方法も適用可能である。   As a mounting method, a conventional surface mounting technique using solder can be used. In addition, any existing method such as a method using a conductive paste or a method using a stud bump can be applied.

次のステップでは、図３（ｂ），（ｃ）に示したように、実装された受動素子２４が薄化処理され平坦化される。
薄化処理の態様としては、研磨処理が挙げられるが、研磨処理の際には基板２０の受動素子非実装面（裏面）３１に基板保持用のテープ３０を貼り、ディスク状の砥石３２を用いて研磨するようにしてもよい。 In the next step, as shown in FIGS. 3B and 3C, the mounted passive element 24 is thinned and flattened.
An example of the thinning process is a polishing process. At the time of the polishing process, a substrate holding tape 30 is attached to the passive element non-mounting surface (back surface) 31 of the substrate 20 and a disc-shaped grindstone 32 is used. You may make it grind.

また、薄化した受動素子の実装する態様としては、予め薄い支持体上に受動素子を形成して基板上に実装する方法、基板に実装する前に予め研削して薄化した受動素子を基板上に実装する方法などが挙げられる。   In addition, as a mode of mounting a thinned passive element, a method of forming a passive element on a thin support in advance and mounting it on a substrate, a passive element that has been ground and thinned before mounting on the substrate, The method of mounting on top is mentioned.

また、実装方法によっては基板の受動素子保持力が十分でなく、受動素子の脱落が発生する場合がある。このため、前記実装工程と前記平坦化工程との間に受動素子２４間に樹脂層（図示さず）を形成する樹脂層形成工程を設けることが好ましい。これにより、研磨する前に実装された受動素子２４間に樹脂を流し込むことにより回避することができる。   Further, depending on the mounting method, the passive element holding force of the substrate is not sufficient, and the passive element may drop off. For this reason, it is preferable to provide the resin layer formation process which forms a resin layer (not shown) between the passive elements 24 between the said mounting process and the said planarization process. This can be avoided by pouring the resin between the passive elements 24 mounted before polishing.

なお、このとき用いることのできる樹脂としては、エポキシ樹脂、ビスマレイミド・トリアジンレジン（ＢＴレジン）などが挙げられる。   Examples of the resin that can be used at this time include an epoxy resin, a bismaleimide-triazine resin (BT resin), and the like.

次のステップでは、図３（ｄ）に示したように、半導体素子２２を半導体搭載用接着剤を用いて、研磨された受動素子２４上に搭載するが、フィルム状接着剤・ペースト状接着剤のどちらも用いることができる。   In the next step, as shown in FIG. 3 (d), the semiconductor element 22 is mounted on the polished passive element 24 using a semiconductor mounting adhesive, but a film adhesive / paste adhesive. Either of these can be used.

また、受動素子２４の薄化処理を行う前に前記樹脂層を設けない場合には、前記平坦化工程と前記積層工程との間に、前記受動素子間に充填する樹脂充填工程を設けることが好ましい。これにより、半導体素子を積層するときに、受動素子２４間に樹脂が充填されていない場合は、前述したようにペースト状接着剤を用いて半導体素子を研磨処理済み受動素子２４に接着固定すると共に、受動素子２４の間を樹脂で充填することが望ましい。このように受動素子２４の間に生じる間隙２６を樹脂で充填するように構成することで、基板２０と半導体素子２２との間には空間が生じなくなるため、半導体素子２２の積層の際に強固な接着を可能にして、半導体装置１０の耐久性が向上する。なお、ここで用いることのできる樹脂としても、上述したものが挙げられる。   Further, when the resin layer is not provided before the thinning process of the passive element 24, a resin filling process for filling between the passive elements may be provided between the planarization process and the lamination process. preferable. Accordingly, when the semiconductor elements are stacked, if the resin is not filled between the passive elements 24, the semiconductor elements are bonded and fixed to the polished passive elements 24 using the paste adhesive as described above. It is desirable to fill the space between the passive elements 24 with resin. Since the gap 26 generated between the passive elements 24 is filled with the resin in this way, no space is generated between the substrate 20 and the semiconductor element 22, so that the semiconductor element 22 is strongly laminated. It is possible to improve the durability of the semiconductor device 10. In addition, what was mentioned above is mentioned also as resin which can be used here.

次のステップでは、図３（ｅ）に示したように、ワイヤーボンディング方式、ＴＡＢ（tape automated bonding）方式などの手法により半導体素子２２がボンディングワイヤ３６を介して基板２０と接続される。その後に、図３（ｆ）に示したように、封止樹脂３８により封止されることにより半導体装置となる。   In the next step, as shown in FIG. 3E, the semiconductor element 22 is connected to the substrate 20 via the bonding wire 36 by a method such as a wire bonding method or a TAB (tape automated bonding) method. Thereafter, as shown in FIG. 3F, the semiconductor device is formed by sealing with a sealing resin 38.

また、半導体素子の上にさらに半導体素子を搭載しワイヤーボンディングなどの手法で基板と接続した後、封止樹脂で封止することも可能である。具体的には、図４に示したように、基板２０の回路形成面上に受動素子２４を実装し、さらに当該受動素子２４の表面に半導体素子２２を積層させて、さらに第２半導体素子４２を積層させて、基板２０と半導体素子２２との間をボンディングワイヤ４４で接続し、さらに半導体素子２２と第２半導体素子４２との間をボンディングワイヤ４６で接続し、さらに受動素子２４間の間隙を樹脂にて封止してなる半導体装置４０の構成をとることもできる。   It is also possible to mount a semiconductor element on the semiconductor element, connect it to the substrate by a technique such as wire bonding, and then seal with a sealing resin. Specifically, as shown in FIG. 4, the passive element 24 is mounted on the circuit forming surface of the substrate 20, the semiconductor element 22 is further laminated on the surface of the passive element 24, and the second semiconductor element 42. Are stacked, the substrate 20 and the semiconductor element 22 are connected by the bonding wire 44, the semiconductor element 22 and the second semiconductor element 42 are connected by the bonding wire 46, and the gap between the passive elements 24 is further connected. The structure of the semiconductor device 40 formed by sealing the resin with resin can also be taken.

上記の発明を用いて、半導体素子と受動素子を積層すれば、半導体パッケージの容積を抑制したまま受動素子を内蔵した半導体パッケージを効率よく製造することができる。   If a semiconductor element and a passive element are stacked using the above invention, a semiconductor package incorporating a passive element can be efficiently manufactured while suppressing the volume of the semiconductor package.

以上、本発明に係る半導体装置およびその製造方法の実施形態について説明したが、本発明の目的の範囲内で適宜変更可能である。
例えば、複数の受動素子を基板上に配置した例を示したが、これに限定されることはなく、少なくともひとつの受動素子および能動素子を混在させても差し支えない。 Although the embodiments of the semiconductor device and the manufacturing method thereof according to the present invention have been described above, the embodiments can be appropriately changed within the scope of the object of the present invention.
For example, although an example in which a plurality of passive elements are arranged on the substrate has been shown, the present invention is not limited to this, and at least one passive element and active element may be mixed.

また、受動素子と受動素子との間の間隙の全てを樹脂で充填する例を説明したが、これに限定されることはなく、当該間隙に例えば能動素子を配置して、その能動素子が占める空間以外の空間を樹脂で充填するようにしてもよい。これにより、受動素子間に生じるデッドスペースの有効利用を図ることができるようになる。   Further, the example in which the entire gap between the passive element and the passive element is filled with the resin has been described. However, the present invention is not limited to this. For example, an active element is disposed in the gap and the active element occupies the gap. A space other than the space may be filled with resin. This makes it possible to effectively use the dead space generated between the passive elements.

以下に、本発明の実施形態の一例を詳細に説明する。なお、本発明は、これにより限定されるものではない。   Hereinafter, an example of an embodiment of the present invention will be described in detail. In addition, this invention is not limited by this.

ＦＲ５基板を用いて作成されたプリント配線板の上の所定の端子に半田ペーストを印刷し、半田ペースト印刷済み端子に対応する部位に長辺６００μｍ、短辺３００μｍの抵抗素子（以後０６０３抵抗と呼称）３０個をＳＭＴペーストにより仮固定した後、リフロー炉に投入し０６０３抵抗とプリント配線板を電気的に接続した。この際、機能面がプリント配線板と正対するよう０６０３抵抗が搭載された。   A solder paste is printed on a predetermined terminal on a printed wiring board formed using an FR5 substrate, and a resistance element (hereinafter referred to as 0603 resistor) having a long side of 600 μm and a short side of 300 μm is provided at a portion corresponding to the solder paste printed terminal. ) After 30 pieces were temporarily fixed with SMT paste, they were put into a reflow furnace to electrically connect the 0603 resistor and the printed wiring board. At this time, a 0603 resistor was mounted so that the functional surface would face the printed wiring board.

次に、固定用テープ（Ｄ―２０３，リンテック社製）に基板を貼り付け、グラインディングマシン（株式会社ディスコ製：ＤＡＧ８１０）により、６００番の砥石で０６０３抵抗３０個の厚みの平均が１００μｍになるまで研磨した。このときの各０６０３抵抗の研磨面の高さばらつきは２μｍ以下であった。   Next, the substrate is attached to a fixing tape (D-203, manufactured by Lintec Corporation), and the average of the thickness of 30 0603 resistors is 100 μm with a grinding wheel No. 600 using a grinding machine (manufactured by DISCO Corporation: DAG810). Polished until At this time, the variation in height of the polished surface of each 0603 resistor was 2 μm or less.

次に、予め半導体素子機能面裏側にフィルム状接着剤（住友ベークライト(株)製ＩＢＦ−Ｘ８５２０）を貼り付けた４ｍｍ角の半導体素子を０６０３抵抗の研磨面に貼り付け、１８０℃１時間加熱することにより接着剤を硬化させた。   Next, a 4 mm square semiconductor element in which a film adhesive (IBF-X8520 manufactured by Sumitomo Bakelite Co., Ltd.) is pasted on the back side of the functional surface of the semiconductor element is pasted on the polished surface of 0603 resistor and heated at 180 ° C. for 1 hour. The adhesive was cured.

次にワイヤーボンディングの手法により、半導体素子とプリント配線板を接続した後、半導体素子と０６０３抵抗をトランスファーモールドの手法により封止樹脂で封止した。   Next, after connecting a semiconductor element and a printed wiring board by the method of wire bonding, the semiconductor element and 0603 resistance were sealed with sealing resin by the method of transfer molding.

このようにして得られた、０６０３抵抗内蔵半導体装置は動作確認試験に供せられ半導体装置としての動作に何の問題のないことが確認された。   The 0603 resistor built-in semiconductor device obtained in this way was subjected to an operation check test, and it was confirmed that there was no problem in the operation as a semiconductor device.

本発明の実施形態に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on embodiment of this invention. 前記半導体装置を上面からみた透視図である。It is the perspective view which looked at the semiconductor device from the upper surface. 本発明の半導体装置の製造方法の一例を示す工程概略図である。It is process schematic which shows an example of the manufacturing method of the semiconductor device of this invention. 前記実施形態の変形例を示す断面図である。It is sectional drawing which shows the modification of the said embodiment.

符号の説明Explanation of symbols

１０ 半導体装置
２０ （プリント配線（回路））基板
２２ 半導体素子
２４ 受動素子
３８ 封止樹脂
４０ 半導体装置
４２ 半導体素子 10 Semiconductor Device 20 (Printed Wiring (Circuit)) Board
22 Semiconductor element 24 Passive element 38 Sealing resin 40 Semiconductor device 42 Semiconductor element

Claims (12)

基板と、
前記基板上に実装される受動素子と、
前記受動素子の表面に積層される半導体素子と、を含む
半導体装置。 A substrate,
Passive elements mounted on the substrate;
And a semiconductor element stacked on the surface of the passive element. 請求項１に記載の半導体装置において、
前記受動素子が、複数設けられていることを特徴とする半導体装置。 The semiconductor device according to claim 1,
A semiconductor device comprising a plurality of the passive elements. 請求項２に記載の半導体装置において、
前記複数の受動素子は、前記基板上に二次元方向に平面的に配列されることを特徴とする半導体装置。 The semiconductor device according to claim 2,
The plurality of passive elements are two-dimensionally arranged in a two-dimensional direction on the substrate. 請求項２に記載の半導体装置において、
前記受動素子は、薄化されて同じ高さまで平坦化されていることを特徴とする半導体装置。 The semiconductor device according to claim 2,
The semiconductor device, wherein the passive element is thinned and flattened to the same height. 請求項１に記載の半導体装置において、
前記受動素子が表面実装型の抵抗素子または薄膜コンデンサーであることを特徴とする半導体装置。 The semiconductor device according to claim 1,
A semiconductor device, wherein the passive element is a surface-mounted resistance element or a thin film capacitor. 請求項４に記載の半導体装置において、
前記抵抗素子の抵抗回路形成面または前記薄膜コンデンサーの薄膜コンデンサー形成面が回路形成された基板と正対するように構成される半導体装置。 The semiconductor device according to claim 4,
A semiconductor device configured such that a resistance circuit formation surface of the resistance element or a thin film capacitor formation surface of the thin film capacitor faces a substrate on which a circuit is formed. 請求項２に記載の半導体装置において、
前記受動素子と受動素子との間には樹脂が充填されていることを特徴とする半導体装置。 The semiconductor device according to claim 2,
A semiconductor device, wherein a resin is filled between the passive element and the passive element. 回路形成された基板上に受動素子を実装する実装工程と、
前記実装された受動素子を薄化する薄化工程と、
前記平坦化された受動素子の表面に半導体素子を積層する積層工程と、を含む
半導体装置の製造方法。 A mounting process for mounting passive elements on a circuit-formed substrate;
A thinning step of thinning the mounted passive element;
And a laminating step of laminating semiconductor elements on the surface of the planarized passive element. 請求項８に記載の半導体装置の製造方法において、
前記実装工程では、複数の受動素子を基板上に実装し、
前記薄化工程では、前記複数の受動素子を薄化して同じ高さまで平坦化することを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 8,
In the mounting step, a plurality of passive elements are mounted on a substrate,
In the thinning step, the plurality of passive elements are thinned and flattened to the same height. 請求項８に記載の半導体装置の製造方法において、
前記薄化工程では、当該受動素子の表面を研磨することを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 8,
In the thinning process, the surface of the passive element is polished. 請求項８に記載の半導体装置の製造方法において、
前記実装工程と前記薄化工程との間に、前記受動素子間に樹脂層を形成する樹脂層形成工程をさらに含むことを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 8,
A method of manufacturing a semiconductor device, further comprising a resin layer forming step of forming a resin layer between the passive elements between the mounting step and the thinning step. 請求項８に記載の半導体装置の製造方法において、
前記実装工程では、複数の受動素子を基板上に実装し、
前記薄化工程と前記積層工程との間に、前記受動素子間に充填する樹脂充填工程をさらに含むことを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 8,
In the mounting step, a plurality of passive elements are mounted on a substrate,
A method of manufacturing a semiconductor device, further comprising a resin filling step of filling between the passive elements between the thinning step and the laminating step.
JP2004155066A 2003-05-27 2004-05-25 Semiconductor device and manufacturing method thereof Expired - Lifetime JP4740555B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004155066A JP4740555B2 (en) 2003-05-27 2004-05-25 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2003149841 2003-05-27
JP2003149841 2003-05-27
JP2004155066A JP4740555B2 (en) 2003-05-27 2004-05-25 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2005012199A true JP2005012199A (en) 2005-01-13
JP4740555B2 JP4740555B2 (en) 2011-08-03

Family

ID=34106692

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004155066A Expired - Lifetime JP4740555B2 (en) 2003-05-27 2004-05-25 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP4740555B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009088069A1 (en) * 2008-01-09 2009-07-16 Nec Corporation Manufacturing method for condenser-packaged device, and manufacturing method for condenser-packaged package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009088069A1 (en) * 2008-01-09 2009-07-16 Nec Corporation Manufacturing method for condenser-packaged device, and manufacturing method for condenser-packaged package
JP5423399B2 (en) * 2008-01-09 2014-02-19 日本電気株式会社 Manufacturing method of device with built-in capacitor and manufacturing method of package with built-in capacitor

Also Published As

Publication number Publication date
JP4740555B2 (en) 2011-08-03

Similar Documents

Publication Publication Date Title
KR101686553B1 (en) Chip Stacked Package and Package on Package
KR102077153B1 (en) Semiconductor packages having through electrodes and methods for fabricating the same
US8487421B2 (en) Microelectronic package with stacked microelectronic elements and method for manufacture thereof
US7408257B2 (en) Packaging chip and packaging method thereof
JP5215244B2 (en) Semiconductor device
EP1119049A2 (en) Laminate type semiconductor apparatus
JP2005252018A (en) Resin-sealed semiconductor device and lead frame, and manufacturing method thereof
JP2002289769A (en) Stacked semiconductor device and its manufacturing method
JP2003115560A (en) Semiconductor device, laminated semiconductor device, manufacturing method of semiconductor device, and manufacturing method of laminated semiconductor device
KR20080020069A (en) Semiconductor package and method for fabricating the same
US11646331B2 (en) Package substrate
KR101245454B1 (en) Multipackage module having stacked packages with asymmetrically arranged die and molding
JP2001223326A (en) Semiconductor device
US8951835B2 (en) Method of fabricating a package substrate
JP2001298115A (en) Semiconductor device, manufacturing method for the same, circuit board as well as electronic equipment
JP2000031309A (en) Chip stack package
JP4395166B2 (en) Semiconductor device with built-in capacitor and manufacturing method thereof
CN110634838A (en) Ultrathin fan-out type packaging structure and manufacturing method thereof
US20040227223A1 (en) Semiconductor device, electronic device, electronic apparatus, and methods for manufacturing semiconductor device and electronic device
JP4175138B2 (en) Semiconductor device
US20050001301A1 (en) Semiconductor device, electronic device, electronic equipment, and method of manufacturing semiconductor device
JP4034468B2 (en) Manufacturing method of semiconductor device
WO2004105134A1 (en) An integrated circuit package
US8872318B2 (en) Through interposer wire bond using low CTE interposer with coarse slot apertures
JP3476383B2 (en) Semiconductor laminated package

Legal Events

Date Code Title Description
A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20041115

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20041116

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070104

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20071012

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20071015

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20080321

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20081125

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20081128

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090127

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090217

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090420

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20090525

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090824

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20091022

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20091120

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20091120

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100115

A912 Re-examination (zenchi) completed and case transferred to appeal board

Free format text: JAPANESE INTERMEDIATE CODE: A912

Effective date: 20100226

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20101224

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110502

R150 Certificate of patent or registration of utility model

Ref document number: 4740555

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140513

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250