WO2009088069A1 - Manufacturing method for condenser-packaged device, and manufacturing method for condenser-packaged package - Google Patents
Manufacturing method for condenser-packaged device, and manufacturing method for condenser-packaged package Download PDFInfo
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- WO2009088069A1 WO2009088069A1 PCT/JP2009/050200 JP2009050200W WO2009088069A1 WO 2009088069 A1 WO2009088069 A1 WO 2009088069A1 JP 2009050200 W JP2009050200 W JP 2009050200W WO 2009088069 A1 WO2009088069 A1 WO 2009088069A1
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Images
Classifications
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- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
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- H—ELECTRICITY
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- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/33—Thin- or thick-film capacitors
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- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
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Definitions
- the present invention is based on the priority claim of Japanese patent application: Japanese Patent Application No. 2008-002340 (filed on Jan. 9, 2008), the entire description of which is incorporated herein by reference. Shall.
- the present invention relates to a method for manufacturing a capacitor built-in device (particularly a semiconductor device) in which a capacitor is built in an electronic device, and a method for manufacturing a capacitor built-in package in which the capacitor built-in device is mounted on a circuit board.
- a voltage drop ⁇ V generated at the time of switching is generally expressed by the following equation (1).
- ⁇ V ⁇ L ⁇ di / dt (1)
- di / dt is the time change of the load current flowing through the circuit by switching
- L is the inductance of the wiring between the LSI and the power supply device.
- a decoupling capacitor is arranged between the LSI and the power supply so that L in Expression (1) is reduced.
- Patent Documents 1 to 4 disclose a mounting structure in which an interposer-type capacitor is disposed between an LSI and a circuit board or inside a circuit board surface immediately below the LSI and directly connected to the LSI only through solder bumps. Has been.
- an interposer type capacitor in which a capacitor is formed on one surface of a substrate on which a through via (through wiring) is formed is manufactured as a discrete component.
- the manufactured interposer type capacitor is electrically connected to the semiconductor element and the circuit board via solder bumps at connection pads formed at both ends of the through wiring.
- a cavity is formed on one surface of the substrate on which the capacitor is formed, Cu is embedded in the cavity, and then the other side of the substrate is formed.
- a substrate via (through wiring) is formed by mechanically grinding the substrate from the surface side to expose Cu at the bottom of the cavity.
- Patent Documents 1 to 4 The entire disclosures of Patent Documents 1 to 4 above are incorporated herein by reference. The following analysis is given from the viewpoint of the present invention.
- the interposer type capacitors described in Patent Documents 1 to 4 are manufactured as discrete components (single unit), a sufficient thickness is required so that they can be handled easily during manufacturing and mounting.
- the thickness that facilitates handling depends on the size of the workpiece or wafer. However, considering that it is possible to manufacture a large number of workpieces simultaneously, the interposer capacitor itself needs to have a thickness of, for example, 200 ⁇ m or more. . Since the interposer type capacitor is inserted, for example, between the semiconductor element and the circuit board, the thickness of the package also increases by the thickness of the interposer type capacitor. If the thickness of the package is increased, it is disadvantageous for downsizing and thinning of the device on which the package is mounted.
- the signal line of the package becomes longer by the thickness of the interposer type capacitor, causing an increase in transmission loss.
- many LSIs that require an interposer type capacitor have a large number of I / O pads of 1000 or more, and the interposer type capacitor requires fine through vias (wiring) with a diameter of 50 ⁇ m or less.
- the diameter of the through via must be increased (in general, the aspect ratio (depth / via diameter) of the through via is about 1). Therefore, it is difficult to form such a fine through via so as to penetrate a substrate having a sufficient thickness so as to be easily handled.
- the interposer type capacitor is made thin in order to solve these problems, it will be difficult to handle this time, and there will be a problem that the production and mounting of the interposer type capacitor will not be realized at a low cost.
- an interposer type capacitor is manufactured with a thickness of 100 ⁇ m or less that can solve the above problem, the mechanical strength is weakened, and it is damaged during the manufacturing process, and the thermal history and warpage due to the material laminated on the substrate increase. For this reason, it is difficult to manufacture and mount the interposer type capacitor with high productivity.
- the method of thinning the capacitor after being connected to the LSI without manufacturing the capacitor as a discrete component for example, a wafer-on-wafer to be connected between wafer states, and an LSI chip selected on the wafer on which the capacitor is formed are used.
- the former has the disadvantages that the LSI and the capacitor must be made of wafers of the same shape, and that good products cannot be selected and connected. In the latter case, the non-defective products can be selected, but after the LSI and the capacitor are integrated, the process is performed in the shape of the wafer on which the capacitor is formed. Therefore, when the LSI test is performed in this state, there is a drawback that a different probe card or test program must be prepared even when the same test as the wafer state test before dicing the LSI is performed.
- An object of the present invention is to provide a method of manufacturing a capacitor built-in device in which a thin capacitor having fine through vias is built in an electronic device, not as a discrete component, and a package with a built-in capacitor in which the capacitor built-in device is mounted on a circuit board. It is to provide a method of manufacturing.
- a method of manufacturing a capacitor built-in device in which a capacitor built-in element is mounted on an electronic device, wherein at least one capacitor having an upper electrode, a dielectric and a lower electrode is used as a unit, and the capacitor substrate.
- a conductor forming step of forming a conductor electrically connected to any of the above, and a capacitor built-in element formed by each step Capacitor-embedded element singulation process that separates the unit into one unit of the capacitor-embedded element, and a plurality of capacitors with one surface facing the electronic element so that the conductor and the electronic element are electrically connected
- Capacitor-embedded element mounting process for flip-chip mounting of the capacitor-embedded element on the electronic element, capacitor substrate thinning process for thinning the capacitor board so that the conductor in the recess is exposed, and a capacitor built-in formed by each process
- a manufacturing method of a device with a built-in capacitor including a
- the method for manufacturing the capacitor-embedded device when the capacitor substrate is non-insulating, is configured so that the capacitor substrate and the conductor are not electrically connected in the interlayer insulating film forming step.
- An insulating film forming step is further included in which an insulating film is formed on the other surface of the capacitor substrate so that the conductor in the recess is exposed after the capacitor thinning step.
- a method of manufacturing a capacitor built-in device in which a capacitor built-in element is mounted on an electronic device, wherein at least one capacitor having an upper electrode, a dielectric and a lower electrode is used as a unit, and the capacitor substrate
- a capacitor forming step of forming a plurality of capacitors on one surface of the capacitor, an interlayer insulating film forming step of forming an interlayer insulating film on one surface of the capacitor substrate, and at least a part of one surface of the electronic device A conductor forming process for forming a conductor that is in contact with a predetermined region where a capacitor is not formed, penetrates the interlayer insulating film, and is electrically connected to either the upper electrode or the lower electrode, and is formed by each process.
- Capacitor-embedded element mounting process for flip-chip mounting a plurality of capacitor-embedded elements on the electronic element with one surface of the capacitor substrate facing the electronic element so as to be electrically connected, and the capacitor substrate is thinned to a predetermined thickness
- a through-hole conductor forming step for forming a through-hole conductor for covering or filling the through-hole, and a capacitor built-in device that separates the assembly of capacitor built-in devices formed by each step into units for each capacitor built-in element
- a method for manufacturing a device with a built-in capacitor including a device dividing step.
- the method for manufacturing the capacitor-embedded device when the capacitor substrate is non-insulating, is configured so that the capacitor substrate and the conductor are not electrically connected in the interlayer insulating film forming step. It further includes an insulating film step of forming an insulating film and forming an insulating film on the inner surface of the through hole and the other surface of the capacitor substrate before the through hole conductor forming step.
- the capacitor substrate in the capacitor substrate thinning step, is thinned by at least one of grinding and etching.
- the method for manufacturing a device with a built-in capacitor further includes an electronic element thinning step for thinning the electronic device before the step of separating the device with a built-in capacitor.
- the method for manufacturing a capacitor-embedded device further includes a first non-defective product selection step of electrically testing the capacitor-embedded element and the electronic element before the capacitor-embedded element mounting step. Including.
- a dummy chip is mounted in at least one area instead of the built-in capacitor element.
- the method for manufacturing a capacitor built-in device further includes a second non-defective product selection step of electrically testing the capacitor built-in device before the capacitor built-in device individualization step.
- a method for manufacturing a package with a built-in capacitor in which a device with a built-in capacitor mounted on an electronic device is mounted on a circuit board, the device including at least an upper electrode, a dielectric, and a lower electrode.
- Capacitor board so that the assembly of the capacitor built-in device formed in each process is divided into individual units for each element with built-in capacitor, and the conductor and the circuit board are electrically connected
- Mounting the built-in capacitor device by flip-chip mounting the separated capacitor built-in device on the circuit board with the other side of the capacitor facing the circuit board
- a method for manufacturing a package with a built-in capacitor in which a device with a built-in capacitor mounted on an electronic device is mounted on a circuit board.
- One capacitor as a unit a capacitor forming step of forming a plurality of units on one surface of the capacitor substrate, an interlayer insulating film forming step of forming an interlayer insulating film on one surface of the capacitor substrate, and at least A part of the electronic device is in contact with a predetermined region where a capacitor is not formed, penetrates the interlayer insulating film, and forms a conductor electrically connected to either the upper electrode or the lower electrode.
- Capacitor-embedded device singulation process that separates the assembly into individual capacitors-embedded elements, and the through-hole conductor and circuit board are electrically connected
- the other surface of the capacitor substrate by the circuit board facing to provide a method of manufacturing a capacitor built-in package comprising a built-in capacitor device mounting step of flip-chip mounting a capacitor-containing apparatus which is sectioned in the circuit board, the.
- the present invention has at least one of the following effects.
- the capacitor built-in element can be made thicker than the final form and subjected to processing such as mounting with a thickness that is easy to handle, damage during the process can be prevented, and the capacitor built-in device and Productivity and quality reliability of the capacitor built-in package can be improved.
- the capacitor substrate is thinned to a desired thickness, so that a thinner capacitor built-in device and a capacitor built-in package can be manufactured.
- the thickness of the element part with a built-in capacitor can be set to 100 ⁇ m or less including the height of one solder bump.
- the diameter of the recess or the through hole can be kept small.
- the device with a built-in capacitor and the package with a built-in capacitor can be further downsized.
- the diameter of the recess or the through hole can be set to 50 ⁇ m or less.
- the electronic element is, for example, a semiconductor element (for example, an LSI)
- the device with a built-in capacitor and the package with a built-in capacitor can be further reduced in thickness by thinning the substrate of the semiconductor element.
- the capacitor built-in element can be subjected to an electrical test even before the capacitor substrate is thinned, the electrical test of the capacitor built-in element and the electronic element is performed in advance before mounting the capacitor built-in element.
- the productivity of the capacitor built-in device and the capacitor built-in package can be improved.
- the arrangement of the pads of the electronic element does not change before and after mounting the built-in capacitor element.
- FIG. 2 is a schematic partial cross-sectional view showing details of one unit with a capacitor in FIG. 1.
- FIG. 2 is a schematic partial cross-sectional view showing details of one unit with a capacitor in FIG. 1.
- FIG. 2 is a schematic partial cross-sectional view showing details of one unit with a capacitor in FIG. 1.
- FIG. 2 is a schematic partial cross-sectional view showing details of one unit with a capacitor in FIG. 1.
- FIG. 2 is a schematic partial cross-sectional view showing details of one unit with a capacitor in FIG. 1.
- FIG. 9 is a schematic partial cross-sectional view showing details of one unit of the capacitor built-in device in FIG. 8.
- FIG. 9 is a schematic partial cross-sectional view showing details of one unit of the capacitor built-in device in FIG. 8.
- FIG. 1 to 5 are schematic process diagrams for explaining a method of manufacturing a capacitor built-in device and a capacitor built-in package according to the first embodiment of the present invention.
- FIG. 1 is an overall schematic cross-sectional view of a method of manufacturing a capacitor built-in device and a capacitor built-in package according to the first embodiment of the present invention
- FIGS. 2 to 5 show details of one unit of the capacitor built-in device in FIG. It is a general
- the lower electrode 3 and the dielectric On one surface 2a of the plate-like capacitor substrate 2 made of a heat-resistant material such as glass and having a thickness that is easy to handle (for example, 0.2 mm or more, preferably 0.5 mm or more), the lower electrode 3 and the dielectric A plurality of units of at least one capacitor 10 are formed using at least one thin film capacitor 10 composed of the body 4 and the upper electrode 5 as a unit (capacitor forming step; FIG. 2A) (in FIG. 3 units of capacitor 10 is formed with the capacitor as one unit). Details of one unit are set as appropriate according to the power supply configuration inside the electronic element to be mounted later.
- a suitable thickness of the capacitor substrate 2 that is easy to handle depends on the thickness of the capacitor substrate 2.
- the thickness is about 0.5 mm or more and the diameter is about 150 mm ( 6 inches) is preferably 0.6 mm or more, and in the case of a diameter of about 200 mm (8 inches), 0.7 mm or more is preferable.
- the method of forming the lower electrode 3 and the upper electrode 5 of the capacitor 10 is not limited, but a sputtering method, a chemical vapor deposition method (CVD method), and the like, which are easy to deposit a uniform metal film or alloy film. Etc.) are preferred.
- a method for forming the dielectric 4 is not limited, but a sputtering method, a CVD method, a sol-gel method, or the like that can form a uniform and good insulating oxide film or nitride film at a low temperature is preferable.
- the electrodes 3 and 5 and the dielectric film 4 are preferably processed and formed by dry etching that enables accurate processing.
- the capacitor 10 is not formed in a region where a through wiring that connects connection pads to an electronic element or a circuit board is formed later.
- the capacitor substrate 2 is preferably made of a material having high surface smoothness and high heat resistance in order to form a thin and high-capacity capacitor.
- a semiconductor substrate such as Si or GaAs or an inorganic material such as glass, sapphire, or quartz.
- An insulator substrate can be used. However, it is not limited to these materials, and it is also possible to use a ceramic whose surface is polished, a high heat resistance resin, or a metal whose insulating layer is formed on the surface. A method using the non-insulating capacitor substrate 2 will be described in the second embodiment.
- the material of the dielectric 4 of the capacitor 10 is not limited, but a material having a high relative dielectric constant and capable of being thinned and having good insulating properties is preferable.
- a material having a high relative dielectric constant and capable of being thinned and having good insulating properties is preferable.
- High dielectric constant oxide having silicon nitride, titanium oxide or perovskite structure is more preferable.
- As a high dielectric constant oxide having a perovskite structure SrTiO 3 , BaTiO 3 , PbTiO 3 , SrBi 2 Ta 2 O 9 , PbBi 2 Ta 2 O 9 and a solid solution thereof, or at least one of them are mainly composed. Compounds as components are preferred.
- the material of the electrodes 3 and 5 of the capacitor is not limited, but a high melting point metal such as Pt, Ru, Ir, or TiN is preferable. It is more preferable to form a laminated structure in which Ti, Cr, Ta, Mo or the like is inserted in order to ensure adhesion between the electrode metal and the capacitor substrate 2 or an interlayer insulating film to be formed later and to prevent diffusion.
- a high melting point metal such as Pt, Ru, Ir, or TiN is preferable. It is more preferable to form a laminated structure in which Ti, Cr, Ta, Mo or the like is inserted in order to ensure adhesion between the electrode metal and the capacitor substrate 2 or an interlayer insulating film to be formed later and to prevent diffusion.
- a region on one surface 2a of the capacitor substrate 2 corresponding to a region where a pad is formed on the other surface 2b side of the capacitor substrate 2 (later electrically with the circuit substrate).
- a resist 6 is formed on one surface 2a of the capacitor substrate 2 so that a region where a contact hole for connection is formed is exposed (FIG. 2B).
- a recess (cavity) 7 having a predetermined depth not penetrating the capacitor substrate 2 is formed on one surface 2a of the capacitor substrate 2 by a dry etching method or the like (recess formation step; FIG. 1 (c), FIG. 2 (c)).
- the depth of the recess 7 is designed to be at least equal to the thickness of the capacitor substrate 2 in the final capacitor built-in device.
- the depth of the concave portion 7 is not limited, but the concave portion 7 can be formed from the viewpoint of suppressing the final increase in the thickness of the capacitor built-in device or the entire package, reducing the transmission loss of the signal wiring, or facilitating the formation of the through wiring.
- the depth of is preferably shallower, for example, preferably 50 ⁇ m or less, and more preferably 20 ⁇ m.
- the formation method of the recessed part 7 is not limited, Reactive dry etching, wet etching, laser processing, sandblasting, drilling, etc. are preferable.
- An interlayer insulating film 8a having a contact hole is formed of a photosensitive resin or the like so that the region and the recess 7 are exposed (interlayer insulating film forming step; FIG. 2D).
- the interlayer insulating film 8a is preferably formed by a CVD method or a sol-gel method if it is an inorganic material, or by a spin coating method if it is a resin, because it is easy to form a uniform insulating film.
- the contact hole is preferably formed by a dry etching method if the interlayer insulating film 8a is an inorganic material or a non-photosensitive resin, and photolithography is preferable if it is a photosensitive resin.
- a resist 6 is formed in a region where an interlayer insulating film is to be formed, and a conductor 9 is formed on the recess 7, the lower electrode 3, the upper electrode 5, and the interlayer insulating film 8a (conductor forming step; FIG. 2). (E)).
- the conductor 9 is covered in the recess 7 or filled in the recess 7.
- the conductor 9 is electrically connected to either the lower electrode 3 or the upper electrode 5 (which can be connected to the power supply or ground of the electronic element, respectively) and is formed so as to penetrate the interlayer insulating film 8a.
- the lower electrodes 3 and the upper electrodes 5 in one unit may be electrically connected to each other by the conductor 9.
- the filling method of the conductor 9 is not limited, but it is preferable to deposit the conductor 9 by a plating method, a printing method, an aerosol by a position (AD) method or the like because the conductor 9 can be embedded in the recess 7 at the same time.
- the material of the conductor 9 is not limited, but Cu, Ag, Au, or an alloy containing these as main components is particularly preferable because it has a low resistance value and can be easily filled.
- an interlayer insulating film 8b is formed (FIG. 3 (f)), and a connection pad 11 for electrical connection with an electronic element is formed (FIG. 1 (g), FIG. 3 (g)).
- an electrical test is performed to select non-defective products (accepted products) (first non-defective product selection step).
- the test method is not limited. For example, it is possible to select non-defective products by measuring the impedance using an alternating current or a physical quantity corresponding to the impedance or measuring the leakage current of a direct current low voltage.
- the aggregate of the capacitor built-in elements 12 is singulated for each unit of the capacitor built-in element mounted on the electronic element (capacitor built-in element individualization step; FIG. 1 (h)).
- a cover insulating film 13 and a solder bump 14 are formed on the capacitor built-in element 12 selected as a non-defective product (FIG. 3 (i)), and an electronic element having a plurality of units to be mounted on a circuit board (for example, on a substrate (wafer))
- a plurality of capacitor built-in elements 12 are flip-chip mounted on a plurality of LSIs 15 (capacitor built-in element mounting step; FIG. 1 (j)).
- the capacitor built-in element 12 is mounted in units of electronic elements that have been selected as non-defective products in a prior electrical test, and when there are electronic element units that have been selected as defective products, a dummy chip is placed on the defective electronic elements.
- the dummy chip is not a non-defective capacitor built-in element, but is preferably formed of the same size and the same substrate material (the capacitor 10 is not formed).
- a dummy chip is also mounted when a region where the capacitor built-in element 12 is not mounted is large (for example, when a region where an LSI is not formed is large at the wafer peripheral portion or the like).
- capacitors or dummy chips of the same material are evenly mounted on the entire surface of the electronic device, and the thinning in the subsequent process can be performed uniformly, and stress that causes cracks and the like is not concentrated on a specific location. Can be.
- an underfill resin 16 is filled in the solder connection portion between the capacitor built-in element 12 and the electronic element 15 and the periphery of the capacitor built-in element 12. Thereby, destruction tolerance and connection reliability can be improved in a later process.
- a mold resin 17 is filled in the gap between the mounted capacitor built-in element 12 and the dummy chip, and the peripheral edge of the electronic element where these do not exist (FIG. 1 (k), FIG. 4 (k)). Thereby, it is possible to further improve the uniformity of thinning and the fracture resistance in the subsequent process.
- the capacitor substrate 2 is thinned to a predetermined thickness until at least the conductor 9 filled in the recess 7 is exposed using the substrate of the electronic element 15 (for example, a wafer on which an LSI is formed) as a support.
- the substrate of the electronic element 15 for example, a wafer on which an LSI is formed
- the other surface 2b side of the capacitor substrate 2 of the capacitor built-in element 12 can be mechanically ground until the bottom of the recess 7 is exposed.
- mechanical grinding may be performed to such an extent that the bottom of the recess 7 is not exposed, and then the conductor 9 in the recess 7 may be exposed by reactive dry etching. According to this method, it is possible to selectively thin the material when the recess 7 is exposed, and it is possible to suppress breakage due to mechanical processing at the boundary between the conductor 9 and the capacitor substrate 2.
- a connection pad, a cover insulating film 18 and a solder bump 19 are formed on the other surface 2b side of the capacitor substrate 2 of the capacitor built-in element 12.
- the entire thickness of the electronic element 15 can be adjusted to a desired thickness by grinding the back side of the electronic element 15 (for example, the back side of the wafer on which the LSI is formed) in this state (electronic element). Thinning process).
- the I / O pad on the electronic device substrate (for example, LSI wafer) is in the same state as before the capacitor built-in device 12 is mounted, and as a circuit, a capacitor is formed between the power supply and the ground.
- the same test as the electrical test after the electronic element 15 is formed should be performed using the same test apparatus, the same probe card, etc. Is possible. Furthermore, even when the electronic device 15 alone is insufficient in decoupling capacity and a sufficient electrical test cannot be performed, it is possible to perform an electrical test of the electronic device 15 in a state where the decoupling capacitor is mounted. 2 good product selection process).
- the assembly of the capacitor built-in device 1 is separated into individual units by dicing so that the capacitor built-in device 1 in which the capacitor is built in the electronic device (for example, the capacitor decoupling capacitor and the LSI are integrated). (Semiconductor device) is obtained (capacitor built-in device singulation step; FIG. 1 (m), FIG. 5 (m)).
- the capacitor built-in device 1 is mounted on the circuit board 20 and the underfill resin 21 is filled between the capacitor built-in device 1 and the circuit board 20 to manufacture the capacitor built-in package 31 (capacitor built-in device mounting step; FIG. 1 (n), FIG. 5 (n)).
- a mounting method of the capacitor built-in device for example, a method similar to that of a normal semiconductor device mounting method or device can be adopted.
- a thin capacitor built-in device and capacitor built-in package can be obtained without going through a thin capacitor built-in element that is difficult to handle.
- non-defective capacitors with built-in capacitors and electronic elements can be combined, and more than one can be manufactured at the same time, so that devices with built-in capacitors and capacitors with built-in capacitors can be manufactured with high yield. Since the capacitor built-in element in a state where the conductor in the recess is not exposed is mounted on the electronic element, the same electrical test as before mounting the capacitor built-in element can be performed with the capacitor element mounted. Further, for mounting the capacitor built-in device on the circuit board, the same method and apparatus as those for mounting a normal electronic device can be used. Therefore, it is possible to improve manufacturability, productivity, quality reliability, and cost as compared with a method of manufacturing a capacitor built-in element as a discrete component.
- the bonding method between the capacitor built-in element 12 and the electronic element 15 and the bonding method between the capacitor built-in device 1 and the circuit board 20 are not limited to solder bumps, and for example, pads may be bonded directly.
- the material of the interlayer insulating film 8 and the cover insulating films 13 and 18 is not limited.
- inorganic insulating materials such as SiO 2 and Si 3 N 4 and resins such as polyimide and epoxy are preferable because they can be easily processed.
- FIGS. 6 and 7 are schematic process diagrams for explaining a method of manufacturing a capacitor built-in device and a capacitor built-in package according to the second embodiment of the present invention.
- 6 and 7 are schematic partial sectional views showing details of one unit of the capacitor built-in device.
- the capacitor built-in device using the insulating substrate and the method for manufacturing the capacitor built-in package have been described.
- the capacitor built-in device and the capacitor using a non-insulating substrate such as a semiconductor or metal are used.
- a method for manufacturing the built-in package will be described. This manufacturing method can also be applied to an insulating substrate.
- a capacitor 10 is formed on the capacitor substrate 2 and a recess 7 is formed (FIG. 6A).
- a first oxide such as a silicon oxide film is formed on the capacitor substrate 2 (including the inner wall of the recess 7) and the capacitor 10 using a CVD method or the like so that the conductor formed below and the capacitor substrate are not electrically connected.
- An interlayer insulating film 38 is formed (FIG. 6B).
- a contact hole 38a for forming an electrical connection with the lower electrode 3 or the upper electrode 5 is formed in the first interlayer insulating film 38 (FIG. 6C).
- connection pads 11 for electrical connection, electrical test of the capacitor 10, separation of the assembly of elements with built-in capacitors, formation of the cover insulating film 13 and the solder bumps 14 are performed (FIG. 6 (e)). .
- the built-in capacitor element 42 is mounted on the electronic element 15, the underfill resin 16 and the mold resin 17 are formed, and the capacitor substrate 2 is thinned. It implements (FIG.7 (f)).
- the capacitor substrate 2 is thinned, the capacitor substrate 2 is thinned at least until the conductor 9 in the recess 7 is exposed.
- a third insulating film 43 for insulating from the capacitor substrate 2 is formed, and a contact hole 43a for electrical connection with the conductor 9 in the recess 7 is formed in the third insulating film 43 (third insulating film). Film formation step; FIG. 7 (g)).
- the third insulating film 43 may be an inorganic material typified by SiO 2 or a resin, but if the same material as the first interlayer insulating film 38 covering the thin film capacitor 10 is used, the stress on the front and back of the capacitor substrate 2 is balanced. This is preferable in that the warpage of the sheet becomes small.
- the capacitor built-in device 41 is manufactured by forming the connection pad, the cover insulating film 18 and the solder bump 19 and separating the capacitor built-in device into individual pieces (FIG. 7 (h)).
- a capacitor built-in package can be manufactured by mounting the capacitor built-in device 41 on a circuit board (not shown).
- FIGS. 9 to 10 are schematic process diagrams for explaining a method for manufacturing a capacitor built-in device and a capacitor built-in package according to a third embodiment of the present invention.
- FIG. 8 is an overall schematic cross-sectional view of a method of manufacturing a capacitor built-in device and a capacitor built-in package according to the third embodiment of the present invention.
- FIGS. 9 to 10 are details of a unit of the capacitor built-in device in FIG. It is a general
- the alphabets indicating the process order shown in FIG. 8 and the alphabets indicating the process order shown in FIGS. 9 to 10 correspond to each other.
- the concave portion is formed in the capacitor substrate before the capacitor built-in element is mounted on the electronic device.
- the through hole is formed in the capacitor substrate. (Cavity) is formed.
- the capacitor 10 is formed on the capacitor substrate 2 in the same manner as in the first embodiment (capacitor forming step; FIGS. 8A and 9A).
- a capacitor built-in element 52 is formed in the same manner as in the first embodiment except that no recess is formed in the capacitor substrate 2 (interlayer insulating film forming process, conductor forming process, capacitor built-in element individualizing process) FIG. 8 (b) and FIG. 9 (b)).
- the capacitor built-in element 52 is mounted on the electronic element 15 to form the underfill resin 16 and the mold resin 17 (capacitor built-in element mounting process; FIGS. 8C to 8D). ), FIG. 9 (d)).
- the capacitor substrate 2 is thinned to a predetermined thickness (capacitor substrate thinning step; FIGS. 8E and 9E).
- a through hole 53 is formed in the capacitor substrate 2 so as to expose the conductor 9 in a region for electrical connection with the conductor 9 (through hole forming step; FIG. 8 (f), FIG. f)).
- a method for forming the through hole 53 a method similar to the method for forming a recess in the first embodiment can be used.
- a connection pad (through wiring) 54 is formed in the through hole 53 so as to be electrically connected to the conductor 9 (through hole conductor forming step; FIG. 10G).
- the capacitor built-in device 51 can be obtained by forming the cover insulating film 18 and the solder bump 19 and separating the assembly of the capacitor built-in device (single-capacitor device separation step). FIG. 8 (h) and FIG. 10 (h)).
- the capacitor built-in package 61 can be obtained by mounting the capacitor built-in device 51 on the circuit board 20 (FIG. 8I).
- the capacitor substrate can be made thinner than when the recess is present, for example, when mechanical grinding is used.
- the third embodiment has been described based on the first embodiment in which the capacitor substrate is an insulating substrate.
- the capacitor substrate in the third embodiment is a non-insulating substrate.
- a form similar to the third embodiment in which the through hole is formed after the capacitor substrate is thinned can be implemented based on the second embodiment.
- the main change is that the capacitor substrate is not electrically connected to the conductor and the connection pad.
- the third insulating film is also formed on the inner wall of the through hole.
- a semiconductor element for example, LSI
- LSI semiconductor element
- the present invention is particularly applicable to LSIs in general, and suppresses switching noises of LSIs in electronic devices such as computers, mobile phones, digital home appliances, and the like that are particularly required to operate at low voltage and high speed, thereby enabling stable operation. Can be applied.
- the disclosures of the aforementioned patent documents and the like are incorporated herein by reference.
- the embodiments and examples can be changed and adjusted based on the basic technical concept.
- Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.
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Abstract
Provided are a method for manufacturing highly efficiently a condenser-packaged device, in which a thin-type condenser having fine through viae are packaged not as discrete parts in an electronic device, and a method for manufacturing a condenser-packaged package, in which the condenser-packaged device is packaged in a circuit substrate. The condenser-packaged device manufacturing method comprises a step of forming a condenser in a condenser substrate, a step of forming a recess of such a depth in a predetermined region of the condenser substrate as does not extend through the condenser substrate, a step of forming an inter-layer insulatingfilm and a conductor (including a recess inside) on the condenser substrate and forming a condenser-packaged element by an individualization, a step of mounting the condenser-packaged element in an electronic element such that the condenser forming face of the condenser substrate and the electronic element may confront each other, a step of thinning the condenser substrate so that the conductor in the recess may be exposed to the outside, and a step of forming the condenser-packaged device by the individualization.
Description
［関連出願の記載］
本発明は、日本国特許出願：特願２００８－００２３４０号（２００８年 １月 ９日出願）の優先権主張に基づくものであり、同出願の全記載内容は引用をもって本書に組み込み記載されているものとする。
本発明は、電子装置にコンデンサを内蔵したコンデンサ内蔵装置（特に半導体装置）の製造方法及び該コンデンサ内蔵装置を回路基板に実装したコンデンサ内蔵パッケージの製造方法に関する。 [Description of related applications]
The present invention is based on the priority claim of Japanese patent application: Japanese Patent Application No. 2008-002340 (filed on Jan. 9, 2008), the entire description of which is incorporated herein by reference. Shall.
The present invention relates to a method for manufacturing a capacitor built-in device (particularly a semiconductor device) in which a capacitor is built in an electronic device, and a method for manufacturing a capacitor built-in package in which the capacitor built-in device is mounted on a circuit board.
本発明は、日本国特許出願：特願２００８－００２３４０号（２００８年 １月 ９日出願）の優先権主張に基づくものであり、同出願の全記載内容は引用をもって本書に組み込み記載されているものとする。
本発明は、電子装置にコンデンサを内蔵したコンデンサ内蔵装置（特に半導体装置）の製造方法及び該コンデンサ内蔵装置を回路基板に実装したコンデンサ内蔵パッケージの製造方法に関する。 [Description of related applications]
The present invention is based on the priority claim of Japanese patent application: Japanese Patent Application No. 2008-002340 (filed on Jan. 9, 2008), the entire description of which is incorporated herein by reference. Shall.
The present invention relates to a method for manufacturing a capacitor built-in device (particularly a semiconductor device) in which a capacitor is built in an electronic device, and a method for manufacturing a capacitor built-in package in which the capacitor built-in device is mounted on a circuit board.
半導体集積回路装置（ＬＳＩ）では、その作製プロセスの進展に従い、高速動作化と同時に電源電圧も低下しているために、ＬＳＩの安定動作のためにはトランジスタのスイッチングの際に生じるノイズ（スイッチングノイズ）の抑制が非常に重要な課題となっている。
In a semiconductor integrated circuit device (LSI), as the manufacturing process progresses, the power supply voltage is reduced at the same time as the high-speed operation. Therefore, for the stable operation of the LSI, noise generated during switching of the transistor (switching noise) ) Is a very important issue.
スイッチングに際して生じる電圧降下ΔＶは、一般的に下記の式（１）で示される。
△Ｖ＝－Ｌ×ｄｉ／ｄｔ・・・・・・（１）
ここで、ｄｉ／ｄｔはスイッチングによって回路を流れる負荷電流の時間変化、ＬはＬＳＩと電源装置との間の配線のインダクタンスである。 A voltage drop ΔV generated at the time of switching is generally expressed by the following equation (1).
ΔV = −L × di / dt (1)
Here, di / dt is the time change of the load current flowing through the circuit by switching, and L is the inductance of the wiring between the LSI and the power supply device.
△Ｖ＝－Ｌ×ｄｉ／ｄｔ・・・・・・（１）
ここで、ｄｉ／ｄｔはスイッチングによって回路を流れる負荷電流の時間変化、ＬはＬＳＩと電源装置との間の配線のインダクタンスである。 A voltage drop ΔV generated at the time of switching is generally expressed by the following equation (1).
ΔV = −L × di / dt (1)
Here, di / dt is the time change of the load current flowing through the circuit by switching, and L is the inductance of the wiring between the LSI and the power supply device.
そこで、ＬＳＩのスイッチングノイズ対策として、ΔＶを小さくするために、式（１）におけるＬが小さくなるようにＬＳＩと電源との間にはデカップリングコンデンサが配置されている。
Therefore, as a countermeasure against switching noise of the LSI, in order to reduce ΔV, a decoupling capacitor is arranged between the LSI and the power supply so that L in Expression (1) is reduced.
しかしながら、近年におけるＬＳＩの高集積化、ＧＨｚを越える高速動作化、そして低電圧化の進展に伴い、許容されるΔＶは減少し、ＬＳＩとデカップリングコンデンサとの間の配線のインダクタンスの影響も無視できなくなってきている。そこで、ＬＳＩとデカップリングコンデンサ間のインダクタンスが出来るだけ小さくなるように、デカップリングコンデンサを出来るだけＬＳＩの近傍に実装する実装構造が提案されている。例えば、特許文献１～４においては、インターポーザ型コンデンサを、ＬＳＩと回路基板との間乃至はＬＳＩ直下の回路基板表面内部へ配置して、ハンダバンプのみを介してＬＳＩと直接接続する実装構造が開示されている。
However, with the recent progress of higher integration of LSI, higher speed operation exceeding GHz, and lowering of voltage, allowable ΔV decreases, and the influence of inductance of wiring between LSI and decoupling capacitor is ignored. It is no longer possible. Therefore, a mounting structure has been proposed in which the decoupling capacitor is mounted as close to the LSI as possible so that the inductance between the LSI and the decoupling capacitor is as small as possible. For example, Patent Documents 1 to 4 disclose a mounting structure in which an interposer-type capacitor is disposed between an LSI and a circuit board or inside a circuit board surface immediately below the LSI and directly connected to the LSI only through solder bumps. Has been.
特許文献１～４に記載のインターポーザ型コンデンサの製造方法においては、貫通ビア（貫通配線）を形成した基板の一方の面上にキャパシタを形成したインターポーザ型コンデンサをディスクリート部品として製造している。製造したインターポーザ型コンデンサは、貫通配線の両端に形成した接続パッドにおいて半導体素子及び回路基板とハンダバンプを介して電気的に接続される。また、特許文献４に記載のインターポーザ型コンデンサの製造方法における貫通配線の形成においては、基板の、コンデンサを形成した一方の面にキャビティを形成し、キャビティにＣｕを埋め込んだ後、基板の他方の面側から基板を機械的に研削し、キャビティ底部のＣｕを露出させることにより基板ビア（貫通配線）を形成している。
In the method for manufacturing an interposer type capacitor described in Patent Documents 1 to 4, an interposer type capacitor in which a capacitor is formed on one surface of a substrate on which a through via (through wiring) is formed is manufactured as a discrete component. The manufactured interposer type capacitor is electrically connected to the semiconductor element and the circuit board via solder bumps at connection pads formed at both ends of the through wiring. Further, in the formation of the through wiring in the method of manufacturing the interposer type capacitor described in Patent Document 4, a cavity is formed on one surface of the substrate on which the capacitor is formed, Cu is embedded in the cavity, and then the other side of the substrate is formed. A substrate via (through wiring) is formed by mechanically grinding the substrate from the surface side to expose Cu at the bottom of the cavity.
以上の特許文献１～４の全開示内容は、本書に引用をもって繰り込み記載されているものとする。
以下の分析は本発明の観点から与えられる。 The entire disclosures ofPatent Documents 1 to 4 above are incorporated herein by reference.
The following analysis is given from the viewpoint of the present invention.
以下の分析は本発明の観点から与えられる。 The entire disclosures of
The following analysis is given from the viewpoint of the present invention.
特許文献１～４に記載のインターポーザ型コンデンサは、ディスクリート部品（単体）として製造されるので、製造時や実装時に取り扱いが容易となるような十分な厚さが必要となる。この取り扱い容易となる厚さは、ワーク又はウェハの大きさに依存することになるが、多数個同時に製造可能とすることを考慮するとインターポーザ型コンデンサ自体で、例えば２００μｍ以上の厚さが必要となる。インターポーザ型コンデンサは、例えば半導体素子と回路基板との間に挿入されるので、パッケージの厚さもインターポーザ型コンデンサの厚さの分だけ厚くなる。パッケージの厚さが厚くなれば、それが実装される機器の小型化及び薄型化に不利となる。
Since the interposer type capacitors described in Patent Documents 1 to 4 are manufactured as discrete components (single unit), a sufficient thickness is required so that they can be handled easily during manufacturing and mounting. The thickness that facilitates handling depends on the size of the workpiece or wafer. However, considering that it is possible to manufacture a large number of workpieces simultaneously, the interposer capacitor itself needs to have a thickness of, for example, 200 μm or more. . Since the interposer type capacitor is inserted, for example, between the semiconductor element and the circuit board, the thickness of the package also increases by the thickness of the interposer type capacitor. If the thickness of the package is increased, it is disadvantageous for downsizing and thinning of the device on which the package is mounted.
また、パッケージの信号線は、インターポーザ型コンデンサの厚さ分だけ長くなることになり、伝送損失の増加を引き起こす。更には、インターポーザ型コンデンサが必要となるようなＬＳＩの多くは１０００以上の多数かつ高密度なＩ／Ｏパッドを有するので、インターポーザ型コンデンサには５０μｍ径以下の微細な貫通ビア（配線）が必要となるが、インターポーザ型コンデンサの厚さが厚いと貫通ビアの径も大きくならざるを得ない（一般的に、貫通ビアのアスペクト比（深さ／ビア径）は約１である）。したがって、そのような微細な貫通ビアを、取り扱い容易となるような十分な厚さ有する基板を貫通するように形成することは困難である。
Also, the signal line of the package becomes longer by the thickness of the interposer type capacitor, causing an increase in transmission loss. Furthermore, many LSIs that require an interposer type capacitor have a large number of I / O pads of 1000 or more, and the interposer type capacitor requires fine through vias (wiring) with a diameter of 50 μm or less. However, if the thickness of the interposer type capacitor is thick, the diameter of the through via must be increased (in general, the aspect ratio (depth / via diameter) of the through via is about 1). Therefore, it is difficult to form such a fine through via so as to penetrate a substrate having a sufficient thickness so as to be easily handled.
一方、これらの問題点を解決するために、インターポーザ型コンデンサを薄くすると、今度は取り扱いが困難となり、インターポーザ型コンデンサの製造や実装を歩留りよく、低コストで実現できない問題が生じる。例えば、上記問題を解決できるような１００μｍ以下の厚さでインターポーザ型コンデンサを製造すると、機械的強度が弱くなり製造工程途中で破損することや、熱履歴や基板に積層する材料による反りが大きくなるために、インターポーザ型コンデンサを生産性良く製造及び実装することが困難となる。
On the other hand, if the interposer type capacitor is made thin in order to solve these problems, it will be difficult to handle this time, and there will be a problem that the production and mounting of the interposer type capacitor will not be realized at a low cost. For example, if an interposer type capacitor is manufactured with a thickness of 100 μm or less that can solve the above problem, the mechanical strength is weakened, and it is damaged during the manufacturing process, and the thermal history and warpage due to the material laminated on the substrate increase. For this reason, it is difficult to manufacture and mount the interposer type capacitor with high productivity.
また、コンデンサをディスクリート部品として作製しないで例えばＬＳＩと接続後に薄化する方法では、他にウェハ状態同士で接続するウェハ・オン・ウェハ、及びコンデンサが形成されたウェハ上に選別されたＬＳＩチップを実装する方法が考えられる。前者は、ＬＳＩとコンデンサを同形状のウェハで作製しなければならないことと、良品同士を選別して接続することができない欠点がある。後者は、良品同士の選別は可能であるが、ＬＳＩとコンデンサを一体化した後はコンデンサが形成されたウェハの形状でプロセスが実施されることになる。従って、この状態でＬＳＩのテストを行う場合には、ＬＳＩをダイシングする前のウェハ状態でのテストと同じテストをする場合でも、異なるプローブカードやテストプログラムを用意しなければならない欠点がある。
In addition, in the method of thinning the capacitor after being connected to the LSI without manufacturing the capacitor as a discrete component, for example, a wafer-on-wafer to be connected between wafer states, and an LSI chip selected on the wafer on which the capacitor is formed are used. Possible implementation methods. The former has the disadvantages that the LSI and the capacitor must be made of wafers of the same shape, and that good products cannot be selected and connected. In the latter case, the non-defective products can be selected, but after the LSI and the capacitor are integrated, the process is performed in the shape of the wafer on which the capacitor is formed. Therefore, when the LSI test is performed in this state, there is a drawback that a different probe card or test program must be prepared even when the same test as the wafer state test before dicing the LSI is performed.
本発明の目的は、ディスクリート部品としてではなく、微細貫通ビアを有する薄型コンデンサを電子装置に内蔵したコンデンサ内蔵装置を生産性良く製造する方法及び該コンデンサ内蔵装置を回路基板に実装したコンデンサ内蔵パッケージを製造する方法を提供することである。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a capacitor built-in device in which a thin capacitor having fine through vias is built in an electronic device, not as a discrete component, and a package with a built-in capacitor in which the capacitor built-in device is mounted on a circuit board. It is to provide a method of manufacturing.
本発明の第１視点によれば、電子素子にコンデンサ内蔵素子を実装したコンデンサ内蔵装置の製造方法であって、上部電極、誘電体及び下部電極を有する少なくとも１つのコンデンサを一単位として、コンデンサ基板の一方の面に、コンデンサを複数単位形成するコンデンサ形成工程と、コンデンサ基板の一方の面のコンデンサが形成されていない所定の領域に、コンデンサ基板を貫通しない所定の深さの少なくとも１つの凹部を形成する凹部形成工程と、コンデンサ基板の一方の面上に、層間絶縁膜を形成する層間絶縁膜形成工程と、凹部内を被覆ないし充填し、層間絶縁膜を貫通すると共に、上部電極及び下部電極のいずれかと電気的に接続された導電体を形成する導電体形成工程と、各工程によって形成されたコンデンサ内蔵素子の集合体をコンデンサ内蔵素子一単位毎に個片化するコンデンサ内蔵素子個片化工程と、導電体と電子素子とが電気的に接続するようにコンデンサ基板の一方の面を電子素子と対向させて複数のコンデンサ内蔵素子を電子素子にフリップチップ実装するコンデンサ内蔵素子実装工程と、凹部内の導電体が露出するようにコンデンサ基板を薄化するコンデンサ基板薄化工程と、各工程によって形成されたコンデンサ内蔵装置の集合体をコンデンサ内蔵素子一単位毎に個片化するコンデンサ内蔵装置個片化工程と、を含むコンデンサ内蔵装置の製造方法を提供する。
According to a first aspect of the present invention, there is provided a method of manufacturing a capacitor built-in device in which a capacitor built-in element is mounted on an electronic device, wherein at least one capacitor having an upper electrode, a dielectric and a lower electrode is used as a unit, and the capacitor substrate. A capacitor forming step of forming a plurality of capacitors on one surface of the capacitor, and at least one recess having a predetermined depth not penetrating the capacitor substrate in a predetermined region where the capacitor is not formed on one surface of the capacitor substrate. A recess forming step to be formed; an interlayer insulating film forming step of forming an interlayer insulating film on one surface of the capacitor substrate; and covering or filling the recess, penetrating the interlayer insulating film, and an upper electrode and a lower electrode A conductor forming step of forming a conductor electrically connected to any of the above, and a capacitor built-in element formed by each step Capacitor-embedded element singulation process that separates the unit into one unit of the capacitor-embedded element, and a plurality of capacitors with one surface facing the electronic element so that the conductor and the electronic element are electrically connected Capacitor-embedded element mounting process for flip-chip mounting of the capacitor-embedded element on the electronic element, capacitor substrate thinning process for thinning the capacitor board so that the conductor in the recess is exposed, and a capacitor built-in formed by each process There is provided a manufacturing method of a device with a built-in capacitor, including a device-with-capacitor device singulation step for separating a group of devices into units for each element with a built-in capacitor.
上記第１視点の好ましい形態によれば、コンデンサ内蔵装置の製造方法は、コンデンサ基板が非絶縁性である場合、層間絶縁膜形成工程において、コンデンサ基板と導電体が電気的に接続しないように層間絶縁膜を形成し、コンデンサ薄化工程後、凹部内の導電体が露出するように、コンデンサ基板の他方の面に絶縁膜を形成する絶縁膜形成工程をさらに含む。
According to a preferred embodiment of the first aspect described above, when the capacitor substrate is non-insulating, the method for manufacturing the capacitor-embedded device is configured so that the capacitor substrate and the conductor are not electrically connected in the interlayer insulating film forming step. An insulating film forming step is further included in which an insulating film is formed on the other surface of the capacitor substrate so that the conductor in the recess is exposed after the capacitor thinning step.
本発明の第２視点によれば、電子素子にコンデンサ内蔵素子を実装したコンデンサ内蔵装置の製造方法であって、上部電極、誘電体及び下部電極を有する少なくとも１つのコンデンサを一単位として、コンデンサ基板の一方の面に、コンデンサを複数単位形成するコンデンサ形成工程と、コンデンサ基板の一方の面上に、層間絶縁膜を形成する層間絶縁膜形成工程と、少なくとも一部が電子装置の一方の面のコンデンサが形成されていない所定の領域に接し、層間絶縁膜を貫通すると共に、上部電極及び下部電極のいずれかと電気的に接続された導電体を形成する導電体形成工程と、各工程によって形成されたコンデンサ内蔵素子の集合体をコンデンサ内蔵素子一単位毎に個片化するコンデンサ内蔵素子個片化工程と、導電体と電子素子とが電気的に接続するようにコンデンサ基板の一方の面を電子素子と対向させて複数のコンデンサ内蔵素子を電子素子にフリップチップ実装するコンデンサ内蔵素子実装工程と、コンデンサ基板を所定の厚さまで薄化するコンデンサ基板薄化工程と、所定の領域の導電体が露出するように、コンデンサ基板の他方の面からコンデンサ基板に少なくとも１つの貫通孔を形成する貫通孔形成工程と、導電体と電気的接続するように貫通孔を被覆ないし充填する貫通孔導電体を形成する貫通孔導電体形成工程と、各工程によって形成されたコンデンサ内蔵装置の集合体をコンデンサ内蔵素子一単位毎に個片化するコンデンサ内蔵装置個片化工程と、を含むコンデンサ内蔵装置の製造方法を提供する。
According to a second aspect of the present invention, there is provided a method of manufacturing a capacitor built-in device in which a capacitor built-in element is mounted on an electronic device, wherein at least one capacitor having an upper electrode, a dielectric and a lower electrode is used as a unit, and the capacitor substrate A capacitor forming step of forming a plurality of capacitors on one surface of the capacitor, an interlayer insulating film forming step of forming an interlayer insulating film on one surface of the capacitor substrate, and at least a part of one surface of the electronic device A conductor forming process for forming a conductor that is in contact with a predetermined region where a capacitor is not formed, penetrates the interlayer insulating film, and is electrically connected to either the upper electrode or the lower electrode, and is formed by each process. A process for separating a capacitor-integrated element into a unit of a capacitor-integrated element, and a conductor and an electronic element; Capacitor-embedded element mounting process for flip-chip mounting a plurality of capacitor-embedded elements on the electronic element with one surface of the capacitor substrate facing the electronic element so as to be electrically connected, and the capacitor substrate is thinned to a predetermined thickness Capacitor substrate thinning step, through-hole forming step of forming at least one through-hole in the capacitor substrate from the other surface of the capacitor substrate so that the conductor in a predetermined region is exposed, and electrical connection with the conductor A through-hole conductor forming step for forming a through-hole conductor for covering or filling the through-hole, and a capacitor built-in device that separates the assembly of capacitor built-in devices formed by each step into units for each capacitor built-in element A method for manufacturing a device with a built-in capacitor including a device dividing step.
上記第２視点の好ましい形態によれば、コンデンサ内蔵装置の製造方法は、コンデンサ基板が非絶縁性である場合、層間絶縁膜形成工程において、コンデンサ基板と導電体が電気的に接続しないように層間絶縁膜を形成し、貫通孔導電体形成工程前に、貫通孔内壁及びコンデンサ基板の他方の面に絶縁膜を形成する絶縁膜工程をさらに含む。
According to a preferred embodiment of the second aspect, when the capacitor substrate is non-insulating, the method for manufacturing the capacitor-embedded device is configured so that the capacitor substrate and the conductor are not electrically connected in the interlayer insulating film forming step. It further includes an insulating film step of forming an insulating film and forming an insulating film on the inner surface of the through hole and the other surface of the capacitor substrate before the through hole conductor forming step.
上記第１視点及び第２視点の好ましい形態によれば、コンデンサ基板薄化工程において、コンデンサ基板は、研削加工及びエッチング加工のうち少なくとも一方によって薄化される。
According to a preferred form of the first and second viewpoints, in the capacitor substrate thinning step, the capacitor substrate is thinned by at least one of grinding and etching.
上記第１視点及び第２視点の好ましい形態によれば、コンデンサ内蔵装置の製造方法は、コンデンサ内蔵装置個片化工程前に、電子素子を薄化する電子素子薄化工程をさらに含む。
According to a preferred form of the first and second viewpoints, the method for manufacturing a device with a built-in capacitor further includes an electronic element thinning step for thinning the electronic device before the step of separating the device with a built-in capacitor.
上記第１視点及び第２視点の好ましい形態によれば、コンデンサ内蔵装置の製造方法は、コンデンサ内蔵素子実装工程前に、コンデンサ内蔵素子及び電子素子を電気的に試験する第１良品選別工程をさらに含む。また、コンデンサ内蔵素子実装工程において、電子素子の不良領域及び電子素子の周縁領域が存在する場合には、少なくとも一方の領域には、コンデンサ内蔵素子ではなくダミーチップを実装する。
According to the preferred embodiments of the first and second aspects, the method for manufacturing a capacitor-embedded device further includes a first non-defective product selection step of electrically testing the capacitor-embedded element and the electronic element before the capacitor-embedded element mounting step. Including. In addition, in the capacitor built-in element mounting step, when there is a defective area of the electronic element and a peripheral area of the electronic element, a dummy chip is mounted in at least one area instead of the built-in capacitor element.
上記第１視点及び第２視点の好ましい形態によれば、コンデンサ内蔵装置の製造方法は、コンデンサ内蔵装置個片化工程前に、コンデンサ内蔵装置を電気的に試験する第２良品選別工程をさらに含む。
According to a preferred form of the first and second aspects, the method for manufacturing a capacitor built-in device further includes a second non-defective product selection step of electrically testing the capacitor built-in device before the capacitor built-in device individualization step. .
本発明の第３視点によれば、電子素子にコンデンサ内蔵素子を実装したコンデンサ内蔵装置を、回路基板に実装したコンデンサ内蔵パッケージの製造方法であって、上部電極、誘電体及び下部電極を有する少なくとも１つのコンデンサを一単位として、コンデンサ基板の一方の面に、コンデンサを複数単位形成するコンデンサ形成工程と、コンデンサ基板の一方の面のコンデンサが形成されていない所定の領域に、コンデンサ基板を貫通しない少なくとも１つの凹部を形成する凹部形成工程と、コンデンサ基板の一方の面上に、層間絶縁膜を形成する層間絶縁膜形成工程と、凹部内を被覆ないし充填し、層間絶縁膜を貫通すると共に、上部電極及び下部電極のいずれかと電気的に接続された導電体を形成する導電体形成工程と、各工程によって形成されたコンデンサ内蔵素子の集合体をコンデンサ内蔵素子一単位毎に個片化するコンデンサ内蔵素子個片化工程と、導電体と電子素子とが電気的に接続するようにコンデンサ基板の一方の面を電子素子と対向させて複数のコンデンサ内蔵素子を電子素子にフリップチップ実装するコンデンサ内蔵素子実装工程と、凹部内の導電体が露出するようにコンデンサ基板を薄化するコンデンサ基板薄化工程と、各工程によって形成されたコンデンサ内蔵装置の集合体をコンデンサ内蔵素子一単位毎に個片化するコンデンサ内蔵装置個片化工程と、導電体と回路基板とが電気的に接続するようにコンデンサ基板の他方の面を回路基板と対向させて、個片化されたコンデンサ内蔵装置を回路基板にフリップチップ実装するコンデンサ内蔵装置実装工程と、を含むコンデンサ内蔵パッケージの製造方法を提供する。
According to a third aspect of the present invention, there is provided a method for manufacturing a package with a built-in capacitor in which a device with a built-in capacitor mounted on an electronic device is mounted on a circuit board, the device including at least an upper electrode, a dielectric, and a lower electrode. Capacitor forming step of forming a plurality of units on one surface of the capacitor substrate, with one capacitor as a unit, and the capacitor substrate not penetrating into a predetermined region where the capacitor on one surface of the capacitor substrate is not formed A recess forming step for forming at least one recess, an interlayer insulating film forming step for forming an interlayer insulating film on one surface of the capacitor substrate, covering or filling the recess, penetrating the interlayer insulating film, A conductor forming process for forming a conductor electrically connected to either the upper electrode or the lower electrode, and The capacitor built-in element singulation process for dividing the assembly of capacitor built-in elements formed for each unit of the capacitor built-in element, and one of the capacitor substrates so that the conductor and the electronic element are electrically connected. A capacitor-embedded element mounting step for flip-chip mounting a plurality of capacitor-embedded elements on the electronic element with the surface facing the electronic element, and a capacitor substrate thinning step for thinning the capacitor substrate so that the conductor in the recess is exposed Capacitor board so that the assembly of the capacitor built-in device formed in each process is divided into individual units for each element with built-in capacitor, and the conductor and the circuit board are electrically connected Mounting the built-in capacitor device by flip-chip mounting the separated capacitor built-in device on the circuit board with the other side of the capacitor facing the circuit board To provide a method of manufacturing a capacitor built-in package comprising a degree, the.
本発明の第４視点によれば、電子素子にコンデンサ内蔵素子を実装したコンデンサ内蔵装置を、回路基板に実装したコンデンサ内蔵パッケージの製造方法であって、上部電極、誘電体及び下部電極を有する少なくとも１つのコンデンサを一単位として、コンデンサ基板の一方の面に、コンデンサを複数単位形成するコンデンサ形成工程と、コンデンサ基板の一方の面上に、層間絶縁膜を形成する層間絶縁膜形成工程と、少なくとも一部が電子装置の一方の面のコンデンサが形成されていない所定の領域に接し、層間絶縁膜を貫通すると共に、上部電極及び下部電極のいずれかと電気的に接続された導電体を形成する導電体形成工程と、各工程によって形成されたコンデンサ内蔵素子の集合体をコンデンサ内蔵素子一単位毎に個片化するコンデンサ内蔵素子個片化工程と、導電体と電子素子とが電気的に接続するようにコンデンサ基板の一方の面を電子素子と対向させて複数のコンデンサ内蔵素子を電子素子にフリップチップ実装するコンデンサ内蔵素子実装工程と、コンデンサ基板を所定の厚さまで薄化するコンデンサ基板薄化工程と、所定の領域の導電体が露出するように、コンデンサ基板の他方の面からコンデンサ基板に少なくとも１つの貫通孔を形成する貫通孔形成工程と、導電体と電気的接続するように貫通孔を被覆ないし充填する貫通孔導電体を形成する貫通孔導電体形成工程と、各工程によって形成されたコンデンサ内蔵装置の集合体をコンデンサ内蔵素子一単位毎に個片化するコンデンサ内蔵装置個片化工程と、貫通孔導電体と回路基板とが電気的に接続するようにコンデンサ基板の他方の面を回路基板と対向させて、個片化されたコンデンサ内蔵装置を回路基板にフリップチップ実装するコンデンサ内蔵装置実装工程と、を含むコンデンサ内蔵パッケージの製造方法を提供する。
According to a fourth aspect of the present invention, there is provided a method for manufacturing a package with a built-in capacitor in which a device with a built-in capacitor mounted on an electronic device is mounted on a circuit board. One capacitor as a unit, a capacitor forming step of forming a plurality of units on one surface of the capacitor substrate, an interlayer insulating film forming step of forming an interlayer insulating film on one surface of the capacitor substrate, and at least A part of the electronic device is in contact with a predetermined region where a capacitor is not formed, penetrates the interlayer insulating film, and forms a conductor electrically connected to either the upper electrode or the lower electrode. Body forming process and a set of capacitor built-in elements formed in each process into pieces for each unit of capacitor built-in elements. Capacitor for flip-chip mounting a plurality of capacitor built-in elements on the electronic element with one surface of the capacitor substrate facing the electronic element so that the conductor and the electronic element are electrically connected to each other. A built-in element mounting step, a capacitor substrate thinning step for thinning the capacitor substrate to a predetermined thickness, and at least one through hole in the capacitor substrate from the other surface of the capacitor substrate so that a conductor in a predetermined region is exposed. A through-hole conductor forming step for forming a through-hole conductor for covering or filling the through-hole so as to be electrically connected to the conductor, and a capacitor built-in device formed by each step Capacitor-embedded device singulation process that separates the assembly into individual capacitors-embedded elements, and the through-hole conductor and circuit board are electrically connected The other surface of the capacitor substrate by the circuit board facing, to provide a method of manufacturing a capacitor built-in package comprising a built-in capacitor device mounting step of flip-chip mounting a capacitor-containing apparatus which is sectioned in the circuit board, the.
本発明は、以下の効果のうち少なくとも１つを有する。
The present invention has at least one of the following effects.
本発明によれば、コンデンサ内蔵素子を、最終形態よりも厚くして、取り扱いが容易な厚さで実装等の処理を施すことができるので、工程途中の破損等を防止でき、コンデンサ内蔵装置及びコンデンサ内蔵パッケージの生産性及び品質信頼性を向上させることができる。
According to the present invention, since the capacitor built-in element can be made thicker than the final form and subjected to processing such as mounting with a thickness that is easy to handle, damage during the process can be prevented, and the capacitor built-in device and Productivity and quality reliability of the capacitor built-in package can be improved.
本発明によれば、コンデンサ内蔵素子の実装後、コンデンサ基板を所望の厚さまで薄化するので、より薄型のコンデンサ内蔵装置及びコンデンサ内蔵パッケージを製造することができる。例えば、コンデンサ内蔵素子部分の厚さを一方のハンダバンプの高さを含めても１００μｍ以下にすることができる。また、コンデンサ基板に形成する凹部ないし貫通孔の深さを浅くすることができるので、凹部ないし貫通孔の径を小さく抑えることができる。これにより、コンデンサ内蔵装置及びコンデンサ内蔵パッケージをより小型化することができる。例えば、凹部ないし貫通孔の径は５０μｍ以下にすることができる。また、電子素子が例えば半導体素子（例えばＬＳＩ）の場合、半導体素子の基板も薄化することによりコンデンサ内蔵装置及びコンデンサ内蔵パッケージをさらに薄型にすることができる。
According to the present invention, after mounting the capacitor built-in element, the capacitor substrate is thinned to a desired thickness, so that a thinner capacitor built-in device and a capacitor built-in package can be manufactured. For example, the thickness of the element part with a built-in capacitor can be set to 100 μm or less including the height of one solder bump. Moreover, since the depth of the recess or the through hole formed in the capacitor substrate can be reduced, the diameter of the recess or the through hole can be kept small. Thereby, the device with a built-in capacitor and the package with a built-in capacitor can be further downsized. For example, the diameter of the recess or the through hole can be set to 50 μm or less. Further, when the electronic element is, for example, a semiconductor element (for example, an LSI), the device with a built-in capacitor and the package with a built-in capacitor can be further reduced in thickness by thinning the substrate of the semiconductor element.
本発明によれば、コンデンサ内蔵素子はコンデンサ基板薄化前の状態であっても電気的試験を実施することができるので、コンデンサ内蔵素子実装前にコンデンサ内蔵素子及び電子素子の電気的試験を予め実施することにより、良品同士を組み合わせて、しかも複数個同時に実装することができる。これにより、コンデンサ内蔵装置及びコンデンサ内蔵パッケージの生産性を向上させることができる。また、電子素子にコンデンサ内蔵素子を実装した状態であっても、コンデンサ内蔵素子実装前後において電子素子のパッドの配置は変わらないので、コンデンサ内蔵素子実装前と同じ装置、同じ冶具、同じプログラムを用いた電子素子（例えばＬＳＩ）の電気的試験が可能となる。回路基板へのコンデンサ内蔵装置の実装時も電子素子単体と同様の取扱いで試験及び実装が可能となる。したがって、特別な電気的試験工程や試験設備は必要なく、低コストで生産性良くコンデンサ内蔵素子及びコンデンサ内蔵装置の実装を実施することができる。また、本発明によれば、コンデンサ内蔵素子と電子素子とを同一形状に形成する必要がない。
According to the present invention, since the capacitor built-in element can be subjected to an electrical test even before the capacitor substrate is thinned, the electrical test of the capacitor built-in element and the electronic element is performed in advance before mounting the capacitor built-in element. By carrying out, it is possible to combine non-defective products and mount a plurality of them simultaneously. Thereby, the productivity of the capacitor built-in device and the capacitor built-in package can be improved. In addition, even when the built-in capacitor element is mounted on the electronic element, the arrangement of the pads of the electronic element does not change before and after mounting the built-in capacitor element. Use the same equipment, jigs, and programs as before mounting the built-in capacitor element. It is possible to perform an electrical test on the electronic device (for example, LSI). When mounting a device with a built-in capacitor on a circuit board, testing and mounting can be performed with the same handling as an electronic device alone. Therefore, no special electrical test process or test equipment is required, and it is possible to implement the built-in capacitor element and the built-in capacitor device at low cost and high productivity. Further, according to the present invention, it is not necessary to form the capacitor built-in element and the electronic element in the same shape.
１ コンデンサ内蔵装置
２ コンデンサ基板
２ａ 一方の面
２ｂ 他方の面
３ 下部電極
４ 誘電体
５ 上部電極
６ レジスト
７ 凹部
８（８ａ，８ｂ） 層間絶縁膜
９ 導電体
１０ コンデンサ
１１ 接続パッド
１２ コンデンサ内蔵素子
１３ カバー絶縁膜
１４ ハンダバンプ
１５ 電子素子
１６ アンダーフィル樹脂
１７ モールド樹脂
１８ カバー絶縁膜
１９ ハンダバンプ
２０ 回路基板
２１ アンダーフィル樹脂
３１ コンデンサ内蔵パッケージ
３８ 第１層間絶縁膜
３８ａ コンタクトホール
３９ 第２層間絶縁膜
４１ コンデンサ内蔵装置
４２ コンデンサ内蔵素子
４３ 第３絶縁膜
４３ａ コンタクトホール
５１ コンデンサ内蔵装置
５２ コンデンサ内蔵素子
５３ 貫通孔
５４ 接続パッド
６１ コンデンサ内蔵パッケージ DESCRIPTION OFSYMBOLS 1 Capacitor built-in apparatus 2 Capacitor board 2a One side 2b The other side 3 Lower electrode 4 Dielectric 5 Upper electrode 6 Resist 7 Recess 8 (8a, 8b) Interlayer insulating film 9 Conductor 10 Capacitor 11 Connection pad 12 Capacitor built-in element 13 Cover insulating film 14 Solder bump 15 Electronic element 16 Underfill resin 17 Mold resin 18 Cover insulating film 19 Solder bump 20 Circuit board 21 Underfill resin 31 Built-in capacitor package 38 First interlayer insulating film 38a Contact hole 39 Second interlayer insulating film 41 Built-in capacitor Device 42 Capacitor built-in element 43 Third insulating film 43a Contact hole 51 Capacitor built-in device 52 Capacitor Built-in element 53 Through hole 54 Connection pad 61 Built-in capacitor package
２ コンデンサ基板
２ａ 一方の面
２ｂ 他方の面
３ 下部電極
４ 誘電体
５ 上部電極
６ レジスト
７ 凹部
８（８ａ，８ｂ） 層間絶縁膜
９ 導電体
１０ コンデンサ
１１ 接続パッド
１２ コンデンサ内蔵素子
１３ カバー絶縁膜
１４ ハンダバンプ
１５ 電子素子
１６ アンダーフィル樹脂
１７ モールド樹脂
１８ カバー絶縁膜
１９ ハンダバンプ
２０ 回路基板
２１ アンダーフィル樹脂
３１ コンデンサ内蔵パッケージ
３８ 第１層間絶縁膜
３８ａ コンタクトホール
３９ 第２層間絶縁膜
４１ コンデンサ内蔵装置
４２ コンデンサ内蔵素子
４３ 第３絶縁膜
４３ａ コンタクトホール
５１ コンデンサ内蔵装置
５２ コンデンサ内蔵素子
５３ 貫通孔
５４ 接続パッド
６１ コンデンサ内蔵パッケージ DESCRIPTION OF
本発明の第１実施形態に係るコンデンサ内蔵装置及びコンデンサ実装パッケージの製造方法について説明する。図１～図５に、本発明の第１実施形態に係るコンデンサ内蔵装置及びコンデンサ内蔵パッケージの製造方法を説明するための概略工程図を示す。図１は、本発明の第１実施形態に係るコンデンサ内蔵装置及びコンデンサ内蔵パッケージの製造方法における全体的な概略断面図であり、図２～図５は、図１におけるコンデンサ内蔵装置一単位の詳細を示す概略部分断面図である。なお、図１に示す工程順序を示すアルファベットと図２～図５に示す工程順序を示すアルファベットとは対応させてある。
A manufacturing method of the capacitor built-in device and the capacitor mounting package according to the first embodiment of the present invention will be described. 1 to 5 are schematic process diagrams for explaining a method of manufacturing a capacitor built-in device and a capacitor built-in package according to the first embodiment of the present invention. FIG. 1 is an overall schematic cross-sectional view of a method of manufacturing a capacitor built-in device and a capacitor built-in package according to the first embodiment of the present invention, and FIGS. 2 to 5 show details of one unit of the capacitor built-in device in FIG. It is a general | schematic fragmentary sectional view which shows. Note that the alphabets indicating the process order shown in FIG. 1 correspond to the alphabets indicating the process order shown in FIGS.
まず、ガラス等の絶縁性のコンデンサ基板を用いたコンデンサ内蔵装置及びコンデンサ内蔵パッケージの製造方法について説明する。ガラスなどの耐熱性のある材料で、取扱いが容易な厚さ（例えば、０．２ｍｍ以上、好ましくは０．５ｍｍ以上）の板状コンデンサ基板２の一方の面２ａ上に、下部電極３、誘電体４及び上部電極５から構成される少なくとも１つの薄膜コンデンサ１０を一単位として、少なくとも１つのコンデンサ１０を複数単位形成する（コンデンサ形成工程；図２（ａ））（図１においては、４つのコンデンサを１単位として、３単位のコンデンサ１０が形成されている）。一単位の詳細は、後に実装する電子素子内部の電源構成に応じて適宜設定する。取り扱いが容易となる好適なコンデンサ基板２の厚さは、コンデンサ基板２の厚さにも依存することになるが、例えば、直径約１００ｍｍ（４インチ）の場合０．５ｍｍ以上、直径約１５０ｍｍ（６インチ）の場合０．６ｍｍ以上、直径約２００ｍｍ（８インチ）の場合０．７ｍｍ以上であると好ましい。コンデンサ１０の下部電極３及び上部電極５の成膜方法は、限定されるものではないが、均一な金属膜や合金膜を堆積させることが容易なスパッタ法、化学的気相成長法（ＣＶＤ法）等が好ましい。誘電体４の成膜方法も限定されるものではないが、均一で絶縁性が良い酸化膜や窒化膜を低温で形成可能なスパッタ法、ＣＶＤ法、ゾルゲル法等が好ましい。また、電極３，５や誘電体膜４の加工、形成は、精度良い加工が可能なドライエッチングが好ましい。コンデンサ１０は、後に電子素子や回路基板との接続パッド間を結ぶ貫通配線が形成される領域には形成しない。
First, a method for manufacturing a capacitor built-in device and a capacitor built-in package using an insulating capacitor substrate such as glass will be described. On one surface 2a of the plate-like capacitor substrate 2 made of a heat-resistant material such as glass and having a thickness that is easy to handle (for example, 0.2 mm or more, preferably 0.5 mm or more), the lower electrode 3 and the dielectric A plurality of units of at least one capacitor 10 are formed using at least one thin film capacitor 10 composed of the body 4 and the upper electrode 5 as a unit (capacitor forming step; FIG. 2A) (in FIG. 3 units of capacitor 10 is formed with the capacitor as one unit). Details of one unit are set as appropriate according to the power supply configuration inside the electronic element to be mounted later. A suitable thickness of the capacitor substrate 2 that is easy to handle depends on the thickness of the capacitor substrate 2. For example, when the diameter is about 100 mm (4 inches), the thickness is about 0.5 mm or more and the diameter is about 150 mm ( 6 inches) is preferably 0.6 mm or more, and in the case of a diameter of about 200 mm (8 inches), 0.7 mm or more is preferable. The method of forming the lower electrode 3 and the upper electrode 5 of the capacitor 10 is not limited, but a sputtering method, a chemical vapor deposition method (CVD method), and the like, which are easy to deposit a uniform metal film or alloy film. Etc.) are preferred. A method for forming the dielectric 4 is not limited, but a sputtering method, a CVD method, a sol-gel method, or the like that can form a uniform and good insulating oxide film or nitride film at a low temperature is preferable. The electrodes 3 and 5 and the dielectric film 4 are preferably processed and formed by dry etching that enables accurate processing. The capacitor 10 is not formed in a region where a through wiring that connects connection pads to an electronic element or a circuit board is formed later.
コンデンサ基板２には、薄く高容量なコンデンサを形成するために、表面の平滑度が高く耐熱性高い材料を用いることが好ましく、例えばＳｉ、ＧａＡｓ等の半導体基板やガラス、サファイア、石英等の無機絶縁体基板を用いることが出来る。但し、これら材料に限定されるものではなく、表面を研磨したセラミックスや高耐熱性樹脂、或いは表面に絶縁層を形成した金属を用いることも可能である。なお、非絶縁性のコンデンサ基板２を用いる方法は第２実施形態において説明する。
The capacitor substrate 2 is preferably made of a material having high surface smoothness and high heat resistance in order to form a thin and high-capacity capacitor. For example, a semiconductor substrate such as Si or GaAs or an inorganic material such as glass, sapphire, or quartz. An insulator substrate can be used. However, it is not limited to these materials, and it is also possible to use a ceramic whose surface is polished, a high heat resistance resin, or a metal whose insulating layer is formed on the surface. A method using the non-insulating capacitor substrate 2 will be described in the second embodiment.
コンデンサ１０の誘電体４の材料は限定されるものではないが、比誘電率が高く薄膜化が可能で絶縁性良い材料が好ましく、例えば、酸化タンタル、酸化アルミニウム、酸化ハフニウム、酸化ジルコニウム、酸化シリコン、窒化シリコン、酸化チタンやペロブスカイト構造を有する高誘電率酸化物がより好ましい。ペロブスカイト構造を有する高誘電率酸化物としては、ＳｒＴｉＯ３、ＢａＴｉＯ３、ＰｂＴｉＯ３、ＳｒＢｉ２Ｔａ２Ｏ９、ＰｂＢｉ２Ｔａ２Ｏ９及びこれらの固溶体、或いはそれらのうちの少なくとも１つを主たる構成成分とした化合物が好ましい。コンデンサの電極３，５の材料も限定されないが、例えばＰｔ、Ｒｕ、Ｉｒ、ＴｉＮ等の高融点金属が好ましい。また、これら電極金属とコンデンサ基板２や後に形成する層間絶縁膜との密着性確保及び拡散防止のためにＴｉ、Ｃｒ、Ｔａ、Ｍｏなどを挿入した積層構造を形成するとより好ましい。
The material of the dielectric 4 of the capacitor 10 is not limited, but a material having a high relative dielectric constant and capable of being thinned and having good insulating properties is preferable. For example, tantalum oxide, aluminum oxide, hafnium oxide, zirconium oxide, silicon oxide High dielectric constant oxide having silicon nitride, titanium oxide or perovskite structure is more preferable. As a high dielectric constant oxide having a perovskite structure, SrTiO 3 , BaTiO 3 , PbTiO 3 , SrBi 2 Ta 2 O 9 , PbBi 2 Ta 2 O 9 and a solid solution thereof, or at least one of them are mainly composed. Compounds as components are preferred. The material of the electrodes 3 and 5 of the capacitor is not limited, but a high melting point metal such as Pt, Ru, Ir, or TiN is preferable. It is more preferable to form a laminated structure in which Ti, Cr, Ta, Mo or the like is inserted in order to ensure adhesion between the electrode metal and the capacitor substrate 2 or an interlayer insulating film to be formed later and to prevent diffusion.
次に、薄膜コンデンサ１０が形成されていない領域で、コンデンサ基板２の他方の面２ｂ側にパッドを形成する領域に対応するコンデンサ基板２の一方の面２ａの領域（後に回路基板と電気的に接続するためのコンタクトホールを形成する領域）が露出するように、コンデンサ基板２の一方の面２ａ上にレジスト６を形成する（図２（ｂ））。
Next, in a region where the thin film capacitor 10 is not formed, a region on one surface 2a of the capacitor substrate 2 corresponding to a region where a pad is formed on the other surface 2b side of the capacitor substrate 2 (later electrically with the circuit substrate). A resist 6 is formed on one surface 2a of the capacitor substrate 2 so that a region where a contact hole for connection is formed is exposed (FIG. 2B).
次に、ドライエッチング法等により、コンデンサ基板２の一方の面２ａに、コンデンサ基板２を貫通しない所定の深さの凹部（キャビティ）７を形成する（凹部形成工程；図１（ｃ）、図２（ｃ））。凹部７の深さは最終的なコンデンサ内蔵装置におけるコンデンサ基板２の厚さと少なくとも同等に設計する。凹部７の深さは限定されないが、最終的なコンデンサ内蔵装置やパッケージ全体の厚さ増加を抑え、信号配線の伝送損失を低減し、或いは貫通配線形成を容易にする等の観点から、凹部７の深さは浅いほうが好ましく、例えば好ましくは５０μｍ以下であり、より好ましくは２０μｍである。凹部７の形成方法は限定されないが、反応性ドライエッチング、ウェットエッチング、レーザ加工、サンドブラスト、ドリル加工等が好ましい。
Next, a recess (cavity) 7 having a predetermined depth not penetrating the capacitor substrate 2 is formed on one surface 2a of the capacitor substrate 2 by a dry etching method or the like (recess formation step; FIG. 1 (c), FIG. 2 (c)). The depth of the recess 7 is designed to be at least equal to the thickness of the capacitor substrate 2 in the final capacitor built-in device. The depth of the concave portion 7 is not limited, but the concave portion 7 can be formed from the viewpoint of suppressing the final increase in the thickness of the capacitor built-in device or the entire package, reducing the transmission loss of the signal wiring, or facilitating the formation of the through wiring. The depth of is preferably shallower, for example, preferably 50 μm or less, and more preferably 20 μm. Although the formation method of the recessed part 7 is not limited, Reactive dry etching, wet etching, laser processing, sandblasting, drilling, etc. are preferable.
次に、レジスト６を除去後、下部電極３、誘電体４及び上部電極５と導電体とを絶縁する領域を覆うように（下部電極３及び上部電極５と導電体とを電気的に接続する領域及び凹部７を露出するように）、コンタクトホールを有する層間絶縁膜８ａを感光性樹脂等で形成する（層間絶縁膜形成工程；図２（ｄ））。層間絶縁膜８ａの形成は、無機材料であればＣＶＤ法やゾルゲル法、樹脂であればスピンコート法が均一な絶縁膜の形成が容易で好ましい。コンタクトホールの形成方法は、層間絶縁膜８ａが無機材料や非感光性樹脂であればドライエッチング法、感光性樹脂であればフォトリソグラフィーが精度良い加工が可能で好ましい。
Next, after removing the resist 6, the lower electrode 3, the dielectric 4, and the upper electrode 5 are electrically connected so as to cover a region that insulates the conductor (the lower electrode 3 and the upper electrode 5 are electrically connected to the conductor). An interlayer insulating film 8a having a contact hole is formed of a photosensitive resin or the like so that the region and the recess 7 are exposed (interlayer insulating film forming step; FIG. 2D). The interlayer insulating film 8a is preferably formed by a CVD method or a sol-gel method if it is an inorganic material, or by a spin coating method if it is a resin, because it is easy to form a uniform insulating film. The contact hole is preferably formed by a dry etching method if the interlayer insulating film 8a is an inorganic material or a non-photosensitive resin, and photolithography is preferable if it is a photosensitive resin.
次に、層間絶縁膜を形成する領域にレジスト６を形成すると共に、凹部７、下部電極３、上部電極５及び層間絶縁膜８ａ上に、導電体９を形成する（導電体形成工程；図２（ｅ））。導電体９は、凹部７内に被覆されているか、又は凹部７内に充填されている。また、導電体９は、下部電極３及び上部電極５のいずれかと電気的に接続されている（それぞれ電子素子の電源又はグランドと接続可能にする）と共に、層間絶縁膜８ａを貫通するように形成されている。一単位内における下部電極３同士及び上部電極５同士（同種類の電極同士）はそれぞれ導電体９によって相互に電気的に接続されてもよい。導電体９の充填方法は限定されないが、メッキ法、印刷法、エアロゾルでポジション（ＡＤ）法などで導電体９を堆積させると、凹部７への導電体９の埋め込みも同時にできて好ましい。導電体９の材料は限定されないが、特に抵抗値が低く充填が容易なＣｕ、Ａｇ、又は、Ａｕ、或いはこれらを主たる成分とする合金がより好ましい。
Next, a resist 6 is formed in a region where an interlayer insulating film is to be formed, and a conductor 9 is formed on the recess 7, the lower electrode 3, the upper electrode 5, and the interlayer insulating film 8a (conductor forming step; FIG. 2). (E)). The conductor 9 is covered in the recess 7 or filled in the recess 7. In addition, the conductor 9 is electrically connected to either the lower electrode 3 or the upper electrode 5 (which can be connected to the power supply or ground of the electronic element, respectively) and is formed so as to penetrate the interlayer insulating film 8a. Has been. The lower electrodes 3 and the upper electrodes 5 (one electrode of the same type) in one unit may be electrically connected to each other by the conductor 9. The filling method of the conductor 9 is not limited, but it is preferable to deposit the conductor 9 by a plating method, a printing method, an aerosol by a position (AD) method or the like because the conductor 9 can be embedded in the recess 7 at the same time. The material of the conductor 9 is not limited, but Cu, Ag, Au, or an alloy containing these as main components is particularly preferable because it has a low resistance value and can be easily filled.
次に、層間絶縁膜８ｂを形成する（図３（ｆ））と共に、電子素子と電気的に接続するための接続パッド１１を形成する（図１（ｇ）、図３（ｇ））。
Next, an interlayer insulating film 8b is formed (FIG. 3 (f)), and a connection pad 11 for electrical connection with an electronic element is formed (FIG. 1 (g), FIG. 3 (g)).
次に、図１（ｇ）に示す状態において、電気的試験を実施して良品（合格品）を選別する（第１良品選別工程）。試験方法は限定されるものではないが、例えば、交流電流を用いたインピーダンスやそれに相当する物理量の測定や、直流低電圧のリーク電流測定などを行うことで良品を選別することが可能である。
Next, in the state shown in FIG. 1 (g), an electrical test is performed to select non-defective products (accepted products) (first non-defective product selection step). The test method is not limited. For example, it is possible to select non-defective products by measuring the impedance using an alternating current or a physical quantity corresponding to the impedance or measuring the leakage current of a direct current low voltage.
次に、コンデンサ内蔵素子１２の集合体を、電子素子に実装するコンデンサ内蔵素子一単位毎に個片化する（コンデンサ内蔵素子個片化工程；図１（ｈ））。次に、良品として選別されたコンデンサ内蔵素子１２にカバー絶縁膜１３及びハンダバンプ１４を形成し（図３（ｉ））、回路基板へ実装する単位を複数有する電子素子（例えば、基板（ウェハ）上に複数形成されたＬＳＩ）１５上に複数のコンデンサ内蔵素子１２をフリップチップ実装する（コンデンサ内蔵素子実装工程；図１（ｊ））。このとき、コンデンサ基板２の一方の面（コンデンサ１０形成面）２ａが電子素子１５と対向する。コンデンサ内蔵素子１２は、事前の電気的試験で良品と選別された電子素子単位に実装し、一部に不良品として選別された電子素子単位がある場合、不良電子素子上には、ダミーチップを実装する。ダミーチップは、良品コンデンサ内蔵素子ではなく、好ましくは、同サイズ同基板材料で形成されたもの（コンデンサ１０が形成されていないもの）である。また、コンデンサ内蔵素子１２を実装しない領域が大きい場合（例えば、ウェハ周縁部などでＬＳＩが形成されていない領域が大きい場合）にもダミーチップを実装しておく。これにより、電子素子全面には均等にコンデンサ又は同材料のダミーチップが搭載され、後の工程での薄化を均一に行うことができると共に、クラックなどの原因となる応力を特定箇所に集中しないようにすることができる。
Next, the aggregate of the capacitor built-in elements 12 is singulated for each unit of the capacitor built-in element mounted on the electronic element (capacitor built-in element individualization step; FIG. 1 (h)). Next, a cover insulating film 13 and a solder bump 14 are formed on the capacitor built-in element 12 selected as a non-defective product (FIG. 3 (i)), and an electronic element having a plurality of units to be mounted on a circuit board (for example, on a substrate (wafer)) A plurality of capacitor built-in elements 12 are flip-chip mounted on a plurality of LSIs 15 (capacitor built-in element mounting step; FIG. 1 (j)). At this time, one surface (capacitor 10 formation surface) 2 a of the capacitor substrate 2 faces the electronic element 15. The capacitor built-in element 12 is mounted in units of electronic elements that have been selected as non-defective products in a prior electrical test, and when there are electronic element units that have been selected as defective products, a dummy chip is placed on the defective electronic elements. Implement. The dummy chip is not a non-defective capacitor built-in element, but is preferably formed of the same size and the same substrate material (the capacitor 10 is not formed). A dummy chip is also mounted when a region where the capacitor built-in element 12 is not mounted is large (for example, when a region where an LSI is not formed is large at the wafer peripheral portion or the like). As a result, capacitors or dummy chips of the same material are evenly mounted on the entire surface of the electronic device, and the thinning in the subsequent process can be performed uniformly, and stress that causes cracks and the like is not concentrated on a specific location. Can be.
次に、コンデンサ内蔵素子１２と電子素子１５との間のハンダ接続部及びコンデンサ内蔵素子１２の周囲にアンダーフィル樹脂１６を充填する。これにより、後の工程において、破壊耐性や接続信頼性を向上させることができる。また、搭載されたコンデンサ内蔵素子１２及びダミーチップ間の隙間、並びにこれらが存在しない電子素子周縁部には、モールド樹脂１７を充填する（図１（ｋ）、図４（ｋ））。これにより、後の工程において、薄化の均一性や破壊耐性を一層改善することができる。
Next, an underfill resin 16 is filled in the solder connection portion between the capacitor built-in element 12 and the electronic element 15 and the periphery of the capacitor built-in element 12. Thereby, destruction tolerance and connection reliability can be improved in a later process. Further, a mold resin 17 is filled in the gap between the mounted capacitor built-in element 12 and the dummy chip, and the peripheral edge of the electronic element where these do not exist (FIG. 1 (k), FIG. 4 (k)). Thereby, it is possible to further improve the uniformity of thinning and the fracture resistance in the subsequent process.
次に、電子素子１５の基板（例えば、ＬＳＩが形成されたウェハ）を支持体として、少なくとも、凹部７内部に充填された導電体９が露出するまで、コンデンサ基板２を所定の厚さに薄化する（コンデンサ基板薄化工程；図１（ｌ）、図４（ｌ））。例えば、コンデンサ内蔵素子１２のコンデンサ基板２の他方の面２ｂ側を機械的に凹部７底部が露出するまで研削することができる。または、凹部７底部が露出しない程度に機械的な研削を施し、その後に反応性ドライエッチングで凹部７の導電体９を露出させてもよい。この方法によれば、凹部７の露出時に選択的に材料を薄化することが可能であり、導電体９とコンデンサ基板２との境界部における機械的加工による破壊などを抑制することができる。
Next, the capacitor substrate 2 is thinned to a predetermined thickness until at least the conductor 9 filled in the recess 7 is exposed using the substrate of the electronic element 15 (for example, a wafer on which an LSI is formed) as a support. (Capacitor substrate thinning step; FIG. 1 (l), FIG. 4 (l)). For example, the other surface 2b side of the capacitor substrate 2 of the capacitor built-in element 12 can be mechanically ground until the bottom of the recess 7 is exposed. Alternatively, mechanical grinding may be performed to such an extent that the bottom of the recess 7 is not exposed, and then the conductor 9 in the recess 7 may be exposed by reactive dry etching. According to this method, it is possible to selectively thin the material when the recess 7 is exposed, and it is possible to suppress breakage due to mechanical processing at the boundary between the conductor 9 and the capacitor substrate 2.
次に、コンデンサ内蔵素子１２のコンデンサ基板２の他方の面２ｂ側に、接続パッド、カバー絶縁膜１８及びハンダバンプ１９を形成する。また、必要であれば、この状態で電子素子１５の基板裏側（例えば、ＬＳＩが形成されたウェハ裏面）を研削して、全体の厚さを所望の厚さに調整することもできる（電子素子薄化工程）。また、このとき、電子素子の基板（例えば、ＬＳＩのウェハ）上のＩ／Ｏパッドは、コンデンサ内蔵素子１２の実装前と同じ状態にあり、回路としては電源とグランド間にコンデンサが形成された状態になっているので、電子素子１５形成後の電気的試験（例えば、ＬＳＩ形成後のウェハ状態における電気的試験）と全く同じテストを、同じテスト装置や同じプローブカード等を用いて実施することが可能となる。さらに、電子素子１５のみではデカップリング容量が足りず十分な電気的試験をできなかった場合でも、このデカップリングコンデンサが実装された状態における電子素子１５の電気的試験の実施が可能となる（第２良品選別工程）。
Next, a connection pad, a cover insulating film 18 and a solder bump 19 are formed on the other surface 2b side of the capacitor substrate 2 of the capacitor built-in element 12. If necessary, the entire thickness of the electronic element 15 can be adjusted to a desired thickness by grinding the back side of the electronic element 15 (for example, the back side of the wafer on which the LSI is formed) in this state (electronic element). Thinning process). At this time, the I / O pad on the electronic device substrate (for example, LSI wafer) is in the same state as before the capacitor built-in device 12 is mounted, and as a circuit, a capacitor is formed between the power supply and the ground. Therefore, the same test as the electrical test after the electronic element 15 is formed (for example, the electrical test in the wafer state after the LSI is formed) should be performed using the same test apparatus, the same probe card, etc. Is possible. Furthermore, even when the electronic device 15 alone is insufficient in decoupling capacity and a sufficient electrical test cannot be performed, it is possible to perform an electrical test of the electronic device 15 in a state where the decoupling capacitor is mounted. 2 good product selection process).
次に、コンデンサ内蔵装置１の集合体をダイシングで一単位毎に個片化することで、電子装置にコンデンサを内蔵したコンデンサ内蔵装置１（例えば、コンデンサデカップリングコンデンサとＬＳＩとが一体となった半導体装置）が得られる（コンデンサ内蔵装置個片化工程；図１（ｍ）、図５（ｍ））。
Next, the assembly of the capacitor built-in device 1 is separated into individual units by dicing so that the capacitor built-in device 1 in which the capacitor is built in the electronic device (for example, the capacitor decoupling capacitor and the LSI are integrated). (Semiconductor device) is obtained (capacitor built-in device singulation step; FIG. 1 (m), FIG. 5 (m)).
最後に、コンデンサ内蔵装置１を回路基板２０に実装し、コンデンサ内蔵装置１と回路基板２０との間にアンダーフィル樹脂２１を充填して、コンデンサ内蔵パッケージ３１を製造する（コンデンサ内蔵装置実装工程；図１（ｎ）、図５（ｎ））。コンデンサ内蔵装置１の実装方法は、例えば通常の半導体装置の実装方法や装置と同様の方法を採用することができる。
Finally, the capacitor built-in device 1 is mounted on the circuit board 20 and the underfill resin 21 is filled between the capacitor built-in device 1 and the circuit board 20 to manufacture the capacitor built-in package 31 (capacitor built-in device mounting step; FIG. 1 (n), FIG. 5 (n)). As a mounting method of the capacitor built-in device 1, for example, a method similar to that of a normal semiconductor device mounting method or device can be adopted.
本発明によれば、ハンドリングが困難な薄化したコンデンサ内蔵素子を経ることがなくても、薄型のコンデンサ内蔵装置及びコンデンサ内蔵パッケージを得ることができる。また、良品同士のコンデンサ内蔵素子と電子素子とを組み合わせることができ、しかも同時に複数製造できるので、コンデンサ内蔵装置及びコンデンサ内蔵パッケージを歩留まり良く製造することができる。凹部内の導電体が露出していない状態のコンデンサ内蔵素子を電子素子に実装するので、コンデンサ内蔵素子実装前と同様の電気的試験をコンデンサ素子を実装した状態で実施することができる。さらに、コンデンサ内蔵装置の回路基板への実装は、通常の電子装置の実装と同様の方法及び装置を使用することができる。したがって、コンデンサ内蔵素子をディスクリート部品として製造する方法と比較して、製造容易性、生産性、品質信頼性、コスト性を向上させることができる。
According to the present invention, a thin capacitor built-in device and capacitor built-in package can be obtained without going through a thin capacitor built-in element that is difficult to handle. In addition, non-defective capacitors with built-in capacitors and electronic elements can be combined, and more than one can be manufactured at the same time, so that devices with built-in capacitors and capacitors with built-in capacitors can be manufactured with high yield. Since the capacitor built-in element in a state where the conductor in the recess is not exposed is mounted on the electronic element, the same electrical test as before mounting the capacitor built-in element can be performed with the capacitor element mounted. Further, for mounting the capacitor built-in device on the circuit board, the same method and apparatus as those for mounting a normal electronic device can be used. Therefore, it is possible to improve manufacturability, productivity, quality reliability, and cost as compared with a method of manufacturing a capacitor built-in element as a discrete component.
コンデンサ内蔵素子１２と電子素子１５との接合方法及びコンデンサ内蔵装置１と回路基板２０との接合方法は、ハンダバンプに限定されず、例えばパッド同士を直接に接合してもよい。
The bonding method between the capacitor built-in element 12 and the electronic element 15 and the bonding method between the capacitor built-in device 1 and the circuit board 20 are not limited to solder bumps, and for example, pads may be bonded directly.
層間絶縁膜８やカバー絶縁膜１３，１８の材料は限定されないが、例えばＳｉＯ２、Ｓｉ３Ｎ４等の無機絶縁材料や、ポリイミド、エポキシ等の樹脂が加工も容易で好ましい。
The material of the interlayer insulating film 8 and the cover insulating films 13 and 18 is not limited. For example, inorganic insulating materials such as SiO 2 and Si 3 N 4 and resins such as polyimide and epoxy are preferable because they can be easily processed.
次に、本発明の第２実施形態に係るコンデンサ内蔵装置及びコンデンサ実装パッケージの製造方法について説明する。図６及び図７に、本発明の第２実施形態に係るコンデンサ内蔵装置及びコンデンサ内蔵パッケージの製造方法を説明するための概略工程図を示す。図６及び図７は、コンデンサ内蔵装置一単位の詳細を示す概略部分断面図である。第１実施形態においては絶縁性基板を用いたコンデンサ内蔵装置及びコンデンサ内蔵パッケージの製造方法について説明したが、本実施形態においては、半導体、金属等の非絶縁性基板を用いたコンデンサ内蔵装置及びコンデンサ内蔵パッケージの製造方法について説明する。なお、この製造方法は、絶縁性基板に対しても適用可能である。
Next, a method for manufacturing a capacitor built-in device and a capacitor mounting package according to a second embodiment of the present invention will be described. 6 and 7 are schematic process diagrams for explaining a method of manufacturing a capacitor built-in device and a capacitor built-in package according to the second embodiment of the present invention. 6 and 7 are schematic partial sectional views showing details of one unit of the capacitor built-in device. In the first embodiment, the capacitor built-in device using the insulating substrate and the method for manufacturing the capacitor built-in package have been described. In the present embodiment, the capacitor built-in device and the capacitor using a non-insulating substrate such as a semiconductor or metal are used. A method for manufacturing the built-in package will be described. This manufacturing method can also be applied to an insulating substrate.
まず、Ｓｉ等の非絶縁性のコンデンサ基板に、図２（ａ）～図２（ｃ）と同様にして、
コンデンサ基板２上にコンデンサ１０を形成すると共に、凹部７を形成する（図６（ａ））。次に、以下に形成する導電体とコンデンサ基板とが電気的に接続しないように、コンデンサ基板２（凹部７内壁含む）及びコンデンサ１０上に、ＣＶＤ法等を用いてシリコン酸化膜等の第１層間絶縁膜３８を形成する（図６（ｂ））。次に、下部電極３又は上部電極５と電気的接続と形成するためのコンタクトホール３８ａを第１層間絶縁膜３８に形成する（図６（ｃ））。次に、図２（ｅ）～図３（ｉ）と同様にして、導電体９の形成（図６（ｄ））、無機材料や樹脂等で第２層間絶縁膜３９の形成、電子素子と電気的に接続するための接続パッド１１の形成、コンデンサ１０の電気的試験、コンデンサ内蔵素子の集合体の個片化、カバー絶縁膜１３及びハンダバンプ１４の形成を実施する（図６（ｅ））。 First, on a non-insulating capacitor substrate such as Si, as in FIGS. 2 (a) to 2 (c),
Acapacitor 10 is formed on the capacitor substrate 2 and a recess 7 is formed (FIG. 6A). Next, a first oxide such as a silicon oxide film is formed on the capacitor substrate 2 (including the inner wall of the recess 7) and the capacitor 10 using a CVD method or the like so that the conductor formed below and the capacitor substrate are not electrically connected. An interlayer insulating film 38 is formed (FIG. 6B). Next, a contact hole 38a for forming an electrical connection with the lower electrode 3 or the upper electrode 5 is formed in the first interlayer insulating film 38 (FIG. 6C). Next, in the same manner as in FIGS. 2 (e) to 3 (i), formation of the conductor 9 (FIG. 6 (d)), formation of the second interlayer insulating film 39 with an inorganic material or resin, etc. Formation of connection pads 11 for electrical connection, electrical test of the capacitor 10, separation of the assembly of elements with built-in capacitors, formation of the cover insulating film 13 and the solder bumps 14 are performed (FIG. 6 (e)). .
コンデンサ基板２上にコンデンサ１０を形成すると共に、凹部７を形成する（図６（ａ））。次に、以下に形成する導電体とコンデンサ基板とが電気的に接続しないように、コンデンサ基板２（凹部７内壁含む）及びコンデンサ１０上に、ＣＶＤ法等を用いてシリコン酸化膜等の第１層間絶縁膜３８を形成する（図６（ｂ））。次に、下部電極３又は上部電極５と電気的接続と形成するためのコンタクトホール３８ａを第１層間絶縁膜３８に形成する（図６（ｃ））。次に、図２（ｅ）～図３（ｉ）と同様にして、導電体９の形成（図６（ｄ））、無機材料や樹脂等で第２層間絶縁膜３９の形成、電子素子と電気的に接続するための接続パッド１１の形成、コンデンサ１０の電気的試験、コンデンサ内蔵素子の集合体の個片化、カバー絶縁膜１３及びハンダバンプ１４の形成を実施する（図６（ｅ））。 First, on a non-insulating capacitor substrate such as Si, as in FIGS. 2 (a) to 2 (c),
A
次に、図４（ｋ）～（ｌ）と同様にして、作成したコンデンサ内蔵素子４２の電子素子１５への実装、アンダーフィル樹脂１６及びモールド樹脂１７の形成、及びコンデンサ基板２の薄化を実施する（図７（ｆ））。コンデンサ基板２の薄化においては少なくとも凹部７内の導電体９が露出するまで薄化する。次に、コンデンサ基板２と絶縁するための第３絶縁膜４３を形成し、凹部７内の導電体９と電気的接続するためのコンタクトホール４３ａを第３絶縁膜４３に形成する（第３絶縁膜形成工程；図７（ｇ））。第３絶縁膜４３はＳｉＯ２に代表される無機材料でも、樹脂でもかまわないが、薄膜コンデンサ１０を覆う第１層間絶縁膜３８と同材料にするとコンデンサ基板２表裏の応力が釣りあいコンデンサ基板２の反りが小さくなる点で好ましい。
Next, in the same manner as in FIGS. 4K to 4L, the built-in capacitor element 42 is mounted on the electronic element 15, the underfill resin 16 and the mold resin 17 are formed, and the capacitor substrate 2 is thinned. It implements (FIG.7 (f)). When the capacitor substrate 2 is thinned, the capacitor substrate 2 is thinned at least until the conductor 9 in the recess 7 is exposed. Next, a third insulating film 43 for insulating from the capacitor substrate 2 is formed, and a contact hole 43a for electrical connection with the conductor 9 in the recess 7 is formed in the third insulating film 43 (third insulating film). Film formation step; FIG. 7 (g)). The third insulating film 43 may be an inorganic material typified by SiO 2 or a resin, but if the same material as the first interlayer insulating film 38 covering the thin film capacitor 10 is used, the stress on the front and back of the capacitor substrate 2 is balanced. This is preferable in that the warpage of the sheet becomes small.
次に、図５（ｍ）と同様にして、接続パッド、カバー絶縁膜１８及びハンダバンプ１９の形成及びコンデンサ内蔵装置の個片化によって、コンデンサ内蔵装置４１を製造する（図７（ｈ））。また、図５（ｎ）と同様にして、コンデンサ内蔵装置４１を回路基板に実装してコンデンサ内蔵パッケージを製造することができる（不図示）。
Next, in the same manner as in FIG. 5 (m), the capacitor built-in device 41 is manufactured by forming the connection pad, the cover insulating film 18 and the solder bump 19 and separating the capacitor built-in device into individual pieces (FIG. 7 (h)). Similarly to FIG. 5 (n), a capacitor built-in package can be manufactured by mounting the capacitor built-in device 41 on a circuit board (not shown).
次に、本発明の第３実施形態に係るコンデンサ内蔵装置及びコンデンサ実装パッケージの製造方法について説明する。図８～図１０に、本発明の第３実施形態に係るコンデンサ内蔵装置及びコンデンサ内蔵パッケージの製造方法を説明するための概略工程図を示す。図８は、本発明の第３実施形態に係るコンデンサ内蔵装置及びコンデンサ内蔵パッケージの製造方法における全体的な概略断面図であり、図９～図１０は、図８におけるコンデンサ内蔵装置一単位の詳細を示す概略部分断面図である。なお、図８に示す工程順序を示すアルファベットと図９～図１０に示す工程順序を示すアルファベットとは対応させてある。
Next, a method for manufacturing a capacitor built-in device and a capacitor mounting package according to a third embodiment of the present invention will be described. 8 to 10 are schematic process diagrams for explaining a method for manufacturing a capacitor built-in device and a capacitor built-in package according to a third embodiment of the present invention. FIG. 8 is an overall schematic cross-sectional view of a method of manufacturing a capacitor built-in device and a capacitor built-in package according to the third embodiment of the present invention. FIGS. 9 to 10 are details of a unit of the capacitor built-in device in FIG. It is a general | schematic fragmentary sectional view which shows. The alphabets indicating the process order shown in FIG. 8 and the alphabets indicating the process order shown in FIGS. 9 to 10 correspond to each other.
第１実施形態においては、コンデンサ内蔵素子を電子素子に実装する前にコンデンサ基板に凹部を形成していたが、本実施形態においては、コンデンサ内蔵素子を電子素子に実装後、コンデンサ基板に貫通孔（キャビティ）を形成する。
In the first embodiment, the concave portion is formed in the capacitor substrate before the capacitor built-in element is mounted on the electronic device. However, in the present embodiment, after the capacitor built-in device is mounted on the electronic device, the through hole is formed in the capacitor substrate. (Cavity) is formed.
まず、コンデンサ基板２上に、第１実施形態と同様にしてコンデンサ１０を形成する（コンデンサ形成工程；図８（ａ）、図９（ａ））。次に、コンデンサ基板２に凹部を形成しない点以外は、第１実施形態と同様にして、コンデンサ内蔵素子５２を形成する（層間絶縁膜形成工程、導電体形成工程、コンデンサ内蔵素子個片化工程；図８（ｂ）、図９（ｂ））。次に、第１実施形態と同様にして、コンデンサ内蔵素子５２を電子素子１５に実装し、アンダーフィル樹脂１６及びモールド樹脂１７を形成する（コンデンサ内蔵素子実装工程；図８（ｃ）～（ｄ）、図９（ｄ））。次に、第１実施形態と同様にして、コンデンサ基板２を所定の厚さまで薄化する（コンデンサ基板薄化工程；図８（ｅ）、図９（ｅ））。
First, the capacitor 10 is formed on the capacitor substrate 2 in the same manner as in the first embodiment (capacitor forming step; FIGS. 8A and 9A). Next, a capacitor built-in element 52 is formed in the same manner as in the first embodiment except that no recess is formed in the capacitor substrate 2 (interlayer insulating film forming process, conductor forming process, capacitor built-in element individualizing process) FIG. 8 (b) and FIG. 9 (b)). Next, in the same manner as in the first embodiment, the capacitor built-in element 52 is mounted on the electronic element 15 to form the underfill resin 16 and the mold resin 17 (capacitor built-in element mounting process; FIGS. 8C to 8D). ), FIG. 9 (d)). Next, as in the first embodiment, the capacitor substrate 2 is thinned to a predetermined thickness (capacitor substrate thinning step; FIGS. 8E and 9E).
次に、導電体９と電気的接続をとるための領域に、導電体９を露出するようにコンデンサ基板２に貫通孔５３を形成する（貫通孔形成工程；図８（ｆ）、図１０（ｆ））。貫通孔５３の形成方法は、第１実施形態における凹部形成方法と同様の方法を利用することができる。次に、導電体９と電気的接続するように貫通孔５３に接続パッド（貫通配線）５４を形成する（貫通孔導電体形成工程；図１０（ｇ））。次に、第１実施形態と同様にして、カバー絶縁膜１８及びハンダバンプ１９の形成及びコンデンサ内蔵装置の集合体の個片化によってコンデンサ内蔵装置５１を得ることができる（コンデンサ内蔵装置個片化工程；図８（ｈ）、図１０（ｈ））。そして、第１実施形態と同様にして、コンデンサ内蔵装置５１を回路基板２０に実装することによりコンデンサ内蔵パッケージ６１を得ることができる（図８（ｉ））。
Next, a through hole 53 is formed in the capacitor substrate 2 so as to expose the conductor 9 in a region for electrical connection with the conductor 9 (through hole forming step; FIG. 8 (f), FIG. f)). As a method for forming the through hole 53, a method similar to the method for forming a recess in the first embodiment can be used. Next, a connection pad (through wiring) 54 is formed in the through hole 53 so as to be electrically connected to the conductor 9 (through hole conductor forming step; FIG. 10G). Next, in the same manner as in the first embodiment, the capacitor built-in device 51 can be obtained by forming the cover insulating film 18 and the solder bump 19 and separating the assembly of the capacitor built-in device (single-capacitor device separation step). FIG. 8 (h) and FIG. 10 (h)). In the same manner as in the first embodiment, the capacitor built-in package 61 can be obtained by mounting the capacitor built-in device 51 on the circuit board 20 (FIG. 8I).
本実施形態によれば、コンデンサ基板の薄化時に凹部が存在していないので、例えば機械的研削を用いたときに凹部が存在している場合よりもコンデンサ基板を薄化することができる。
According to the present embodiment, since the recess is not present when the capacitor substrate is thinned, the capacitor substrate can be made thinner than when the recess is present, for example, when mechanical grinding is used.
第３実施形態は、コンデンサ基板が絶縁性基板である第１実施形態を基に説明したが、第３実施形態におけるコンデンサ基板が非絶縁性基板である場合には、第４実施形態として、第２実施形態を基に、コンデンサ基板薄化後に貫通孔を形成する第３実施形態と同様の形態を実施できることは言うまでもない。主な変更点としては、コンデンサ基板と導電体及び接続パッドとが電気的に接続しないようにする。例えば、貫通孔形成後、貫通孔の内壁にも第３絶縁膜を形成するようにする。
The third embodiment has been described based on the first embodiment in which the capacitor substrate is an insulating substrate. However, when the capacitor substrate in the third embodiment is a non-insulating substrate, It goes without saying that a form similar to the third embodiment in which the through hole is formed after the capacitor substrate is thinned can be implemented based on the second embodiment. The main change is that the capacitor substrate is not electrically connected to the conductor and the connection pad. For example, after the through hole is formed, the third insulating film is also formed on the inner wall of the through hole.
本発明は、上記実施形態を基に説明したが、上記実施形態に限定されることなく、本発明の範囲内において種々の変更、変形、改良等を含むことはいうまでもない。また、本発明の範囲内において、開示した要素の多様な組み合わせ、置換ないし選択が可能である。
Although the present invention has been described based on the above embodiment, it is needless to say that the present invention is not limited to the above embodiment and includes various changes, modifications, improvements and the like within the scope of the present invention. Further, various combinations, substitutions or selections of the disclosed elements are possible within the scope of the present invention.
本発明のさらなる課題・目的及び展開形態は、特許請求の範囲を含む本発明の全開示事項からも明らかにされる。
Further problems / objects and development forms of the present invention will be made clear from the entire disclosure of the present invention including the claims.
本発明における電子素子としては半導体素子（例えばＬＳＩ）を利用することができるが、これに限定されることなく種々の電子素子を利用することができる。本発明は、特にＬＳＩ全般に適用できるものであるが、特に低電圧で高速動作が要求されるコンピュータ、携帯電話、デジタル家電等の電子装置におけるＬＳＩのスイッチングノイズを抑制して安定動作させることに適用することができる。
なお、前述の特許文献等の各開示を、本書に引用をもって繰り込むものとする。本発明の全開示（請求の範囲を含む）の枠内において、さらにその基本的技術思想に基づいて、実施形態ないし実施例の変更・調整が可能である。また、本発明の請求の範囲の枠内において種々の開示要素の多様な組み合わせないし選択が可能である。すなわち、本発明は、請求の範囲を含む全開示、技術的思想にしたがって当業者であればなし得るであろう各種変形、修正を含むことは勿論である。 A semiconductor element (for example, LSI) can be used as the electronic element in the present invention, but various electronic elements can be used without being limited thereto. The present invention is particularly applicable to LSIs in general, and suppresses switching noises of LSIs in electronic devices such as computers, mobile phones, digital home appliances, and the like that are particularly required to operate at low voltage and high speed, thereby enabling stable operation. Can be applied.
It should be noted that the disclosures of the aforementioned patent documents and the like are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.
なお、前述の特許文献等の各開示を、本書に引用をもって繰り込むものとする。本発明の全開示（請求の範囲を含む）の枠内において、さらにその基本的技術思想に基づいて、実施形態ないし実施例の変更・調整が可能である。また、本発明の請求の範囲の枠内において種々の開示要素の多様な組み合わせないし選択が可能である。すなわち、本発明は、請求の範囲を含む全開示、技術的思想にしたがって当業者であればなし得るであろう各種変形、修正を含むことは勿論である。 A semiconductor element (for example, LSI) can be used as the electronic element in the present invention, but various electronic elements can be used without being limited thereto. The present invention is particularly applicable to LSIs in general, and suppresses switching noises of LSIs in electronic devices such as computers, mobile phones, digital home appliances, and the like that are particularly required to operate at low voltage and high speed, thereby enabling stable operation. Can be applied.
It should be noted that the disclosures of the aforementioned patent documents and the like are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.
Claims (11)
- 電子素子にコンデンサ内蔵素子を実装したコンデンサ内蔵装置の製造方法であって、
上部電極、誘電体及び下部電極を有する少なくとも１つのコンデンサを一単位として、コンデンサ基板の一方の面に、前記コンデンサを複数単位形成するコンデンサ形成工程と、
前記コンデンサ基板の前記一方の面の前記コンデンサが形成されていない所定の領域に、前記コンデンサ基板を貫通しない所定の深さの少なくとも１つの凹部を形成する凹部形成工程と、
前記コンデンサ基板の前記一方の面上に、層間絶縁膜を形成する層間絶縁膜形成工程と、
前記凹部内を被覆ないし充填し、前記層間絶縁膜を貫通すると共に、前記上部電極及び前記下部電極のいずれかと電気的に接続された導電体を形成する導電体形成工程と、
前記各工程によって形成されたコンデンサ内蔵素子の集合体をコンデンサ内蔵素子一単位毎に個片化するコンデンサ内蔵素子個片化工程と、
前記導電体と前記電子素子とが電気的に接続するように前記コンデンサ基板の前記一方の面を前記電子素子と対向させて複数のコンデンサ内蔵素子を前記電子素子にフリップチップ実装するコンデンサ内蔵素子実装工程と、
前記凹部内の前記導電体が露出するように前記コンデンサ基板を薄化するコンデンサ基板薄化工程と、
前記各工程によって形成されたコンデンサ内蔵装置の集合体を前記コンデンサ内蔵素子一単位毎に個片化するコンデンサ内蔵装置個片化工程と、
を含むことを特徴とするコンデンサ内蔵装置の製造方法。 A method of manufacturing a device with a built-in capacitor in which an element with a built-in capacitor is mounted on an electronic device,
Forming at least one capacitor having an upper electrode, a dielectric and a lower electrode as a unit, and forming a plurality of units of the capacitor on one surface of the capacitor substrate; and
A recess forming step of forming at least one recess of a predetermined depth not penetrating the capacitor substrate in a predetermined region where the capacitor is not formed on the one surface of the capacitor substrate;
An interlayer insulating film forming step of forming an interlayer insulating film on the one surface of the capacitor substrate;
Covering or filling the recess, penetrating the interlayer insulating film, and forming a conductor electrically connected to either the upper electrode or the lower electrode; and
Capacitor-incorporated element singulation step for separating a set of capacitor-incorporated elements formed by the respective steps into units for each capacitor-incorporated element;
Capacitor-incorporated element mounting in which a plurality of capacitor-incorporated elements are flip-chip mounted on the electronic element with the one surface of the capacitor substrate facing the electronic element so that the conductor and the electronic element are electrically connected Process,
A capacitor substrate thinning step of thinning the capacitor substrate so that the conductor in the recess is exposed;
Capacitor built-in device singulation step for separating a unit of capacitor built-in devices formed by the respective steps into units for each capacitor built-in element;
The manufacturing method of the apparatus with a built-in capacitor | condenser characterized by the above-mentioned. - 前記コンデンサ基板が非絶縁性である場合、
前記層間絶縁膜形成工程において、前記コンデンサ基板と前記導電体が電気的に接続しないように層間絶縁膜を形成し、
前記コンデンサ薄化工程後、前記凹部内の前記導電体が露出するように、前記コンデンサ基板の前記他方の面に絶縁膜を形成する絶縁膜形成工程をさらに含むことを特徴とする請求項１に記載のコンデンサ内蔵装置の製造方法。 When the capacitor substrate is non-insulating,
In the interlayer insulating film forming step, an interlayer insulating film is formed so that the capacitor substrate and the conductor are not electrically connected,
2. The method according to claim 1, further comprising an insulating film forming step of forming an insulating film on the other surface of the capacitor substrate so that the conductor in the recess is exposed after the capacitor thinning step. The manufacturing method of the capacitor built-in apparatus of description. - 電子素子にコンデンサ内蔵素子を実装したコンデンサ内蔵装置の製造方法であって、
上部電極、誘電体及び下部電極を有する少なくとも１つのコンデンサを一単位として、コンデンサ基板の一方の面に、前記コンデンサを複数単位形成するコンデンサ形成工程と、
前記コンデンサ基板の前記一方の面上に、層間絶縁膜を形成する層間絶縁膜形成工程と、
少なくとも一部が前記電子装置の前記一方の面の前記コンデンサが形成されていない所定の領域に接し、前記層間絶縁膜を貫通すると共に、前記上部電極及び前記下部電極のいずれかと電気的に接続された導電体を形成する導電体形成工程と、
前記各工程によって形成されたコンデンサ内蔵素子の集合体をコンデンサ内蔵素子一単位毎に個片化するコンデンサ内蔵素子個片化工程と、
前記導電体と前記電子素子とが電気的に接続するように前記コンデンサ基板の前記一方の面を前記電子素子と対向させて複数のコンデンサ内蔵素子を前記電子素子にフリップチップ実装するコンデンサ内蔵素子実装工程と、
前記コンデンサ基板を所定の厚さまで薄化するコンデンサ基板薄化工程と、
前記所定の領域の前記導電体が露出するように、前記コンデンサ基板の他方の面から前記コンデンサ基板に少なくとも１つの貫通孔を形成する貫通孔形成工程と、
前記導電体と電気的接続するように前記貫通孔を被覆ないし充填する貫通孔導電体を形成する貫通孔導電体形成工程と、
前記各工程によって形成されたコンデンサ内蔵装置の集合体を前記コンデンサ内蔵素子一単位毎に個片化するコンデンサ内蔵装置個片化工程と、
を含むことを特徴とするコンデンサ内蔵装置の製造方法。 A method of manufacturing a device with a built-in capacitor in which an element with a built-in capacitor is mounted on an electronic device,
Forming at least one capacitor having an upper electrode, a dielectric and a lower electrode as a unit, and forming a plurality of units of the capacitor on one surface of the capacitor substrate; and
An interlayer insulating film forming step of forming an interlayer insulating film on the one surface of the capacitor substrate;
At least a portion of the electronic device is in contact with a predetermined region where the capacitor is not formed, penetrates the interlayer insulating film, and is electrically connected to either the upper electrode or the lower electrode. A conductor forming step for forming the conductor;
Capacitor-incorporated element singulation step for separating a set of capacitor-incorporated elements formed by the respective steps into units for each capacitor-incorporated element;
Capacitor-incorporated element mounting in which a plurality of capacitor-incorporated elements are flip-chip mounted on the electronic element with the one surface of the capacitor substrate facing the electronic element so that the conductor and the electronic element are electrically connected Process,
A capacitor substrate thinning step for thinning the capacitor substrate to a predetermined thickness;
A through hole forming step of forming at least one through hole in the capacitor substrate from the other surface of the capacitor substrate so that the conductor in the predetermined region is exposed;
A through hole conductor forming step of forming a through hole conductor that covers or fills the through hole so as to be electrically connected to the conductor;
Capacitor built-in device singulation step for separating a unit of capacitor built-in devices formed by the respective steps into units for each capacitor built-in element;
The manufacturing method of the apparatus with a built-in capacitor | condenser characterized by the above-mentioned. - 前記コンデンサ基板が非絶縁性である場合、
前記層間絶縁膜形成工程において、前記コンデンサ基板と前記導電体が電気的に接続しないように層間絶縁膜を形成し、
前記貫通孔導電体形成工程前に、前記貫通孔内壁及び前記コンデンサ基板の他方の面に絶縁膜を形成する絶縁膜工程をさらに含むことを特徴とする請求項３に記載のコンデンサ内蔵装置の製造方法。 When the capacitor substrate is non-insulating,
In the interlayer insulating film forming step, an interlayer insulating film is formed so that the capacitor substrate and the conductor are not electrically connected,
4. The device with a built-in capacitor according to claim 3, further comprising an insulating film step of forming an insulating film on the inner wall of the through hole and the other surface of the capacitor substrate before the through hole conductor forming step. Method. - 前記コンデンサ基板薄化工程において、前記コンデンサ基板は、研削加工及びエッチング加工のうち少なくとも一方によって薄化されることを特徴とする請求項１～４のいずれか一項に記載のコンデンサ内蔵装置の製造方法。 5. The method of manufacturing a capacitor built-in device according to claim 1, wherein, in the capacitor substrate thinning step, the capacitor substrate is thinned by at least one of grinding and etching. Method.
- 前記コンデンサ内蔵装置個片化工程前に、前記電子素子を薄化する電子素子薄化工程をさらに含むことを特徴とする請求項１～５のいずれか一項に記載のコンデンサ内蔵装置の製造方法。 6. The method for manufacturing a capacitor built-in device according to claim 1, further comprising an electronic element thinning step for thinning the electronic device before the individual capacitor built-in device separation step. .
- 前記コンデンサ内蔵素子実装工程前に、前記コンデンサ内蔵素子及び前記電子素子を電気的に試験する第１良品選別工程をさらに含むことを特徴とする請求項１～６のいずれか一項に記載のコンデンサ内蔵装置の製造方法。 7. The capacitor according to claim 1, further comprising a first non-defective product selection step of electrically testing the capacitor built-in element and the electronic element before the capacitor built-in element mounting step. A method for manufacturing a built-in device.
- 前記コンデンサ内蔵素子実装工程において、前記電子素子の不良領域及び前記電子素子の周縁領域が存在する場合には、少なくとも一方の領域には、前記コンデンサ内蔵素子ではなくダミーチップを実装することを特徴とする請求項１～７のいずれか一項に記載のコンデンサ内蔵装置の製造方法。 In the capacitor built-in element mounting step, when there is a defective area of the electronic element and a peripheral area of the electronic element, a dummy chip is mounted in at least one area instead of the capacitor built-in element. The method for manufacturing a device with a built-in capacitor according to any one of claims 1 to 7.
- 前記コンデンサ内蔵装置個片化工程前に、前記コンデンサ内蔵装置を電気的に試験する第２良品選別工程をさらに含むことを特徴とする請求項１～８のいずれか一項に記載のコンデンサ内蔵装置の製造方法。 9. The capacitor built-in device according to claim 1, further comprising a second non-defective product selection step for electrically testing the capacitor built-in device before the individual capacitor built-in device separation step. Manufacturing method.
- 電子素子にコンデンサ内蔵素子を実装したコンデンサ内蔵装置を、回路基板に実装したコンデンサ内蔵パッケージの製造方法であって、
上部電極、誘電体及び下部電極を有する少なくとも１つのコンデンサを一単位として、コンデンサ基板の一方の面に、前記コンデンサを複数単位形成するコンデンサ形成工程と、
前記コンデンサ基板の前記一方の面の前記コンデンサが形成されていない所定の領域に、前記コンデンサ基板を貫通しない少なくとも１つの凹部を形成する凹部形成工程と、
前記コンデンサ基板の前記一方の面上に、層間絶縁膜を形成する層間絶縁膜形成工程と、
前記凹部内を被覆ないし充填し、前記層間絶縁膜を貫通すると共に、前記上部電極及び前記下部電極のいずれかと電気的に接続された導電体を形成する導電体形成工程と、
前記各工程によって形成されたコンデンサ内蔵素子の集合体をコンデンサ内蔵素子一単位毎に個片化するコンデンサ内蔵素子個片化工程と、
前記導電体と前記電子素子とが電気的に接続するように前記コンデンサ基板の前記一方の面を前記電子素子と対向させて複数のコンデンサ内蔵素子を前記電子素子にフリップチップ実装するコンデンサ内蔵素子実装工程と、
前記凹部内の前記導電体が露出するように前記コンデンサ基板を薄化するコンデンサ基板薄化工程と、
前記各工程によって形成されたコンデンサ内蔵装置の集合体を前記コンデンサ内蔵素子一単位毎に個片化するコンデンサ内蔵装置個片化工程と、
前記導電体と前記回路基板とが電気的に接続するように前記コンデンサ基板の他方の面を前記回路基板と対向させて、個片化された前記コンデンサ内蔵装置を前記回路基板にフリップチップ実装するコンデンサ内蔵装置実装工程と、
を含むことを特徴とするコンデンサ内蔵パッケージの製造方法。 A method of manufacturing a package with a built-in capacitor in which a device with a built-in capacitor mounted on an electronic device is mounted on a circuit board.
Forming at least one capacitor having an upper electrode, a dielectric and a lower electrode as a unit, and forming a plurality of units of the capacitor on one surface of the capacitor substrate; and
A recess forming step of forming at least one recess not penetrating the capacitor substrate in a predetermined region where the capacitor is not formed on the one surface of the capacitor substrate;
An interlayer insulating film forming step of forming an interlayer insulating film on the one surface of the capacitor substrate;
Covering or filling the recess, penetrating the interlayer insulating film, and forming a conductor electrically connected to either the upper electrode or the lower electrode; and
Capacitor-incorporated element singulation step for separating a set of capacitor-incorporated elements formed by the respective steps into units for each capacitor-incorporated element;
Capacitor-incorporated element mounting in which a plurality of capacitor-incorporated elements are flip-chip mounted on the electronic element with the one surface of the capacitor substrate facing the electronic element so that the conductor and the electronic element are electrically connected Process,
A capacitor substrate thinning step of thinning the capacitor substrate so that the conductor in the recess is exposed;
Capacitor built-in device singulation step for separating a unit of capacitor built-in devices formed by the respective steps into units for each capacitor built-in element;
Flip-chip mounting the separated capacitor built-in device on the circuit board with the other surface of the capacitor board facing the circuit board so that the conductor and the circuit board are electrically connected Capacitor built-in device mounting process,
A method of manufacturing a package with a built-in capacitor, comprising: - 電子素子にコンデンサ内蔵素子を実装したコンデンサ内蔵装置を、回路基板に実装したコンデンサ内蔵パッケージの製造方法であって、
上部電極、誘電体及び下部電極を有する少なくとも１つのコンデンサを一単位として、コンデンサ基板の一方の面に、前記コンデンサを複数単位形成するコンデンサ形成工程と、
前記コンデンサ基板の前記一方の面上に、層間絶縁膜を形成する層間絶縁膜形成工程と、
少なくとも一部が前記電子装置の前記一方の面の前記コンデンサが形成されていない所定の領域に接し、前記層間絶縁膜を貫通すると共に、前記上部電極及び前記下部電極のいずれかと電気的に接続された導電体を形成する導電体形成工程と、
前記各工程によって形成されたコンデンサ内蔵素子の集合体をコンデンサ内蔵素子一単位毎に個片化するコンデンサ内蔵素子個片化工程と、
前記導電体と前記電子素子とが電気的に接続するように前記コンデンサ基板の前記一方の面を前記電子素子と対向させて複数のコンデンサ内蔵素子を前記電子素子にフリップチップ実装するコンデンサ内蔵素子実装工程と、
前記コンデンサ基板を所定の厚さまで薄化するコンデンサ基板薄化工程と、
前記所定の領域の前記導電体が露出するように、前記コンデンサ基板の他方の面から前記コンデンサ基板に少なくとも１つの貫通孔を形成する貫通孔形成工程と、
前記導電体と電気的接続するように前記貫通孔を被覆ないし充填する貫通孔導電体を形成する貫通孔導電体形成工程と、
前記各工程によって形成されたコンデンサ内蔵装置の集合体を前記コンデンサ内蔵素子一単位毎に個片化するコンデンサ内蔵装置個片化工程と、
前記貫通孔導電体と前記回路基板とが電気的に接続するように前記コンデンサ基板の前記他方の面を前記回路基板と対向させて、個片化された前記コンデンサ内蔵装置を前記回路基板にフリップチップ実装するコンデンサ内蔵装置実装工程と、
を含むことを特徴とするコンデンサ内蔵パッケージの製造方法。 A method of manufacturing a package with a built-in capacitor in which a device with a built-in capacitor mounted on an electronic device is mounted on a circuit board.
Forming at least one capacitor having an upper electrode, a dielectric and a lower electrode as a unit, and forming a plurality of units of the capacitor on one surface of the capacitor substrate; and
An interlayer insulating film forming step of forming an interlayer insulating film on the one surface of the capacitor substrate;
At least a portion of the electronic device is in contact with a predetermined region where the capacitor is not formed, penetrates the interlayer insulating film, and is electrically connected to either the upper electrode or the lower electrode. A conductor forming step for forming the conductor;
Capacitor-incorporated element singulation step for separating a set of capacitor-incorporated elements formed by the respective steps into units for each capacitor-incorporated element;
Capacitor-incorporated element mounting in which a plurality of capacitor-incorporated elements are flip-chip mounted on the electronic element with the one surface of the capacitor substrate facing the electronic element so that the conductor and the electronic element are electrically connected Process,
A capacitor substrate thinning step for thinning the capacitor substrate to a predetermined thickness;
A through hole forming step of forming at least one through hole in the capacitor substrate from the other surface of the capacitor substrate so that the conductor in the predetermined region is exposed;
A through hole conductor forming step of forming a through hole conductor that covers or fills the through hole so as to be electrically connected to the conductor;
Capacitor built-in device singulation step for separating a unit of capacitor built-in devices formed by the respective steps into units for each capacitor built-in element;
Flip the separated capacitor built-in device to the circuit board with the other surface of the capacitor board facing the circuit board so that the through-hole conductor and the circuit board are electrically connected. Mounting process of the device with built-in capacitor to be mounted on the chip,
A method of manufacturing a package with a built-in capacitor, comprising:
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